Log - 31715781c62f506875a7fea017aff64fdac643af - platform/external/mesa3d

477ea60 i965: Program 3DSTATE_AA_LINE_PARAMETERS in upload_invariant_state by Nanley Chery · 8 years ago
c30b716 i965/miptree: Remove the stencil_as_y_tiled parameter from get_aligned_offset by Jason Ekstrand · 8 years ago
0aa0b39 i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masks by Jason Ekstrand · 8 years ago
04f74d6 i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush. by Francisco Jerez · 8 years ago
83c6749 i965: Assert that a depth_mt exists when using HiZ. by Matt Turner · 8 years ago
b6f250d i965: Send the minimal number of STATE_BASE_ADDRESS packets. by Kenneth Graunke · 8 years ago
97179c6 i965: Combine Gen4-7 and Gen8+ state base address emitters. by Kenneth Graunke · 8 years ago
e9ca952 i965: Drop BRW_NEW_BLORP from stipple and line parameter packets. by Kenneth Graunke · 8 years ago
9e153c0 i965/blorp: Do not trigger re-emission of base state address by Topi Pohjolainen · 8 years ago
6d5ce1b i965: Make all atoms to track BRW_NEW_BLORP by default by Kenneth Graunke · 8 years ago
53739fd i965: Rename define for the PIPE_CONTROL DC flush bit. by Francisco Jerez · 9 years ago
0556b87 i965/gen7.5+: Disable resource streamer during GPGPU workloads. by Francisco Jerez · 9 years ago
c8df0e7 i965/gen7: Emit stall and dummy primitive draw after switching to the 3D pipeline. by Francisco Jerez · 9 years ago
635be14 i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines. by Francisco Jerez · 9 years ago
18c7655 i965/gen6-7: Implement stall and flushes required prior to switching pipelines. by Francisco Jerez · 9 years ago
044acb9 i965/gen8+: Invalidate color calc state when switching to the GPGPU pipeline. by Francisco Jerez · 9 years ago
dbae576 i965: add EXT_polygon_offset_clamp support to gen4/gen5 by Ilia Mirkin · 9 years ago
1dc41be i965: Use intel_get_tile_dims() to get tile masks by Anuj Phogat · 9 years ago
4e5752e i965: Always re-emit the pipeline select during invariant state emission by Chris Wilson · 9 years ago
0743376 i965: Trivial formatting changes in brw_misc_state.c by Ian Romanick · 9 years ago
c1da157 i965: Use float calculations when double is unnecessary. by Matt Turner · 9 years ago
4b35ab9 i965: Rename intel_emit* to reflect their new location in brw_pipe_control by Chris Wilson · 9 years ago
41b6db2 i965: Use _mesa_geometric_ functions appropriately by Kevin Rogovin · 9 years ago
0e0e23e i965/state: Emit pipeline select when changing pipelines by Jordan Justen · 9 years ago
4e56a9a i965/state: Don't use brw->state.dirty.brw by Jordan Justen · 10 years ago
aedcd46 i965/hiz: Start to separate miptree out from hiz buffers by Jordan Justen · 10 years ago
0b499ab i965: Do Sandybridge workaround flushes before each primitive. by Kenneth Graunke · 10 years ago
5f34a18 i965: Delete brw_state_flags::cache and related code. by Kenneth Graunke · 10 years ago
4f24c16 i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache). by Kenneth Graunke · 10 years ago
ce44b20 i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA. by Kenneth Graunke · 10 years ago
f421db7 i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE. by Kenneth Graunke · 10 years ago
bea9b8e i965: Alphabetize brw_tracked_state flags and use a consistent style. by Kenneth Graunke · 10 years ago
f14a35f i965: Always enable VF statistics by Ben Widawsky · 10 years ago
822e791 i965/skl: Set mask bits in PIPELINE_SELECT on Skylake. by Kenneth Graunke · 10 years ago
864c463 Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404 by Jordan Justen · 10 years ago
88e3d40 i965: Create a macro for setting a dirty bit. by Paul Berry · 11 years ago
56cdb55 i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface by Jordan Justen · 11 years ago
11bef60 i965: Move has_hiz from the slice to the level. by Eric Anholt · 10 years ago
e7f6565 i965: Delete the intel_regions.c code. by Eric Anholt · 10 years ago
e16c5c9 i965: Drop use of intel_region from miptrees. by Eric Anholt · 10 years ago
3033f80 i965: Move intel_region_get_aligned_offset() to be a miptree function. by Eric Anholt · 10 years ago
9791eb4 i965: Move intel_region_get_tile_masks() to be a miptree function. by Eric Anholt · 10 years ago
ac30e1a i965: Actually emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS. by Kenneth Graunke · 10 years ago
c10896b i965: Fix render-to-texture in non-FinishRenderTexture cases. by Eric Anholt · 11 years ago
09d9a89 i965: Pull format conversion logic out of brw_depthbuffer_format. by Kenneth Graunke · 11 years ago
a487ef8 mesa: Fix MESA_FORMAT_Z24_UNORM_S8_UINT vs. X8_UINT mix-up. by Kenneth Graunke · 11 years ago
eeed49f mesa: Change many Type P MESA_FORMATs to meet naming spec by Mark Mueller · 11 years ago
50a01d2 mesa: Change many Type A MESA_FORMATs to meet naming standard by Mark Mueller · 11 years ago
4c6a1d3 i965: Update invariant state for Broadwell. by Kenneth Graunke · 12 years ago
1c5e296 i965: Remove CACHED_BATCH support altogether. by Kenneth Graunke · 11 years ago
8771285 s/Tungsten Graphics/VMware/ by José Fonseca · 11 years ago
a7bdd4c i965: Drop trailing whitespace from the rest of the driver. by Kenneth Graunke · 11 years ago
c6a3fb6 i965: Use has_surface_tile_offset in depth/stencil alignment workaround. by Kenneth Graunke · 11 years ago
3aef1fe i965: Emit post-sync non-zero flush before 3DSTATE_DRAWING_RECTANGLE. by Kenneth Graunke · 11 years ago
fc5b865 i965: Remove has_aa_line_parameters. by Kenneth Graunke · 11 years ago
feaad18 i965: Move binding table code to a new file, brw_binding_tables.c. by Kenneth Graunke · 11 years ago
4b3c0a7 i965: Use brw_stage_state for WM data as well. by Kenneth Graunke · 11 years ago
ec94e3c i965: Move data from brw->vs into a base class if gs will also need it. by Paul Berry · 11 years ago
32e16e2 i965: rename legacy gs structs and functions to ff_gs. by Paul Berry · 11 years ago
e6893b9 i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2) by Ville Syrjälä · 11 years ago
2216198 i965/hsw: Populate MOCS for STATE_BASE_ADDRESS (v2) by Ville Syrjälä · 11 years ago
bf25ee2 gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface by Jordan Justen · 11 years ago
0e6be2e i965: init global state first in brw_workaround_depthstencil_alignment by Jordan Justen · 11 years ago
8c9a54e i965: Delete intel_context entirely. by Kenneth Graunke · 11 years ago
53631be i965: Move intel_context::gen and gt fields to brw_context. by Kenneth Graunke · 11 years ago
794de2f i965: Move intel_context::is_<platform> flags to brw_context. by Kenneth Graunke · 11 years ago
44fd490 i965: Move must_use/has_separate_stencil fields to brw_context. by Kenneth Graunke · 11 years ago
e3c2bb1 i965: Shorten context base class dereference chains. by Kenneth Graunke · 11 years ago
329779a i965: Move intel_context::batch to brw_context. by Kenneth Graunke · 11 years ago
e43043c i965: Move intel_context::vtbl to brw_context. by Kenneth Graunke · 11 years ago
ca43757 i965: Pass brw_context to functions rather than intel_context. by Kenneth Graunke · 11 years ago
adf8afa i965: NULL check depth_mt to quiet static analysis. by Matt Turner · 11 years ago
d671eb1 i965: Emit invariant state once at startup on Gen6+. by Kenneth Graunke · 11 years ago
64a87f2 i965: Kill software primitive counting entirely. by Kenneth Graunke · 11 years ago
75d402b i965/gen7: fix 3DSTATE_LINE_STIPPLE_PATTERN by Chia-I Wu · 11 years ago
28170c5 i965: Fix an unused variable warning in the release build. by Eric Anholt · 11 years ago
916d1ea i965: Remove brw_context::depthstencil::hiz_mt by Chad Versace · 11 years ago
2d3bbc5 intel: Replace checks for hiz_mt with intel_has*hiz() by Chad Versace · 11 years ago
5b79705 i965: Change signature of brw_get_depthstencil_tile_masks() by Chad Versace · 11 years ago
41e4bcc i965: Reduce code duplication in handling of depth, stencil, and HiZ. by Paul Berry · 11 years ago
0af56c9 i965: Avoid unnecessary copy when depthstencil workaround invoked by clear. by Paul Berry · 12 years ago
60894ed intel: Make intel_region's pitch be bytes instead of pixels. by Eric Anholt · 12 years ago
0d6a722 i965: Add perf debug for depth/stencil alignment workaround. by Eric Anholt · 12 years ago
c8ed9f6 i965/gen4-5: Fix segfaults with stencil-only depth/stencil setups. by Eric Anholt · 12 years ago
fdd6d14 i965: Use the separate stencil buffer's offsets for stencil setup. by Eric Anholt · 12 years ago
52ee1a7 i965: Move all the depth/stencil/hiz offset logic into the workaround. by Eric Anholt · 12 years ago
9ec6a54 i965: When rebasing depth or stencil, update x/y before deciding the other. by Eric Anholt · 12 years ago
56f8ed4 i965/gen4: Fix assertion failures in depthstencil piglit tests. by Eric Anholt · 12 years ago
7139ab8 i965: Fix rendering to small mipmaps of depth/stencil buffers using a temp mt. by Eric Anholt · 12 years ago
5c8dd6c i965: Share the draw x/y offset masking code between main/blorp and all gens. by Eric Anholt · 12 years ago
b760c99 intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset. by Paul Berry · 12 years ago
50dec7f intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks. by Paul Berry · 12 years ago
68216f3 i965/gen6+: Add support for fast depth clears. by Eric Anholt · 12 years ago
19e9b24 i965/gen6: Initial implementation of MSAA. by Paul Berry · 12 years ago
a683012 i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets. by Paul Berry · 12 years ago
3ec0e55 i965: Fix mipmap offsets for HiZ and separate stencil buffers. by Paul Berry · 12 years ago
4433b03 intel: use _mesa_is_winsys/user_fbo() helpers by Brian Paul · 12 years ago
a27c7d8 i965: Stop lying about cpp and height of a stencil buffer. by Paul Berry · 12 years ago
b2ace06 i965: Fix Gen6+ dynamic state upper bound on older kernels. by Kenneth Graunke · 13 years ago
5a7942c i965: Rename the original binding table to mention that it's the WM now. by Eric Anholt · 13 years ago