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gerrit-public.fairphone.software
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platform
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external
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mesa3d
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eddd5cb2fa36d6c8028296f8993bfeb2b1907693
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src
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mesa
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drivers
6973278
Android: drop Android 4.4 (KitKat) support
by Rob Herring
· 7 years ago
a8e217d
i965: Set kernel features before computing max GL version.
by Kenneth Graunke
· 7 years ago
05eb1c7
i965: Skip register write detection when possible.
by Kenneth Graunke
· 7 years ago
e7f872f
i965: Set screen->cmd_parser_version to 0 if we can't write registers.
by Kenneth Graunke
· 7 years ago
20319f5
i965: Document the sad story of the kernel command parser.
by Kenneth Graunke
· 7 years ago
29a7d73
i965/blorp: Bump the batch space estimate
by Jason Ekstrand
· 7 years ago
04df217
i965/blorp: Align vertex buffers to 64B
by Jason Ekstrand
· 7 years ago
f77cecf
i965/fs: Always provide a default LOD of 0 for TXS and TXL
by Jason Ekstrand
· 7 years ago
613e6e4
i965/fs: Don't emit SEL instructions for type-converting MOVs.
by Matt Turner
· 7 years ago
0ecda18
i965: Fall back to GL 4.2/4.3 on Haswell if the kernel isn't new enough.
by Kenneth Graunke
· 7 years ago
e504ecb
intel: Correct the BDW surface state size
by Nanley Chery
· 7 years ago
8a5684d
i965/gen8+: Do full stall when switching pipeline
by Topi Pohjolainen
· 7 years ago
7f7b116
i965: move brw_define.h ifndef guard to the top
by Emil Velikov
· 7 years ago
ea7711f
i965/fs: emit MOV_INDIRECT with the source with the right register type
by Samuel Iglesias Gonsálvez
· 7 years ago
e1e27b0
i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handles
by Samuel Iglesias Gonsálvez
· 7 years ago
59e6c0d
i965/fs: fix indirect load DF uniforms on BSW/BXT
by Samuel Iglesias Gonsálvez
· 7 years ago
7d3a10c
i965/fs: detect different bit size accesses to uniforms to push them in proper locations
by Samuel Iglesias Gonsálvez
· 7 years ago
d4caa4249
i965/fs: mark last DF uniform array element as 64 bit live one
by Samuel Iglesias Gonsálvez
· 7 years ago
e7a8f2e
intel/blorp: Explicitly flush all allocated state
by Jason Ekstrand
· 7 years ago
e1ba82d
i965/fs: fix uninitialized memory access
by Lionel Landwerlin
· 7 years ago
a594bd1
i965/fs: Fix the inline nir_op_pack_double optimization
by Jason Ekstrand
· 7 years ago
1db3ceb
i965/sampler_state: Set the "Base Mip Level" field on Sandy Bridge
by Jason Ekstrand
· 8 years ago
bcd58a9
i965/sampler_state: Pass texObj into update_sampler_state
by Jason Ekstrand
· 8 years ago
d5859cb
i965/sampler_state: Clamp min/max LOD to 14 on gen7+
by Jason Ekstrand
· 8 years ago
05abd64
Revert "i965: Disable guardband clipping in the smaller-than-viewport case."
by Kenneth Graunke
· 8 years ago
0946822
i965: Always scissor on Gen6-7.5 instead of disabling guardband.
by Kenneth Graunke
· 8 years ago
d44a881
i965: Use a better guardband calculation.
by Jason Ekstrand
· 8 years ago
726c327
i965: Combine the Gen6 SF and Clip viewport atoms.
by Kenneth Graunke
· 8 years ago
cdc5bb8
dri/common: clear the loaderPrivate pointer in driDestroyDrawable
by Nicolai Hähnle
· 8 years ago
06b9bc6
i965: Support the force_glsl_version driconf option.
by Kenneth Graunke
· 8 years ago
270597d
i965: Fix check for negative pitch in can_do_fast_copy_blit().
by Kenneth Graunke
· 8 years ago
671dfe5
i965: Unbind deleted shaders from brw_context, fixing malloc heisenbug.
by Kenneth Graunke
· 8 years ago
27e7e7e
dri/osmesa: automake: include builddir prior to srcdir
by Emil Velikov
· 8 years ago
3919fee
dri/swrast: automake: include builddir prior to srcdir
by Emil Velikov
· 8 years ago
6ee9468
radeon, r200: automake: include builddir prior to srcdir
by Emil Velikov
· 8 years ago
042b344
i915: automake: include builddir prior to srcdir
by Emil Velikov
· 8 years ago
0a1ad5c
i965: automake: include builddir prior to srcdir
by Emil Velikov
· 8 years ago
c22ee80
i965: automake: correctly set MKDIR_GEN
by Emil Velikov
· 8 years ago
2554c98
i965: Make intelEmitCopyBlit not truncate large strides.
by Kenneth Graunke
· 8 years ago
3171578
i965: Use a UW source type for CS_OPCODE_CS_TERMINATE.
by Kenneth Graunke
· 8 years ago
dcb3b24
i965: Fix fast depth clears for surfaces with a dimension of 16384.
by Kenneth Graunke
· 8 years ago
450f6aa
i965/blorp: Use the correct ISL format for combined depth/stencil
by Jason Ekstrand
· 8 years ago
d940b91
i965/blorp: Add also depth and stencil buffers to render cache
by Topi Pohjolainen
· 8 years ago
9577977
i965/blorp: Make post draw flush more explicit
by Topi Pohjolainen
· 8 years ago
8621961
i965/gen6: Issue direct depth stall and flush after depth clear
by Topi Pohjolainen
· 8 years ago
7d5a98f
i965: Make depth clear flushing more explicit
by Topi Pohjolainen
· 8 years ago
4e6445c
i965/blorp: Use the render cache mechanism instead of explicit flushing
by Topi Pohjolainen
· 8 years ago
5b4a531
i965: Make brw_cache_item structure private to brw_program_cache.c.
by Kenneth Graunke
· 8 years ago
b0cc55f
i965: Fix SURFACE_STATE to handle non-zero aux offsets
by Ben Widawsky
· 8 years ago
aa291c3
i965: Don't map/unmap in brw_print_program_cache on LLC platforms.
by Kenneth Graunke
· 8 years ago
ce89239
i965: Move program cache printing to brw_program_cache.c.
by Kenneth Graunke
· 8 years ago
f9edc55
i965: Make a helper for finding an existing shader variant.
by Kenneth Graunke
· 8 years ago
9919542
i965: Make DCE set null destinations on messages with side effects.
by Kenneth Graunke
· 8 years ago
90bf39c
i965: Combine some dead code elimination NOP'ing code.
by Kenneth Graunke
· 8 years ago
be5f53e
i965: Make DCE explicitly not eliminate any control flow instructions.
by Kenneth Graunke
· 8 years ago
7a2b65a
i965: Make BLORP disable the NP Z PMA stall fix.
by Kenneth Graunke
· 8 years ago
d2590eb
i965: Enable OpenGL 4.5 on Haswell.
by Kenneth Graunke
· 8 years ago
5597b2b
i965: Use align1 mode for barrier messages.
by Kenneth Graunke
· 8 years ago
0d5071d
i965: Move Gen4-5 interpolation stuff to brw_wm_prog_data.
by Kenneth Graunke
· 8 years ago
56ee2df
i965/vec4: Fix mapping attributes
by Juan A. Suarez Romero
· 8 years ago
99c019e
i965: Fix textureGather with RG32I/UI on Gen7.
by Kenneth Graunke
· 8 years ago
dc18ec8
xlib: Unify the style of function pointer calls in structs
by Boyan Ding
· 9 years ago
2d05425
radeon: Unify the style of function pointer calls in structs
by Boyan Ding
· 9 years ago
056cfa5
nouveau: Unify the style of function pointer calls in structs
by Boyan Ding
· 9 years ago
3698d71
i915: Add XRGB8888 format to intel_screen_make_configs
by Derek Foreman
· 8 years ago
ce44501
nir/i965: assert first is always less than 64
by Juan A. Suarez Romero
· 8 years ago
75968a6
i965/gen7: expose OpenGL 4.2 on Haswell when supported
by Juan A. Suarez Romero
· 8 years ago
7707798
i965: enable ARB_shader_precision to HSW+
by Samuel Iglesias Gonsálvez
· 8 years ago
1d1ddba
i965: unify the code to enable of ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit for HSW+
by Samuel Iglesias Gonsálvez
· 8 years ago
485955b
i965: Enable ARB_vertex_attrib_64bit for Haswell
by Alejandro Piñeiro
· 8 years ago
6bb4255
i965: check for dual slot attributes on any gen
by Juan A. Suarez Romero
· 8 years ago
f51a5b5
i965/vec4: emit correctly load_inputs for 64bit data
by Juan A. Suarez Romero
· 8 years ago
58fdb85
i965/vec4: take into account doubles when creating attribute mapping
by Alejandro Piñeiro
· 8 years ago
57bab67
i965/vec4/nir: vec4 also needs to remap vs attributes
by Alejandro Piñeiro
· 8 years ago
f831018
i965/vec4: use attribute slots for first non payload GRF
by Alejandro Piñeiro
· 8 years ago
329cbe3
i965: downsize *64*PASSTHRU formats to equivalent *32*FLOAT formats on gen < 8
by Alejandro Piñeiro
· 8 years ago
717f99b
i965: return PASSTHRU surface types also on gen7
by Alejandro Piñeiro
· 8 years ago
ea7e4b1
i965: Enable predicate support on gen >= 8.
by Rafael Antognolli
· 8 years ago
b4c44ff
i965: Use the nir_move_comparisons pass.
by Kenneth Graunke
· 8 years ago
b5e682a
i965: Move nir_lower_locals_to_regs a bit later.
by Kenneth Graunke
· 8 years ago
5edc338
compiler: Merge shader_info's tcs and tes structs.
by Kenneth Graunke
· 8 years ago
2bae2fa
i965: Fix number of slots in SSO mode when there are no user varyings.
by Kenneth Graunke
· 8 years ago
c2acf97
nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes
by Juan A. Suarez Romero
· 8 years ago
8b43f42
i965: call intel_prepare_render always when reading pixels
by Tapani Pälli
· 8 years ago
86b9be7
i965: Move TES input VUE map calculation out a layer.
by Kenneth Graunke
· 8 years ago
6e8ac06
i965: Pass NULL for gl_program when compiling TES.
by Kenneth Graunke
· 8 years ago
08f8f1b
i965: Move TES spacing/domain/topology setup to brw_compile_tes().
by Kenneth Graunke
· 8 years ago
cc2df4b
i965: Access TES shader info via NIR.
by Kenneth Graunke
· 8 years ago
a4fd84e
mesa: Introduce a compiler enum for tessellation spacing.
by Kenneth Graunke
· 8 years ago
9bb8917
compiler: Change shader_info->tes.vertex_order into a ccw boolean.
by Kenneth Graunke
· 8 years ago
5a165b4
drirc: Allow extension midshader for Divinity: Original Sin (EE)
by Kai Wasserbäch
· 8 years ago
45912fb
i965/compiler: Use the new nir_opt_copy_prop_vars pass
by Jason Ekstrand
· 8 years ago
e6ae199
i965: Rework gl_TessLevel*[] handling to use NIR compact arrays.
by Kenneth Graunke
· 8 years ago
31d9de5
i965: Inline store_output helper in quads workaround code.
by Kenneth Graunke
· 8 years ago
496693d
i965: Make unify_interfaces not spread VARYING_BIT_TESS_LEVEL_*.
by Kenneth Graunke
· 8 years ago
1472ff3
i965: Enable several GLES 3.1 extensions on HSW+
by Ian Romanick
· 8 years ago
90c51cc
i965: Always set MaxViewports and related limits
by Ian Romanick
· 8 years ago
2138347
i965: Properly flush in hsw_pause_transform_feedback().
by Kenneth Graunke
· 8 years ago
4295af6
i965: Fix texturing in the vec4 TCS and GS backends.
by Kenneth Graunke
· 8 years ago
a4d6f4d
i965: Don't set EmitNoMainReturn.
by Kenneth Graunke
· 8 years ago
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