Log - f8e6d19f3f40931be741b44d3edf210c38e13f0f - platform/external/mesa3d

116680d i965: Remove all bits of NRM3 and NRM4 code by Ian Romanick · 13 years ago
6571c07 Merge branch 'kasanen-post-process-v2' by Brian Paul · 13 years ago
4990e7e radeon: Fix flushing before writing a teximage's BO when !t->bo. by Eric Anholt · 13 years ago
7dae1aa intel: use new gl_texture_image:Face, Level fields by Brian Paul · 13 years ago
0d63621 i965: Only map the necessary buffer range in brw_prepare_indices by Ian Romanick · 13 years ago
28249bd mesa: Eliminate dd_function_table::MapBuffer by Ian Romanick · 13 years ago
cccc741 radeon: Hack up an implementation of MapBufferRange by Ian Romanick · 13 years ago
b2184da mesa: Fix incorrect access parameter passed to MapBuffer by Ian Romanick · 13 years ago
6183edc mesa: Remove target parameter from dd_function_table::FlushMappedBufferRange by Ian Romanick · 13 years ago
f973be5 intel: Correctly check for read-only mappings in intel_bufferobj_map_range by Ian Romanick · 13 years ago
4ddae2f mesa: Remove target parameter from dd_function_table::MapBufferRange by Ian Romanick · 13 years ago
6c8aa34 mesa: Remove target parameter from dd_function_table::GetBufferSubData by Ian Romanick · 13 years ago
92f3fca mesa: Remove target parameter from dd_function_table::BufferSubData by Ian Romanick · 13 years ago
12d924c mesa: Remove target parameter from dd_function_table::MapBuffer by Ian Romanick · 13 years ago
56f0c00 mesa: Remove target parameter from dd_function_table::UnmapBuffer by Ian Romanick · 13 years ago
abbb8fc i965: Fix typo in 2b224d66a01f3ce867fb05558b25749705bbfe7a by Eric Anholt · 13 years ago
9d4b98e i965/gen6+: Use non-normalized coordinates for GL_TEXTURE_RECTANGLE. by Eric Anholt · 13 years ago
4eeb4c1 i965: Implement textureSize (TXS) on Gen4. by Kenneth Graunke · 13 years ago
ecf8963 i965/fs: Implement textureSize (TXS) on Gen5+. by Kenneth Graunke · 13 years ago
b6bdcf2 i965/fs: Rudimentary support for non-floating point texture results. by Kenneth Graunke · 13 years ago
1e3bcbd glsl: Add a new ir_txs (textureSize) opcode to ir_texture. by Kenneth Graunke · 14 years ago
6959528 intel: Abort when DRI2 separate stencil handshake fails by Chad Versace · 13 years ago
f7d2dca i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables. by Kenneth Graunke · 13 years ago
e98ee06 i965/fs: Don't double-convert integer/boolean uniforms. by Kenneth Graunke · 13 years ago
eb86bb5 i965/fs: Change incorrect use of 'struct fs_reg' to simply 'fs_reg'. by Kenneth Graunke · 13 years ago
f4db755 i965/vs: Implement proper register allocation instead of 1:1 mapping. by Eric Anholt · 13 years ago
8174945 i965/vs: Add simple dead code elimination. by Eric Anholt · 13 years ago
3dadc1e i965/vs: Copy the live intervals calculation over from the FS. by Eric Anholt · 13 years ago
eb5454f i965/vs: Remove stale comment about compressed instructions. by Eric Anholt · 13 years ago
6a6441f driconf: Add the PP descriptions by Lauri Kasanen · 13 years ago
3f78f71 i965/fs: Fix 32-bit integer multiplication. by Eric Anholt · 13 years ago
59e5695 xmlpool.h: fix a typo by Lauri Kasanen · 13 years ago
b629d5b xmlconfig: Make the error message more informative by Lauri Kasanen · 13 years ago
0ddf0f1 i965/vs: Fix multiplies to actually do 32-bit multiplies. by Eric Anholt · 13 years ago
7bf70c2 i965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg. by Eric Anholt · 13 years ago
e9a86ae i965/vs: Fix memory leak of ralloc context for the visitor. by Eric Anholt · 13 years ago
feff7c6 i965/vs: Fix condition code for scalar expression all_equals. by Eric Anholt · 13 years ago
8a64927 i965/vs: Don't assertion fail on vertex texturing. by Eric Anholt · 13 years ago
d0c595a i965/gen6: Force WHILE exec size to 8. by Eric Anholt · 13 years ago
905f3d0 i965/vs: Remove remaining use of foreach_iter. by Eric Anholt · 13 years ago
54e66a0 i965/vs: Fix abs/negate handling on attributes. by Eric Anholt · 13 years ago
7642c1d i965/vs: Avoid generating a MOV for most ir_assignment handling. by Eric Anholt · 13 years ago
7fbe7fe i965/vs: Run the shader backend at link time and return compile failures. by Eric Anholt · 13 years ago
d376fa8 i965: Fix assertion failure on a loop consisting of while (true) { break }. by Eric Anholt · 13 years ago
e8980c6 i965/vs: Fix the trivial register allocator's failure path. by Eric Anholt · 13 years ago
193a9a2 i965/vs: Add support for if(any(bvec)) on gen6. by Eric Anholt · 13 years ago
072d641 i965/vs: Add support for GL_FIXED attributes. by Eric Anholt · 13 years ago
aed5e35 i965/vs: Clamp vertex color outputs when required by ARB_color_buffer_float. by Eric Anholt · 13 years ago
a55fbbc i965/vs: Fix access of attribute arrays. by Eric Anholt · 13 years ago
fea7d34 i965/vs: Fix builtin uniform setup. by Eric Anholt · 13 years ago
0b359e3 i965/vs: Add support for loops. by Eric Anholt · 13 years ago
abf843a i965/vs: Add support for ir_binop_pow. by Eric Anholt · 13 years ago
250770b i965/vs: Respect the gen6 limitation that math opcodes can't be align16. by Eric Anholt · 13 years ago
6408b02 i965/vs: Fix implementation of ir_unop_any. by Eric Anholt · 13 years ago
7b91eef i965/vs: Slightly improve the trivial reg allocator to skip unused regs. by Eric Anholt · 13 years ago
e94bdbe i965: Add gen6 disassembly for DP render cache messages. by Eric Anholt · 13 years ago
54fa706 i965/vs: Enable variable array indexing in the VS. by Eric Anholt · 13 years ago
584ff40 i965/vs: Add support for scratch read/write codegen. by Eric Anholt · 13 years ago
0f22f98 i965: Make some EU emit code for DP read/write messages non-static. by Eric Anholt · 13 years ago
d0e4d71 i965/vs: Move virtual GRFs with array accesses to them to scratch space. by Eric Anholt · 13 years ago
758c3c2 i965/vs: Reserve MRF 14/15 for array loads/register unspilling. by Eric Anholt · 13 years ago
1ff4f11 i965/vs: Track the variable index of array accesses. by Eric Anholt · 13 years ago
314c257 i965: Add remaining scratch space setup emit to unit states. by Eric Anholt · 13 years ago
2b224d6 i965: Set up allocation of a VS scratch space if required. by Eric Anholt · 13 years ago
e355b17 i965: Remove dead brw->wm.max_threads field. by Eric Anholt · 13 years ago
160a5a3 i965/vs: Add support for VUEs larger than a single URB write. by Eric Anholt · 13 years ago
31ef2e3 i965/vs: Avoid generating extra moves when setting up large ir_constants. by Eric Anholt · 13 years ago
aba9801 i965/vs: Fix types of varying outputs. by Eric Anholt · 13 years ago
9790726 i965/vs: Handle assignment of structures/arrays/matrices better. by Eric Anholt · 13 years ago
930afd1 i965/vs: Don't forget to set up assignment condition code for arrays/structs. by Eric Anholt · 13 years ago
cda28bc i965/vs: Apply the gen6 math workaround for math1 instructions. by Eric Anholt · 13 years ago
2b7632a i965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6. by Eric Anholt · 13 years ago
c3752b3 i965/vs: Add support for dot product opcodes. by Eric Anholt · 13 years ago
8e947c2 i965/vs: Fix the types of array/struct dereferences. by Eric Anholt · 13 years ago
814a9be i965/vs: Drop the assertion about dst.reg_offset == 0. by Eric Anholt · 13 years ago
e5363c7 i965/vs: Use an appropriate swizzle on src regs from variables. by Eric Anholt · 13 years ago
eca762d i965/vs: Fix support for zero uniforms in use. by Eric Anholt · 13 years ago
164ccd2 i965/vs: Fix support for "IF" instructions by copying brw_fs_visitor.cpp. by Eric Anholt · 13 years ago
aa753c5 i965/vs: Disable loops for now until rendering is generally correct. by Eric Anholt · 13 years ago
bb468fc i965/vs: Fix ir_swizzle handling. by Eric Anholt · 13 years ago
78fac18 i965/vs: Allocate storage for "auto" variables just like temps. by Eric Anholt · 13 years ago
82aa929 i965/vs: Allow scalar values in assignments, too. by Eric Anholt · 13 years ago
c0f334a i965/vs: Don't emit an extra copy of the vertex position. by Eric Anholt · 13 years ago
4a48572 i965/vs: Port the fix for clip plane writemasks from brw_vs_emit.c. by Eric Anholt · 13 years ago
83d5850 i965/vs: Fix constant vector construction. by Eric Anholt · 13 years ago
a070d5f i965/vs: Start adding support for uniforms by Eric Anholt · 14 years ago
af3c980 i965: Start adding the VS visitor and codegen. by Eric Anholt · 14 years ago
65b5cbb i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*. by Eric Anholt · 13 years ago
6034b9a i965: Create a shared enum for hardware and compiler-internal opcodes. by Eric Anholt · 14 years ago
c1f0073 i965: Generate driver-specific IR for non-fragment shaders as well. by Eric Anholt · 14 years ago
5880a9a radeon: Explain to the user what went wrong when built without libdrm. by Eric Anholt · 13 years ago
fa351bd intel: GetBuffer fix by Ben Widawsky · 13 years ago
09eeb0f i830: Add missing vtable entry for i830 from the hiz work. by Carl Simonson · 13 years ago
c9e81fe i965: Drop the reg/hw_reg distinction. by Eric Anholt · 13 years ago
b1f0bff i965/fs: Factor out the register allocator setup to a separate function. by Eric Anholt · 14 years ago
4e10d58 i965/fs: Simplify the register allocator using a map from RA reg to GRF. by Eric Anholt · 14 years ago
b76378d i965/fs: Eliminate the magic nature of virtual GRF 0. by Eric Anholt · 14 years ago
bbcf13a i965/fs: Use the new convenience interface for setting up reg conflicts. by Eric Anholt · 14 years ago
a9e97d0 intel: Fix warnings from gl_constant_parameter changes. by Eric Anholt · 13 years ago
9998df3 i965: Add dumping for gen6 WM constants too. by Eric Anholt · 13 years ago