Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 1 | /* |
Daniele Castagna | 7a755de | 2016-12-16 17:32:30 -0500 | [diff] [blame] | 2 | * Copyright 2014 The Chromium OS Authors. All rights reserved. |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | */ |
| 6 | |
Gurchetan Singh | 46faf6b | 2016-08-05 14:40:07 -0700 | [diff] [blame] | 7 | #ifdef DRV_I915 |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 8 | |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 9 | #include <assert.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 10 | #include <errno.h> |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 11 | #include <i915_drm.h> |
Kristian H. Kristensen | 9c3fb32 | 2018-04-11 15:55:13 -0700 | [diff] [blame] | 12 | #include <stdbool.h> |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 13 | #include <stdio.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 14 | #include <string.h> |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 15 | #include <sys/mman.h> |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 16 | #include <unistd.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 17 | #include <xf86drm.h> |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 18 | |
Gurchetan Singh | 46faf6b | 2016-08-05 14:40:07 -0700 | [diff] [blame] | 19 | #include "drv_priv.h" |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 20 | #include "helpers.h" |
| 21 | #include "util.h" |
| 22 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 23 | #define I915_CACHELINE_SIZE 64 |
| 24 | #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1) |
| 25 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 26 | static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888, |
| 27 | DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888, |
| 28 | DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010, |
| 29 | DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010, |
| 30 | DRM_FORMAT_XRGB8888 }; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 31 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 32 | static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F }; |
| 33 | |
| 34 | static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010, |
| 35 | DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID }; |
Gurchetan Singh | 179687e | 2016-10-28 10:07:35 -0700 | [diff] [blame] | 36 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 37 | struct i915_device { |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 38 | uint32_t gen; |
| 39 | int32_t has_llc; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 40 | }; |
| 41 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 42 | static uint32_t i915_get_gen(int device_id) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 43 | { |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 44 | const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE, |
| 45 | 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 }; |
Stéphane Marchesin | a39dfde | 2014-09-15 15:38:25 -0700 | [diff] [blame] | 46 | unsigned i; |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 47 | for (i = 0; i < ARRAY_SIZE(gen3_ids); i++) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 48 | if (gen3_ids[i] == device_id) |
| 49 | return 3; |
| 50 | |
| 51 | return 4; |
| 52 | } |
| 53 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 54 | static uint64_t unset_flags(uint64_t current_flags, uint64_t mask) |
Kristian H. Kristensen | 9c3fb32 | 2018-04-11 15:55:13 -0700 | [diff] [blame] | 55 | { |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 56 | uint64_t value = current_flags & ~mask; |
| 57 | return value; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | static int i915_add_combinations(struct driver *drv) |
| 61 | { |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 62 | struct format_metadata metadata; |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 63 | uint64_t render, scanout_and_render, texture_only; |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 64 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 65 | scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT; |
| 66 | render = BO_USE_RENDER_MASK; |
| 67 | texture_only = BO_USE_TEXTURE_MASK; |
| 68 | uint64_t linear_mask = BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_PROTECTED | |
| 69 | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 70 | |
| 71 | metadata.tiling = I915_TILING_NONE; |
| 72 | metadata.priority = 1; |
Kristian H. Kristensen | bc8c593 | 2017-10-24 18:36:32 -0700 | [diff] [blame] | 73 | metadata.modifier = DRM_FORMAT_MOD_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 74 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 75 | drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats), |
| 76 | &metadata, scanout_and_render); |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 77 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 78 | drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render); |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 79 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 80 | drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata, |
| 81 | texture_only); |
| 82 | |
| 83 | drv_modify_linear_combinations(drv); |
Hirokazu Honda | 3b8d4d0 | 2019-07-31 16:35:52 +0900 | [diff] [blame] | 84 | /* |
| 85 | * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the |
| 86 | * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future. |
| 87 | */ |
| 88 | drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER); |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 89 | /* IPU3 camera ISP supports only NV12 output. */ |
David Stevens | 6116b31 | 2019-09-03 10:49:50 +0900 | [diff] [blame] | 90 | drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 91 | BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER | |
| 92 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT); |
Hirokazu Honda | 3b8d4d0 | 2019-07-31 16:35:52 +0900 | [diff] [blame] | 93 | |
Gurchetan Singh | 71bc665 | 2018-09-17 17:42:05 -0700 | [diff] [blame] | 94 | /* Android CTS tests require this. */ |
| 95 | drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK); |
| 96 | |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 97 | /* |
| 98 | * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots |
| 99 | * from camera. |
| 100 | */ |
| 101 | drv_modify_combination(drv, DRM_FORMAT_R8, &metadata, |
Tomasz Figa | fd0b016 | 2017-07-11 18:28:02 +0900 | [diff] [blame] | 102 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 103 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 104 | render = unset_flags(render, linear_mask); |
| 105 | scanout_and_render = unset_flags(scanout_and_render, linear_mask); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 106 | |
| 107 | metadata.tiling = I915_TILING_X; |
| 108 | metadata.priority = 2; |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 109 | metadata.modifier = I915_FORMAT_MOD_X_TILED; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 110 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 111 | drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render); |
| 112 | drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats), |
| 113 | &metadata, scanout_and_render); |
Gurchetan Singh | 8ac0c9a | 2017-05-15 09:34:22 -0700 | [diff] [blame] | 114 | |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 115 | metadata.tiling = I915_TILING_Y; |
| 116 | metadata.priority = 3; |
Tomasz Figa | e821cc2 | 2017-07-08 15:53:11 +0900 | [diff] [blame] | 117 | metadata.modifier = I915_FORMAT_MOD_Y_TILED; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 118 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 119 | scanout_and_render = unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY); |
| 120 | /* Support y-tiled NV12 and P010 for libva */ |
| 121 | #ifdef I915_SCANOUT_Y_TILED |
| 122 | drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, |
| 123 | BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT); |
| 124 | #else |
Gurchetan Singh | 86ddfdc | 2018-09-17 17:13:45 -0700 | [diff] [blame] | 125 | drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, |
| 126 | BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER); |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 127 | #endif |
| 128 | scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT); |
Miguel Casas | cdb2554 | 2019-07-18 13:07:30 -0400 | [diff] [blame] | 129 | drv_add_combination(drv, DRM_FORMAT_P010, &metadata, |
| 130 | BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER); |
Kristian H. Kristensen | 3cb5bba | 2018-04-04 16:10:42 -0700 | [diff] [blame] | 131 | |
Ilja H. Friedel | f39dcbc | 2020-02-26 02:50:51 +0000 | [diff] [blame] | 132 | drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render); |
| 133 | drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats), |
| 134 | &metadata, scanout_and_render); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 135 | return 0; |
| 136 | } |
| 137 | |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 138 | static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride, |
| 139 | uint32_t *aligned_height) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 140 | { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 141 | struct i915_device *i915 = bo->drv->priv; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 142 | uint32_t horizontal_alignment; |
| 143 | uint32_t vertical_alignment; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 144 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 145 | switch (tiling) { |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 146 | default: |
| 147 | case I915_TILING_NONE: |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 148 | /* |
| 149 | * The Intel GPU doesn't need any alignment in linear mode, |
| 150 | * but libva requires the allocation stride to be aligned to |
| 151 | * 16 bytes and height to 4 rows. Further, we round up the |
| 152 | * horizontal alignment so that row start on a cache line (64 |
| 153 | * bytes). |
| 154 | */ |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 155 | horizontal_alignment = 64; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 156 | vertical_alignment = 4; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 157 | break; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 158 | |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 159 | case I915_TILING_X: |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 160 | horizontal_alignment = 512; |
| 161 | vertical_alignment = 8; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 162 | break; |
| 163 | |
| 164 | case I915_TILING_Y: |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 165 | if (i915->gen == 3) { |
| 166 | horizontal_alignment = 512; |
| 167 | vertical_alignment = 8; |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 168 | } else { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 169 | horizontal_alignment = 128; |
| 170 | vertical_alignment = 32; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 171 | } |
| 172 | break; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 173 | } |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 174 | |
David Stevens | 793675a | 2019-09-25 11:17:48 +0900 | [diff] [blame] | 175 | *aligned_height = ALIGN(*aligned_height, vertical_alignment); |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 176 | if (i915->gen > 3) { |
| 177 | *stride = ALIGN(*stride, horizontal_alignment); |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 178 | } else { |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 179 | while (*stride > horizontal_alignment) |
| 180 | horizontal_alignment <<= 1; |
| 181 | |
| 182 | *stride = horizontal_alignment; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 183 | } |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 184 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 185 | if (i915->gen <= 3 && *stride > 8192) |
| 186 | return -EINVAL; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 187 | |
Gurchetan Singh | 6423ecb | 2017-03-29 08:23:40 -0700 | [diff] [blame] | 188 | return 0; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 189 | } |
| 190 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 191 | static void i915_clflush(void *start, size_t size) |
| 192 | { |
| 193 | void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK); |
| 194 | void *end = (void *)((uintptr_t)start + size); |
| 195 | |
| 196 | __builtin_ia32_mfence(); |
| 197 | while (p < end) { |
| 198 | __builtin_ia32_clflush(p); |
| 199 | p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE); |
| 200 | } |
| 201 | } |
| 202 | |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 203 | static int i915_init(struct driver *drv) |
| 204 | { |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 205 | int ret; |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 206 | int device_id; |
| 207 | struct i915_device *i915; |
| 208 | drm_i915_getparam_t get_param; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 209 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 210 | i915 = calloc(1, sizeof(*i915)); |
| 211 | if (!i915) |
| 212 | return -ENOMEM; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 213 | |
| 214 | memset(&get_param, 0, sizeof(get_param)); |
| 215 | get_param.param = I915_PARAM_CHIPSET_ID; |
| 216 | get_param.value = &device_id; |
| 217 | ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param); |
| 218 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 219 | drv_log("Failed to get I915_PARAM_CHIPSET_ID\n"); |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 220 | free(i915); |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 221 | return -EINVAL; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 222 | } |
| 223 | |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 224 | i915->gen = i915_get_gen(device_id); |
| 225 | |
| 226 | memset(&get_param, 0, sizeof(get_param)); |
| 227 | get_param.param = I915_PARAM_HAS_LLC; |
| 228 | get_param.value = &i915->has_llc; |
| 229 | ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param); |
| 230 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 231 | drv_log("Failed to get I915_PARAM_HAS_LLC\n"); |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 232 | free(i915); |
| 233 | return -EINVAL; |
| 234 | } |
| 235 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 236 | drv->priv = i915; |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 237 | |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 238 | return i915_add_combinations(drv); |
Gurchetan Singh | 3eb8d8f | 2017-01-03 13:36:13 -0800 | [diff] [blame] | 239 | } |
| 240 | |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 241 | static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format) |
| 242 | { |
| 243 | uint32_t offset; |
| 244 | size_t plane; |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 245 | int ret, pagesize; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 246 | |
| 247 | offset = 0; |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 248 | pagesize = getpagesize(); |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 249 | for (plane = 0; plane < drv_num_planes_from_format(format); plane++) { |
| 250 | uint32_t stride = drv_stride_from_format(format, width, plane); |
| 251 | uint32_t plane_height = drv_height_from_format(format, height, plane); |
| 252 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 253 | if (bo->meta.tiling != I915_TILING_NONE) |
Gurchetan Singh | cc35e69 | 2019-02-28 15:44:54 -0800 | [diff] [blame] | 254 | assert(IS_ALIGNED(offset, pagesize)); |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 255 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 256 | ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height); |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 257 | if (ret) |
| 258 | return ret; |
| 259 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 260 | bo->meta.strides[plane] = stride; |
| 261 | bo->meta.sizes[plane] = stride * plane_height; |
| 262 | bo->meta.offsets[plane] = offset; |
| 263 | offset += bo->meta.sizes[plane]; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 264 | } |
| 265 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 266 | bo->meta.total_size = ALIGN(offset, pagesize); |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 267 | |
| 268 | return 0; |
| 269 | } |
| 270 | |
David Stevens | 26fe682 | 2020-03-09 12:23:42 +0000 | [diff] [blame] | 271 | static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, |
| 272 | uint64_t use_flags, const uint64_t *modifiers, uint32_t count) |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 273 | { |
David Stevens | 26fe682 | 2020-03-09 12:23:42 +0000 | [diff] [blame] | 274 | static const uint64_t modifier_order[] = { |
| 275 | I915_FORMAT_MOD_Y_TILED_CCS, |
| 276 | I915_FORMAT_MOD_Y_TILED, |
| 277 | I915_FORMAT_MOD_X_TILED, |
| 278 | DRM_FORMAT_MOD_LINEAR, |
| 279 | }; |
| 280 | uint64_t modifier; |
| 281 | |
| 282 | if (modifiers) { |
| 283 | modifier = |
| 284 | drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order)); |
| 285 | } else { |
| 286 | struct combination *combo = drv_get_combination(bo->drv, format, use_flags); |
| 287 | if (!combo) |
| 288 | return -EINVAL; |
| 289 | modifier = combo->metadata.modifier; |
| 290 | } |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 291 | |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 292 | switch (modifier) { |
| 293 | case DRM_FORMAT_MOD_LINEAR: |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 294 | bo->meta.tiling = I915_TILING_NONE; |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 295 | break; |
| 296 | case I915_FORMAT_MOD_X_TILED: |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 297 | bo->meta.tiling = I915_TILING_X; |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 298 | break; |
| 299 | case I915_FORMAT_MOD_Y_TILED: |
Mark Yacoub | c956564 | 2020-02-07 11:02:22 -0500 | [diff] [blame] | 300 | case I915_FORMAT_MOD_Y_TILED_CCS: |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 301 | bo->meta.tiling = I915_TILING_Y; |
Kristian H. Kristensen | 6061eab | 2017-10-03 13:53:19 -0700 | [diff] [blame] | 302 | break; |
| 303 | } |
Owen Lin | bbb69fd | 2017-06-05 14:33:08 +0800 | [diff] [blame] | 304 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 305 | bo->meta.format_modifiers[0] = modifier; |
Kristian H. Kristensen | 2b8f89e | 2018-02-07 16:10:06 -0800 | [diff] [blame] | 306 | |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 307 | if (format == DRM_FORMAT_YVU420_ANDROID) { |
| 308 | /* |
| 309 | * We only need to be able to use this as a linear texture, |
| 310 | * which doesn't put any HW restrictions on how we lay it |
| 311 | * out. The Android format does require the stride to be a |
| 312 | * multiple of 16 and expects the Cr and Cb stride to be |
| 313 | * ALIGN(Y_stride / 2, 16), which we can make happen by |
| 314 | * aligning to 32 bytes here. |
| 315 | */ |
| 316 | uint32_t stride = ALIGN(width, 32); |
| 317 | drv_bo_from_format(bo, stride, height, format); |
Mark Yacoub | c956564 | 2020-02-07 11:02:22 -0500 | [diff] [blame] | 318 | } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) { |
| 319 | /* |
| 320 | * For compressed surfaces, we need a color control surface |
| 321 | * (CCS). Color compression is only supported for Y tiled |
| 322 | * surfaces, and for each 32x16 tiles in the main surface we |
| 323 | * need a tile in the control surface. Y tiles are 128 bytes |
| 324 | * wide and 32 lines tall and we use that to first compute the |
| 325 | * width and height in tiles of the main surface. stride and |
| 326 | * height are already multiples of 128 and 32, respectively: |
| 327 | */ |
| 328 | uint32_t stride = drv_stride_from_format(format, width, 0); |
| 329 | uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128); |
| 330 | uint32_t height_in_tiles = DIV_ROUND_UP(height, 32); |
| 331 | uint32_t size = width_in_tiles * height_in_tiles * 4096; |
| 332 | uint32_t offset = 0; |
| 333 | |
| 334 | bo->meta.strides[0] = width_in_tiles * 128; |
| 335 | bo->meta.sizes[0] = size; |
| 336 | bo->meta.offsets[0] = offset; |
| 337 | offset += size; |
| 338 | |
| 339 | /* |
| 340 | * Now, compute the width and height in tiles of the control |
| 341 | * surface by dividing and rounding up. |
| 342 | */ |
| 343 | uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32); |
| 344 | uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16); |
| 345 | uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096; |
| 346 | |
| 347 | /* |
| 348 | * With stride and height aligned to y tiles, offset is |
| 349 | * already a multiple of 4096, which is the required alignment |
| 350 | * of the CCS. |
| 351 | */ |
| 352 | bo->meta.strides[1] = ccs_width_in_tiles * 128; |
| 353 | bo->meta.sizes[1] = ccs_size; |
| 354 | bo->meta.offsets[1] = offset; |
| 355 | offset += ccs_size; |
| 356 | |
| 357 | bo->meta.num_planes = 2; |
| 358 | bo->meta.total_size = offset; |
Kristian H. Kristensen | e8778f0 | 2018-04-04 14:21:41 -0700 | [diff] [blame] | 359 | } else { |
| 360 | i915_bo_from_format(bo, width, height, format); |
| 361 | } |
David Stevens | 26fe682 | 2020-03-09 12:23:42 +0000 | [diff] [blame] | 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | static int i915_bo_create_from_metadata(struct bo *bo) |
| 366 | { |
| 367 | int ret; |
| 368 | size_t plane; |
| 369 | struct drm_i915_gem_create gem_create; |
| 370 | struct drm_i915_gem_set_tiling gem_set_tiling; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 371 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 372 | memset(&gem_create, 0, sizeof(gem_create)); |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 373 | gem_create.size = bo->meta.total_size; |
Stéphane Marchesin | 5d867a4 | 2014-11-24 17:09:49 -0800 | [diff] [blame] | 374 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 375 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create); |
| 376 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 377 | drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size); |
Stéphane Marchesin | 6ac299f | 2019-03-21 12:23:29 -0700 | [diff] [blame] | 378 | return -errno; |
Ilja H. Friedel | f9d2ab7 | 2015-04-09 14:08:36 -0700 | [diff] [blame] | 379 | } |
Gurchetan Singh | 83dc4fb | 2016-07-19 15:52:33 -0700 | [diff] [blame] | 380 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 381 | for (plane = 0; plane < bo->meta.num_planes; plane++) |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 382 | bo->handles[plane].u32 = gem_create.handle; |
Daniel Nicoara | 1de26dc | 2014-09-25 18:53:19 -0400 | [diff] [blame] | 383 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 384 | memset(&gem_set_tiling, 0, sizeof(gem_set_tiling)); |
| 385 | gem_set_tiling.handle = bo->handles[0].u32; |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 386 | gem_set_tiling.tiling_mode = bo->meta.tiling; |
| 387 | gem_set_tiling.stride = bo->meta.strides[0]; |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 388 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 389 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling); |
| 390 | if (ret) { |
| 391 | struct drm_gem_close gem_close; |
| 392 | memset(&gem_close, 0, sizeof(gem_close)); |
| 393 | gem_close.handle = bo->handles[0].u32; |
| 394 | drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close); |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 395 | |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 396 | drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno); |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 397 | return -errno; |
| 398 | } |
| 399 | |
| 400 | return 0; |
| 401 | } |
| 402 | |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 403 | static void i915_close(struct driver *drv) |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 404 | { |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 405 | free(drv->priv); |
| 406 | drv->priv = NULL; |
Gurchetan Singh | 82a8eed | 2017-01-03 13:01:37 -0800 | [diff] [blame] | 407 | } |
| 408 | |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 409 | static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data) |
| 410 | { |
| 411 | int ret; |
| 412 | struct drm_i915_gem_get_tiling gem_get_tiling; |
| 413 | |
| 414 | ret = drv_prime_bo_import(bo, data); |
| 415 | if (ret) |
| 416 | return ret; |
| 417 | |
| 418 | /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */ |
| 419 | memset(&gem_get_tiling, 0, sizeof(gem_get_tiling)); |
| 420 | gem_get_tiling.handle = bo->handles[0].u32; |
| 421 | |
| 422 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling); |
| 423 | if (ret) { |
Joe Kniss | 9e5d12a | 2017-06-29 11:54:22 -0700 | [diff] [blame] | 424 | drv_gem_bo_destroy(bo); |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 425 | drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n"); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 426 | return ret; |
| 427 | } |
| 428 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 429 | bo->meta.tiling = gem_get_tiling.tiling_mode; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 430 | return 0; |
| 431 | } |
| 432 | |
Gurchetan Singh | ee43c30 | 2017-11-14 18:20:27 -0800 | [diff] [blame] | 433 | static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags) |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 434 | { |
| 435 | int ret; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 436 | void *addr; |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 437 | |
Mark Yacoub | c956564 | 2020-02-07 11:02:22 -0500 | [diff] [blame] | 438 | if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS) |
| 439 | return MAP_FAILED; |
| 440 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 441 | if (bo->meta.tiling == I915_TILING_NONE) { |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 442 | struct drm_i915_gem_mmap gem_map; |
| 443 | memset(&gem_map, 0, sizeof(gem_map)); |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 444 | |
Tomasz Figa | 39eb951 | 2018-11-01 00:45:31 +0900 | [diff] [blame] | 445 | /* TODO(b/118799155): We don't seem to have a good way to |
| 446 | * detect the use cases for which WC mapping is really needed. |
| 447 | * The current heuristic seems overly coarse and may be slowing |
| 448 | * down some other use cases unnecessarily. |
| 449 | * |
| 450 | * For now, care must be taken not to use WC mappings for |
| 451 | * Renderscript and camera use cases, as they're |
| 452 | * performance-sensitive. */ |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 453 | if ((bo->meta.use_flags & BO_USE_SCANOUT) && |
| 454 | !(bo->meta.use_flags & |
Tomasz Figa | 39eb951 | 2018-11-01 00:45:31 +0900 | [diff] [blame] | 455 | (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))) |
Gurchetan Singh | 5af2023 | 2017-09-19 15:10:58 -0700 | [diff] [blame] | 456 | gem_map.flags = I915_MMAP_WC; |
| 457 | |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 458 | gem_map.handle = bo->handles[0].u32; |
| 459 | gem_map.offset = 0; |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 460 | gem_map.size = bo->meta.total_size; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 461 | |
| 462 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map); |
| 463 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 464 | drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n"); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 465 | return MAP_FAILED; |
| 466 | } |
| 467 | |
| 468 | addr = (void *)(uintptr_t)gem_map.addr_ptr; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 469 | } else { |
| 470 | struct drm_i915_gem_mmap_gtt gem_map; |
| 471 | memset(&gem_map, 0, sizeof(gem_map)); |
| 472 | |
| 473 | gem_map.handle = bo->handles[0].u32; |
| 474 | |
| 475 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map); |
| 476 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 477 | drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n"); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 478 | return MAP_FAILED; |
| 479 | } |
| 480 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 481 | addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, |
| 482 | bo->drv->fd, gem_map.offset); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 483 | } |
| 484 | |
| 485 | if (addr == MAP_FAILED) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 486 | drv_log("i915 GEM mmap failed\n"); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 487 | return addr; |
| 488 | } |
| 489 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 490 | vma->length = bo->meta.total_size; |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 491 | return addr; |
| 492 | } |
Gurchetan Singh | 1a31e60 | 2016-10-06 10:58:00 -0700 | [diff] [blame] | 493 | |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 494 | static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping) |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 495 | { |
| 496 | int ret; |
| 497 | struct drm_i915_gem_set_domain set_domain; |
| 498 | |
| 499 | memset(&set_domain, 0, sizeof(set_domain)); |
| 500 | set_domain.handle = bo->handles[0].u32; |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 501 | if (bo->meta.tiling == I915_TILING_NONE) { |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 502 | set_domain.read_domains = I915_GEM_DOMAIN_CPU; |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 503 | if (mapping->vma->map_flags & BO_MAP_WRITE) |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 504 | set_domain.write_domain = I915_GEM_DOMAIN_CPU; |
| 505 | } else { |
| 506 | set_domain.read_domains = I915_GEM_DOMAIN_GTT; |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 507 | if (mapping->vma->map_flags & BO_MAP_WRITE) |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 508 | set_domain.write_domain = I915_GEM_DOMAIN_GTT; |
| 509 | } |
| 510 | |
| 511 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain); |
| 512 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 513 | drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret); |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 514 | return ret; |
| 515 | } |
| 516 | |
| 517 | return 0; |
| 518 | } |
| 519 | |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 520 | static int i915_bo_flush(struct bo *bo, struct mapping *mapping) |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 521 | { |
Gurchetan Singh | 68af9c2 | 2017-01-18 13:48:11 -0800 | [diff] [blame] | 522 | struct i915_device *i915 = bo->drv->priv; |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 523 | if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE) |
Gurchetan Singh | 47e629b | 2017-11-02 14:07:18 -0700 | [diff] [blame] | 524 | i915_clflush(mapping->vma->addr, mapping->vma->length); |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 525 | |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 526 | return 0; |
Gurchetan Singh | ef92053 | 2016-08-12 16:38:25 -0700 | [diff] [blame] | 527 | } |
| 528 | |
Gurchetan Singh | 0d44d48 | 2019-06-04 19:39:51 -0700 | [diff] [blame] | 529 | static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags) |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 530 | { |
| 531 | switch (format) { |
Gurchetan Singh | f3b22da | 2016-11-21 10:46:38 -0800 | [diff] [blame] | 532 | case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 533 | /* KBL camera subsystem requires NV12. */ |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 534 | if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) |
Tomasz Figa | d30c0a5 | 2017-07-05 17:50:18 +0900 | [diff] [blame] | 535 | return DRM_FORMAT_NV12; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 536 | /*HACK: See b/28671744 */ |
Gurchetan Singh | f3b22da | 2016-11-21 10:46:38 -0800 | [diff] [blame] | 537 | return DRM_FORMAT_XBGR8888; |
| 538 | case DRM_FORMAT_FLEX_YCbCr_420_888: |
Tomasz Figa | b92e4f8 | 2017-06-22 16:52:43 +0900 | [diff] [blame] | 539 | /* |
| 540 | * KBL camera subsystem requires NV12. Our other use cases |
| 541 | * don't care: |
| 542 | * - Hardware video supports NV12, |
| 543 | * - USB Camera HALv3 supports NV12, |
| 544 | * - USB Camera HALv1 doesn't use this format. |
| 545 | * Moreover, NV12 is preferred for video, due to overlay |
| 546 | * support on SKL+. |
| 547 | */ |
| 548 | return DRM_FORMAT_NV12; |
Gurchetan Singh | d6fb577 | 2016-08-29 19:13:51 -0700 | [diff] [blame] | 549 | default: |
| 550 | return format; |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 551 | } |
| 552 | } |
| 553 | |
Gurchetan Singh | 3e9d383 | 2017-10-31 10:36:25 -0700 | [diff] [blame] | 554 | const struct backend backend_i915 = { |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 555 | .name = "i915", |
Gurchetan Singh | d7c84fd | 2016-08-16 18:18:24 -0700 | [diff] [blame] | 556 | .init = i915_init, |
| 557 | .close = i915_close, |
David Stevens | 26fe682 | 2020-03-09 12:23:42 +0000 | [diff] [blame] | 558 | .bo_compute_metadata = i915_bo_compute_metadata, |
| 559 | .bo_create_from_metadata = i915_bo_create_from_metadata, |
Gurchetan Singh | cc015e8 | 2017-01-17 16:15:25 -0800 | [diff] [blame] | 560 | .bo_destroy = drv_gem_bo_destroy, |
Gurchetan Singh | fcad5ad | 2017-01-05 20:39:31 -0800 | [diff] [blame] | 561 | .bo_import = i915_bo_import, |
Gurchetan Singh | d7c84fd | 2016-08-16 18:18:24 -0700 | [diff] [blame] | 562 | .bo_map = i915_bo_map, |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 563 | .bo_unmap = drv_bo_munmap, |
Gurchetan Singh | 2d1877f | 2017-10-10 14:12:46 -0700 | [diff] [blame] | 564 | .bo_invalidate = i915_bo_invalidate, |
Gurchetan Singh | 8e02e05 | 2017-09-14 14:18:43 -0700 | [diff] [blame] | 565 | .bo_flush = i915_bo_flush, |
Gurchetan Singh | bfba8c2 | 2016-08-16 17:57:10 -0700 | [diff] [blame] | 566 | .resolve_format = i915_resolve_format, |
Stéphane Marchesin | 25a2606 | 2014-09-12 16:18:59 -0700 | [diff] [blame] | 567 | }; |
| 568 | |
| 569 | #endif |