Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 1 | /* |
Daniele Castagna | 7a755de | 2016-12-16 17:32:30 -0500 | [diff] [blame] | 2 | * Copyright 2016 The Chromium OS Authors. All rights reserved. |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | */ |
| 6 | #ifdef DRV_AMDGPU |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 7 | #include <amdgpu.h> |
| 8 | #include <amdgpu_drm.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 9 | #include <errno.h> |
| 10 | #include <stdio.h> |
| 11 | #include <stdlib.h> |
| 12 | #include <string.h> |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 13 | #include <sys/mman.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 14 | #include <xf86drm.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 15 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 16 | #include "dri.h" |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 17 | #include "drv_priv.h" |
| 18 | #include "helpers.h" |
| 19 | #include "util.h" |
| 20 | |
Gurchetan Singh | cf9ed9d | 2019-12-13 09:37:01 -0800 | [diff] [blame] | 21 | // clang-format off |
| 22 | #define DRI_PATH STRINGIZE(DRI_DRIVER_DIR/radeonsi_dri.so) |
| 23 | // clang-format on |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 24 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 25 | #define TILE_TYPE_LINEAR 0 |
| 26 | /* DRI backend decides tiling in this case. */ |
| 27 | #define TILE_TYPE_DRI 1 |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 28 | |
Ikshwaku Chauhan | 047df2b | 2020-06-29 16:44:57 +0530 | [diff] [blame] | 29 | /* Height alignement for Encoder/Decoder buffers */ |
| 30 | #define CHROME_HEIGHT_ALIGN 16 |
| 31 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 32 | struct amdgpu_priv { |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 33 | struct dri_driver dri; |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 34 | int drm_version; |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 35 | |
| 36 | /* sdma */ |
| 37 | struct drm_amdgpu_info_device dev_info; |
| 38 | uint32_t sdma_ctx; |
| 39 | uint32_t sdma_cmdbuf_bo; |
| 40 | uint64_t sdma_cmdbuf_addr; |
| 41 | uint64_t sdma_cmdbuf_size; |
| 42 | uint32_t *sdma_cmdbuf_map; |
| 43 | }; |
| 44 | |
| 45 | struct amdgpu_linear_vma_priv { |
| 46 | uint32_t handle; |
| 47 | uint32_t map_flags; |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 48 | }; |
| 49 | |
Bas Nieuwenhuizen | b16076b | 2020-06-29 12:41:18 +0200 | [diff] [blame] | 50 | const static uint32_t render_target_formats[] = { |
| 51 | DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, |
| 52 | DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, DRM_FORMAT_ABGR2101010, |
| 53 | DRM_FORMAT_ARGB2101010, DRM_FORMAT_XBGR2101010, DRM_FORMAT_XRGB2101010, |
| 54 | }; |
Gurchetan Singh | 179687e | 2016-10-28 10:07:35 -0700 | [diff] [blame] | 55 | |
Gurchetan Singh | 8d88474 | 2020-03-24 13:48:54 -0700 | [diff] [blame] | 56 | const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, |
| 57 | DRM_FORMAT_NV21, DRM_FORMAT_NV12, |
Hirokazu Honda | 3b8d4d0 | 2019-07-31 16:35:52 +0900 | [diff] [blame] | 58 | DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420 }; |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 59 | |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 60 | static int query_dev_info(int fd, struct drm_amdgpu_info_device *dev_info) |
| 61 | { |
| 62 | struct drm_amdgpu_info info_args = { 0 }; |
| 63 | |
| 64 | info_args.return_pointer = (uintptr_t)dev_info; |
| 65 | info_args.return_size = sizeof(*dev_info); |
| 66 | info_args.query = AMDGPU_INFO_DEV_INFO; |
| 67 | |
| 68 | return drmCommandWrite(fd, DRM_AMDGPU_INFO, &info_args, sizeof(info_args)); |
| 69 | } |
| 70 | |
| 71 | static int sdma_init(struct amdgpu_priv *priv, int fd) |
| 72 | { |
| 73 | union drm_amdgpu_ctx ctx_args = { { 0 } }; |
| 74 | union drm_amdgpu_gem_create gem_create = { { 0 } }; |
| 75 | struct drm_amdgpu_gem_va va_args = { 0 }; |
| 76 | union drm_amdgpu_gem_mmap gem_map = { { 0 } }; |
| 77 | struct drm_gem_close gem_close = { 0 }; |
| 78 | int ret; |
| 79 | |
| 80 | /* Ensure we can make a submission without BO lists. */ |
| 81 | if (priv->drm_version < 27) |
| 82 | return 0; |
| 83 | |
| 84 | /* Anything outside this range needs adjustments to the SDMA copy commands */ |
| 85 | if (priv->dev_info.family < AMDGPU_FAMILY_CI || priv->dev_info.family > AMDGPU_FAMILY_NV) |
| 86 | return 0; |
| 87 | |
| 88 | ctx_args.in.op = AMDGPU_CTX_OP_ALLOC_CTX; |
| 89 | |
| 90 | ret = drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args)); |
| 91 | if (ret < 0) |
| 92 | return ret; |
| 93 | |
| 94 | priv->sdma_ctx = ctx_args.out.alloc.ctx_id; |
| 95 | |
| 96 | priv->sdma_cmdbuf_size = ALIGN(4096, priv->dev_info.virtual_address_alignment); |
| 97 | gem_create.in.bo_size = priv->sdma_cmdbuf_size; |
| 98 | gem_create.in.alignment = 4096; |
| 99 | gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT; |
| 100 | |
| 101 | ret = drmCommandWriteRead(fd, DRM_AMDGPU_GEM_CREATE, &gem_create, sizeof(gem_create)); |
| 102 | if (ret < 0) |
| 103 | goto fail_ctx; |
| 104 | |
| 105 | priv->sdma_cmdbuf_bo = gem_create.out.handle; |
| 106 | |
| 107 | priv->sdma_cmdbuf_addr = |
| 108 | ALIGN(priv->dev_info.virtual_address_offset, priv->dev_info.virtual_address_alignment); |
| 109 | |
| 110 | /* Map the buffer into the GPU address space so we can use it from the GPU */ |
| 111 | va_args.handle = priv->sdma_cmdbuf_bo; |
| 112 | va_args.operation = AMDGPU_VA_OP_MAP; |
| 113 | va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_EXECUTABLE; |
| 114 | va_args.va_address = priv->sdma_cmdbuf_addr; |
| 115 | va_args.offset_in_bo = 0; |
| 116 | va_args.map_size = priv->sdma_cmdbuf_size; |
| 117 | |
| 118 | ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args)); |
| 119 | if (ret) |
| 120 | goto fail_bo; |
| 121 | |
| 122 | gem_map.in.handle = priv->sdma_cmdbuf_bo; |
| 123 | ret = drmIoctl(fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map); |
| 124 | if (ret) |
| 125 | goto fail_va; |
| 126 | |
| 127 | priv->sdma_cmdbuf_map = mmap(0, priv->sdma_cmdbuf_size, PROT_READ | PROT_WRITE, MAP_SHARED, |
| 128 | fd, gem_map.out.addr_ptr); |
| 129 | if (priv->sdma_cmdbuf_map == MAP_FAILED) { |
| 130 | priv->sdma_cmdbuf_map = NULL; |
| 131 | ret = -ENOMEM; |
| 132 | goto fail_va; |
| 133 | } |
| 134 | |
| 135 | return 0; |
| 136 | fail_va: |
| 137 | va_args.operation = AMDGPU_VA_OP_UNMAP; |
| 138 | va_args.flags = 0; |
| 139 | drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args)); |
| 140 | fail_bo: |
| 141 | gem_close.handle = priv->sdma_cmdbuf_bo; |
| 142 | drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &gem_close); |
| 143 | fail_ctx: |
| 144 | memset(&ctx_args, 0, sizeof(ctx_args)); |
| 145 | ctx_args.in.op = AMDGPU_CTX_OP_FREE_CTX; |
| 146 | ctx_args.in.ctx_id = priv->sdma_ctx; |
| 147 | drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args)); |
| 148 | return ret; |
| 149 | } |
| 150 | |
| 151 | static void sdma_finish(struct amdgpu_priv *priv, int fd) |
| 152 | { |
| 153 | union drm_amdgpu_ctx ctx_args = { { 0 } }; |
| 154 | struct drm_amdgpu_gem_va va_args = { 0 }; |
| 155 | struct drm_gem_close gem_close = { 0 }; |
| 156 | |
| 157 | if (!priv->sdma_cmdbuf_map) |
| 158 | return; |
| 159 | |
| 160 | va_args.handle = priv->sdma_cmdbuf_bo; |
| 161 | va_args.operation = AMDGPU_VA_OP_UNMAP; |
| 162 | va_args.flags = 0; |
| 163 | va_args.va_address = priv->sdma_cmdbuf_addr; |
| 164 | va_args.offset_in_bo = 0; |
| 165 | va_args.map_size = priv->sdma_cmdbuf_size; |
| 166 | drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args)); |
| 167 | |
| 168 | gem_close.handle = priv->sdma_cmdbuf_bo; |
| 169 | drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &gem_close); |
| 170 | |
| 171 | ctx_args.in.op = AMDGPU_CTX_OP_FREE_CTX; |
| 172 | ctx_args.in.ctx_id = priv->sdma_ctx; |
| 173 | drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args)); |
| 174 | } |
| 175 | |
| 176 | static int sdma_copy(struct amdgpu_priv *priv, int fd, uint32_t src_handle, uint32_t dst_handle, |
| 177 | uint64_t size) |
| 178 | { |
| 179 | const uint64_t max_size_per_cmd = 0x3fff00; |
| 180 | const uint32_t cmd_size = 7 * sizeof(uint32_t); /* 7 dwords, see loop below. */ |
| 181 | const uint64_t max_commands = priv->sdma_cmdbuf_size / cmd_size; |
| 182 | uint64_t src_addr = priv->sdma_cmdbuf_addr + priv->sdma_cmdbuf_size; |
| 183 | uint64_t dst_addr = src_addr + size; |
| 184 | struct drm_amdgpu_gem_va va_args = { 0 }; |
| 185 | unsigned cmd = 0; |
| 186 | uint64_t remaining_size = size; |
| 187 | uint64_t cur_src_addr = src_addr; |
| 188 | uint64_t cur_dst_addr = dst_addr; |
| 189 | struct drm_amdgpu_cs_chunk_ib ib = { 0 }; |
| 190 | struct drm_amdgpu_cs_chunk chunks[2] = { { 0 } }; |
| 191 | uint64_t chunk_ptrs[2]; |
| 192 | union drm_amdgpu_cs cs = { { 0 } }; |
| 193 | struct drm_amdgpu_bo_list_in bo_list = { 0 }; |
| 194 | struct drm_amdgpu_bo_list_entry bo_list_entries[3] = { { 0 } }; |
| 195 | union drm_amdgpu_wait_cs wait_cs = { { 0 } }; |
| 196 | int ret = 0; |
| 197 | |
| 198 | if (size > UINT64_MAX - max_size_per_cmd || |
| 199 | DIV_ROUND_UP(size, max_size_per_cmd) > max_commands) |
| 200 | return -ENOMEM; |
| 201 | |
| 202 | /* Map both buffers into the GPU address space so we can access them from the GPU. */ |
| 203 | va_args.handle = src_handle; |
| 204 | va_args.operation = AMDGPU_VA_OP_MAP; |
| 205 | va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_DELAY_UPDATE; |
| 206 | va_args.va_address = src_addr; |
| 207 | va_args.map_size = size; |
| 208 | |
| 209 | ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args)); |
| 210 | if (ret) |
| 211 | return ret; |
| 212 | |
| 213 | va_args.handle = dst_handle; |
| 214 | va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_DELAY_UPDATE; |
| 215 | va_args.va_address = dst_addr; |
| 216 | |
| 217 | ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args)); |
| 218 | if (ret) |
| 219 | goto unmap_src; |
| 220 | |
| 221 | while (remaining_size) { |
| 222 | uint64_t cur_size = remaining_size; |
| 223 | if (cur_size > max_size_per_cmd) |
| 224 | cur_size = max_size_per_cmd; |
| 225 | |
| 226 | priv->sdma_cmdbuf_map[cmd++] = 0x01; /* linear copy */ |
| 227 | priv->sdma_cmdbuf_map[cmd++] = |
| 228 | priv->dev_info.family >= AMDGPU_FAMILY_AI ? (cur_size - 1) : cur_size; |
| 229 | priv->sdma_cmdbuf_map[cmd++] = 0; |
| 230 | priv->sdma_cmdbuf_map[cmd++] = cur_src_addr; |
| 231 | priv->sdma_cmdbuf_map[cmd++] = cur_src_addr >> 32; |
| 232 | priv->sdma_cmdbuf_map[cmd++] = cur_dst_addr; |
| 233 | priv->sdma_cmdbuf_map[cmd++] = cur_dst_addr >> 32; |
| 234 | |
| 235 | remaining_size -= cur_size; |
| 236 | cur_src_addr += cur_size; |
| 237 | cur_dst_addr += cur_size; |
| 238 | } |
| 239 | |
| 240 | ib.va_start = priv->sdma_cmdbuf_addr; |
| 241 | ib.ib_bytes = cmd * 4; |
| 242 | ib.ip_type = AMDGPU_HW_IP_DMA; |
| 243 | |
| 244 | chunks[1].chunk_id = AMDGPU_CHUNK_ID_IB; |
| 245 | chunks[1].length_dw = sizeof(ib) / 4; |
| 246 | chunks[1].chunk_data = (uintptr_t)&ib; |
| 247 | |
| 248 | bo_list_entries[0].bo_handle = priv->sdma_cmdbuf_bo; |
| 249 | bo_list_entries[0].bo_priority = 8; /* Middle of range, like RADV. */ |
| 250 | bo_list_entries[1].bo_handle = src_handle; |
| 251 | bo_list_entries[1].bo_priority = 8; |
| 252 | bo_list_entries[2].bo_handle = dst_handle; |
| 253 | bo_list_entries[2].bo_priority = 8; |
| 254 | |
| 255 | bo_list.bo_number = 3; |
| 256 | bo_list.bo_info_size = sizeof(bo_list_entries[0]); |
| 257 | bo_list.bo_info_ptr = (uintptr_t)bo_list_entries; |
| 258 | |
| 259 | chunks[0].chunk_id = AMDGPU_CHUNK_ID_BO_HANDLES; |
| 260 | chunks[0].length_dw = sizeof(bo_list) / 4; |
| 261 | chunks[0].chunk_data = (uintptr_t)&bo_list; |
| 262 | |
| 263 | chunk_ptrs[0] = (uintptr_t)&chunks[0]; |
| 264 | chunk_ptrs[1] = (uintptr_t)&chunks[1]; |
| 265 | |
| 266 | cs.in.ctx_id = priv->sdma_ctx; |
| 267 | cs.in.num_chunks = 2; |
| 268 | cs.in.chunks = (uintptr_t)chunk_ptrs; |
| 269 | |
| 270 | ret = drmCommandWriteRead(fd, DRM_AMDGPU_CS, &cs, sizeof(cs)); |
| 271 | if (ret) { |
| 272 | drv_log("SDMA copy command buffer submission failed %d\n", ret); |
| 273 | goto unmap_dst; |
| 274 | } |
| 275 | |
| 276 | wait_cs.in.handle = cs.out.handle; |
| 277 | wait_cs.in.ip_type = AMDGPU_HW_IP_DMA; |
| 278 | wait_cs.in.ctx_id = priv->sdma_ctx; |
| 279 | wait_cs.in.timeout = INT64_MAX; |
| 280 | |
| 281 | ret = drmCommandWriteRead(fd, DRM_AMDGPU_WAIT_CS, &wait_cs, sizeof(wait_cs)); |
| 282 | if (ret) { |
| 283 | drv_log("Could not wait for CS to finish\n"); |
| 284 | } else if (wait_cs.out.status) { |
| 285 | drv_log("Infinite wait timed out, likely GPU hang.\n"); |
| 286 | ret = -ENODEV; |
| 287 | } |
| 288 | |
| 289 | unmap_dst: |
| 290 | va_args.handle = dst_handle; |
| 291 | va_args.operation = AMDGPU_VA_OP_UNMAP; |
| 292 | va_args.flags = AMDGPU_VM_DELAY_UPDATE; |
| 293 | va_args.va_address = dst_addr; |
| 294 | drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args)); |
| 295 | |
| 296 | unmap_src: |
| 297 | va_args.handle = src_handle; |
| 298 | va_args.operation = AMDGPU_VA_OP_UNMAP; |
| 299 | va_args.flags = AMDGPU_VM_DELAY_UPDATE; |
| 300 | va_args.va_address = src_addr; |
| 301 | drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args)); |
| 302 | |
| 303 | return ret; |
| 304 | } |
| 305 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 306 | static int amdgpu_init(struct driver *drv) |
| 307 | { |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 308 | struct amdgpu_priv *priv; |
| 309 | drmVersionPtr drm_version; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 310 | struct format_metadata metadata; |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 311 | uint64_t use_flags = BO_USE_RENDER_MASK; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 312 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 313 | priv = calloc(1, sizeof(struct amdgpu_priv)); |
| 314 | if (!priv) |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 315 | return -ENOMEM; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 316 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 317 | drm_version = drmGetVersion(drv_get_fd(drv)); |
| 318 | if (!drm_version) { |
| 319 | free(priv); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 320 | return -ENODEV; |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | priv->drm_version = drm_version->version_minor; |
| 324 | drmFreeVersion(drm_version); |
| 325 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 326 | drv->priv = priv; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 327 | |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 328 | if (query_dev_info(drv_get_fd(drv), &priv->dev_info)) { |
| 329 | free(priv); |
| 330 | drv->priv = NULL; |
| 331 | return -ENODEV; |
| 332 | } |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 333 | if (dri_init(drv, DRI_PATH, "radeonsi")) { |
| 334 | free(priv); |
| 335 | drv->priv = NULL; |
| 336 | return -ENODEV; |
| 337 | } |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 338 | |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 339 | if (sdma_init(priv, drv_get_fd(drv))) { |
| 340 | drv_log("SDMA init failed\n"); |
| 341 | |
| 342 | /* Continue, as we can still succesfully map things without SDMA. */ |
| 343 | } |
| 344 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 345 | metadata.tiling = TILE_TYPE_LINEAR; |
| 346 | metadata.priority = 1; |
Kristian H. Kristensen | bc8c593 | 2017-10-24 18:36:32 -0700 | [diff] [blame] | 347 | metadata.modifier = DRM_FORMAT_MOD_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 348 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 349 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 350 | &metadata, use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 351 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 352 | drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), |
| 353 | &metadata, BO_USE_TEXTURE_MASK); |
| 354 | |
Hirokazu Honda | 3bd681c | 2020-06-23 17:52:20 +0900 | [diff] [blame] | 355 | /* NV12 format for camera, display, decoding and encoding. */ |
| 356 | drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, |
| 357 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT | |
| 358 | BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER); |
Hirokazu Honda | 3b8d4d0 | 2019-07-31 16:35:52 +0900 | [diff] [blame] | 359 | |
Gurchetan Singh | 71bc665 | 2018-09-17 17:42:05 -0700 | [diff] [blame] | 360 | /* Android CTS tests require this. */ |
| 361 | drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK); |
| 362 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 363 | /* Linear formats supported by display. */ |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 364 | drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 365 | drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
Drew Davenport | 5d21524 | 2019-03-25 09:18:42 -0600 | [diff] [blame] | 366 | drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 367 | drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 368 | |
Bas Nieuwenhuizen | b16076b | 2020-06-29 12:41:18 +0200 | [diff] [blame] | 369 | drv_modify_combination(drv, DRM_FORMAT_ABGR2101010, &metadata, BO_USE_SCANOUT); |
| 370 | drv_modify_combination(drv, DRM_FORMAT_ARGB2101010, &metadata, BO_USE_SCANOUT); |
| 371 | drv_modify_combination(drv, DRM_FORMAT_XBGR2101010, &metadata, BO_USE_SCANOUT); |
| 372 | drv_modify_combination(drv, DRM_FORMAT_XRGB2101010, &metadata, BO_USE_SCANOUT); |
| 373 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 374 | drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 375 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 376 | /* |
| 377 | * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots |
David Stevens | 4951814 | 2020-06-15 13:48:48 +0900 | [diff] [blame] | 378 | * from camera and input/output from hardware decoder/encoder. |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 379 | */ |
| 380 | drv_modify_combination(drv, DRM_FORMAT_R8, &metadata, |
David Stevens | 4951814 | 2020-06-15 13:48:48 +0900 | [diff] [blame] | 381 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER | |
| 382 | BO_USE_HW_VIDEO_ENCODER); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 383 | |
| 384 | /* |
| 385 | * The following formats will be allocated by the DRI backend and may be potentially tiled. |
| 386 | * Since format modifier support hasn't been implemented fully yet, it's not |
| 387 | * possible to enumerate the different types of buffers (like i915 can). |
| 388 | */ |
| 389 | use_flags &= ~BO_USE_RENDERSCRIPT; |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 390 | use_flags &= ~BO_USE_SW_WRITE_OFTEN; |
| 391 | use_flags &= ~BO_USE_SW_READ_OFTEN; |
| 392 | use_flags &= ~BO_USE_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 393 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 394 | metadata.tiling = TILE_TYPE_DRI; |
| 395 | metadata.priority = 2; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 396 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 397 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 398 | &metadata, use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 399 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 400 | /* Potentially tiled formats supported by display. */ |
| 401 | drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 402 | drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
Bas Nieuwenhuizen | 582bdbf | 2019-04-03 18:12:12 +0200 | [diff] [blame] | 403 | drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 404 | drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); |
Bas Nieuwenhuizen | b16076b | 2020-06-29 12:41:18 +0200 | [diff] [blame] | 405 | |
| 406 | drv_modify_combination(drv, DRM_FORMAT_ABGR2101010, &metadata, BO_USE_SCANOUT); |
| 407 | drv_modify_combination(drv, DRM_FORMAT_ARGB2101010, &metadata, BO_USE_SCANOUT); |
| 408 | drv_modify_combination(drv, DRM_FORMAT_XBGR2101010, &metadata, BO_USE_SCANOUT); |
| 409 | drv_modify_combination(drv, DRM_FORMAT_XRGB2101010, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 410 | return 0; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | static void amdgpu_close(struct driver *drv) |
| 414 | { |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 415 | sdma_finish(drv->priv, drv_get_fd(drv)); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 416 | dri_close(drv); |
| 417 | free(drv->priv); |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 418 | drv->priv = NULL; |
| 419 | } |
| 420 | |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 421 | static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, |
| 422 | uint64_t use_flags) |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 423 | { |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 424 | int ret; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 425 | uint32_t plane, stride; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 426 | union drm_amdgpu_gem_create gem_create; |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 427 | struct amdgpu_priv *priv = bo->drv->priv; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 428 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 429 | stride = drv_stride_from_format(format, width, 0); |
Keiichi Watanabe | 79155d7 | 2018-08-13 16:44:54 +0900 | [diff] [blame] | 430 | stride = ALIGN(stride, 256); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 431 | |
Ikshwaku Chauhan | 047df2b | 2020-06-29 16:44:57 +0530 | [diff] [blame] | 432 | /* |
| 433 | * Currently, allocator used by chrome aligns the height for Encoder/ |
| 434 | * Decoder buffers while allocator used by android(gralloc/minigbm) |
| 435 | * doesn't provide any aligment. |
| 436 | * |
| 437 | * See b/153130069 |
| 438 | */ |
| 439 | if (use_flags & (BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER)) |
| 440 | height = ALIGN(height, CHROME_HEIGHT_ALIGN); |
| 441 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 442 | drv_bo_from_format(bo, stride, height, format); |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 443 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 444 | memset(&gem_create, 0, sizeof(gem_create)); |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 445 | gem_create.in.bo_size = |
| 446 | ALIGN(bo->meta.total_size, priv->dev_info.virtual_address_alignment); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 447 | gem_create.in.alignment = 256; |
Dominik Behr | fa17cdd | 2017-11-30 12:23:06 -0800 | [diff] [blame] | 448 | gem_create.in.domain_flags = 0; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 449 | |
Gurchetan Singh | 71bc665 | 2018-09-17 17:42:05 -0700 | [diff] [blame] | 450 | if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK)) |
Dominik Behr | fa17cdd | 2017-11-30 12:23:06 -0800 | [diff] [blame] | 451 | gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; |
| 452 | |
Deepak Sharma | 62a9c4e | 2018-05-01 12:11:27 -0700 | [diff] [blame] | 453 | gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT; |
Bas Nieuwenhuizen | 4daf12c | 2020-06-04 23:11:27 +0200 | [diff] [blame] | 454 | |
| 455 | /* Scanout in GTT requires USWC, otherwise try to use cachable memory |
| 456 | * for buffers that are read often, because uncacheable reads can be |
| 457 | * very slow. USWC should be faster on the GPU though. */ |
| 458 | if ((use_flags & BO_USE_SCANOUT) || !(use_flags & BO_USE_SW_READ_OFTEN)) |
Jao-ke Chin-Lee | 5481e3c | 2020-04-10 00:12:12 +0000 | [diff] [blame] | 459 | gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC; |
Dominik Behr | fa17cdd | 2017-11-30 12:23:06 -0800 | [diff] [blame] | 460 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 461 | /* Allocate the buffer with the preferred heap. */ |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 462 | ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create, |
| 463 | sizeof(gem_create)); |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 464 | if (ret < 0) |
| 465 | return ret; |
| 466 | |
Gurchetan Singh | 298b757 | 2019-09-19 09:55:18 -0700 | [diff] [blame] | 467 | for (plane = 0; plane < bo->meta.num_planes; plane++) |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 468 | bo->handles[plane].u32 = gem_create.out.handle; |
| 469 | |
Bas Nieuwenhuizen | 7119d33 | 2020-02-07 20:20:30 +0100 | [diff] [blame] | 470 | bo->meta.format_modifiers[0] = DRM_FORMAT_MOD_LINEAR; |
| 471 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 472 | return 0; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 473 | } |
| 474 | |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 475 | static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, |
| 476 | uint64_t use_flags) |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 477 | { |
| 478 | struct combination *combo; |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 479 | |
| 480 | combo = drv_get_combination(bo->drv, format, use_flags); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 481 | if (!combo) |
| 482 | return -EINVAL; |
| 483 | |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 484 | if (combo->metadata.tiling == TILE_TYPE_DRI) { |
| 485 | bool needs_alignment = false; |
| 486 | #ifdef __ANDROID__ |
| 487 | /* |
| 488 | * Currently, the gralloc API doesn't differentiate between allocation time and map |
| 489 | * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at |
| 490 | * allocation time. |
| 491 | * |
| 492 | * See b/115946221,b/117942643 |
| 493 | */ |
| 494 | if (use_flags & (BO_USE_SW_MASK)) |
| 495 | needs_alignment = true; |
| 496 | #endif |
| 497 | // See b/122049612 |
| 498 | if (use_flags & (BO_USE_SCANOUT)) |
| 499 | needs_alignment = true; |
| 500 | |
| 501 | if (needs_alignment) { |
| 502 | uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0); |
| 503 | width = ALIGN(width, 256 / bytes_per_pixel); |
| 504 | } |
| 505 | |
| 506 | return dri_bo_create(bo, width, height, format, use_flags); |
| 507 | } |
| 508 | |
| 509 | return amdgpu_create_bo_linear(bo, width, height, format, use_flags); |
| 510 | } |
| 511 | |
| 512 | static int amdgpu_create_bo_with_modifiers(struct bo *bo, uint32_t width, uint32_t height, |
| 513 | uint32_t format, const uint64_t *modifiers, |
| 514 | uint32_t count) |
| 515 | { |
| 516 | bool only_use_linear = true; |
| 517 | |
| 518 | for (uint32_t i = 0; i < count; ++i) |
| 519 | if (modifiers[i] != DRM_FORMAT_MOD_LINEAR) |
| 520 | only_use_linear = false; |
| 521 | |
| 522 | if (only_use_linear) |
| 523 | return amdgpu_create_bo_linear(bo, width, height, format, BO_USE_SCANOUT); |
| 524 | |
| 525 | return dri_bo_create_with_modifiers(bo, width, height, format, modifiers, count); |
| 526 | } |
| 527 | |
| 528 | static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data) |
| 529 | { |
| 530 | bool dri_tiling = data->format_modifiers[0] != DRM_FORMAT_MOD_LINEAR; |
| 531 | if (data->format_modifiers[0] == DRM_FORMAT_MOD_INVALID) { |
| 532 | struct combination *combo; |
| 533 | combo = drv_get_combination(bo->drv, data->format, data->use_flags); |
| 534 | if (!combo) |
| 535 | return -EINVAL; |
| 536 | |
| 537 | dri_tiling = combo->metadata.tiling == TILE_TYPE_DRI; |
| 538 | } |
| 539 | |
| 540 | if (dri_tiling) |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 541 | return dri_bo_import(bo, data); |
| 542 | else |
| 543 | return drv_prime_bo_import(bo, data); |
| 544 | } |
| 545 | |
| 546 | static int amdgpu_destroy_bo(struct bo *bo) |
| 547 | { |
| 548 | if (bo->priv) |
| 549 | return dri_bo_destroy(bo); |
| 550 | else |
| 551 | return drv_gem_bo_destroy(bo); |
| 552 | } |
| 553 | |
| 554 | static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags) |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 555 | { |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 556 | void *addr = MAP_FAILED; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 557 | int ret; |
| 558 | union drm_amdgpu_gem_mmap gem_map; |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 559 | struct drm_amdgpu_gem_create_in bo_info = { 0 }; |
| 560 | struct drm_amdgpu_gem_op gem_op = { 0 }; |
| 561 | uint32_t handle = bo->handles[plane].u32; |
| 562 | struct amdgpu_linear_vma_priv *priv = NULL; |
| 563 | struct amdgpu_priv *drv_priv; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 564 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 565 | if (bo->priv) |
| 566 | return dri_bo_map(bo, vma, plane, map_flags); |
| 567 | |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 568 | drv_priv = bo->drv->priv; |
| 569 | gem_op.handle = handle; |
| 570 | gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO; |
| 571 | gem_op.value = (uintptr_t)&bo_info; |
| 572 | |
| 573 | ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_OP, &gem_op, sizeof(gem_op)); |
| 574 | if (ret) |
| 575 | return MAP_FAILED; |
| 576 | |
| 577 | vma->length = bo_info.bo_size; |
| 578 | |
| 579 | if (((bo_info.domains & AMDGPU_GEM_DOMAIN_VRAM) || |
| 580 | (bo_info.domain_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)) && |
| 581 | drv_priv->sdma_cmdbuf_map) { |
| 582 | union drm_amdgpu_gem_create gem_create = { { 0 } }; |
| 583 | |
| 584 | priv = calloc(1, sizeof(struct amdgpu_linear_vma_priv)); |
| 585 | if (!priv) |
| 586 | return MAP_FAILED; |
| 587 | |
| 588 | gem_create.in.bo_size = bo_info.bo_size; |
| 589 | gem_create.in.alignment = 4096; |
| 590 | gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT; |
| 591 | |
| 592 | ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_CREATE, &gem_create, |
| 593 | sizeof(gem_create)); |
| 594 | if (ret < 0) { |
| 595 | drv_log("GEM create failed\n"); |
| 596 | free(priv); |
| 597 | return MAP_FAILED; |
| 598 | } |
| 599 | |
| 600 | priv->map_flags = map_flags; |
| 601 | handle = priv->handle = gem_create.out.handle; |
| 602 | |
| 603 | ret = sdma_copy(bo->drv->priv, bo->drv->fd, bo->handles[0].u32, priv->handle, |
| 604 | bo_info.bo_size); |
| 605 | if (ret) { |
| 606 | drv_log("SDMA copy for read failed\n"); |
| 607 | goto fail; |
| 608 | } |
| 609 | } |
| 610 | |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 611 | memset(&gem_map, 0, sizeof(gem_map)); |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 612 | gem_map.in.handle = handle; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 613 | |
| 614 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map); |
| 615 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 616 | drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n"); |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 617 | goto fail; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 618 | } |
Gurchetan Singh | cfb8876 | 2017-09-28 17:14:50 -0700 | [diff] [blame] | 619 | |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 620 | addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd, |
Gurchetan Singh | cfb8876 | 2017-09-28 17:14:50 -0700 | [diff] [blame] | 621 | gem_map.out.addr_ptr); |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 622 | if (addr == MAP_FAILED) |
| 623 | goto fail; |
| 624 | |
| 625 | vma->priv = priv; |
| 626 | return addr; |
| 627 | |
| 628 | fail: |
| 629 | if (priv) { |
| 630 | struct drm_gem_close gem_close = { 0 }; |
| 631 | gem_close.handle = priv->handle; |
| 632 | drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close); |
| 633 | free(priv); |
| 634 | } |
| 635 | return MAP_FAILED; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 636 | } |
| 637 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 638 | static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma) |
| 639 | { |
| 640 | if (bo->priv) |
| 641 | return dri_bo_unmap(bo, vma); |
Bas Nieuwenhuizen | 4a3f98c | 2020-06-20 03:50:34 +0200 | [diff] [blame] | 642 | else { |
| 643 | int r = munmap(vma->addr, vma->length); |
| 644 | if (r) |
| 645 | return r; |
| 646 | |
| 647 | if (vma->priv) { |
| 648 | struct amdgpu_linear_vma_priv *priv = vma->priv; |
| 649 | struct drm_gem_close gem_close = { 0 }; |
| 650 | |
| 651 | if (BO_MAP_WRITE & priv->map_flags) { |
| 652 | r = sdma_copy(bo->drv->priv, bo->drv->fd, priv->handle, |
| 653 | bo->handles[0].u32, vma->length); |
| 654 | if (r) |
| 655 | return r; |
| 656 | } |
| 657 | |
| 658 | gem_close.handle = priv->handle; |
| 659 | r = drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close); |
| 660 | } |
| 661 | |
| 662 | return 0; |
| 663 | } |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 664 | } |
| 665 | |
Deepak Sharma | ff66c80 | 2018-11-16 12:10:54 -0800 | [diff] [blame] | 666 | static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping) |
| 667 | { |
| 668 | int ret; |
| 669 | union drm_amdgpu_gem_wait_idle wait_idle; |
| 670 | |
| 671 | if (bo->priv) |
| 672 | return 0; |
| 673 | |
| 674 | memset(&wait_idle, 0, sizeof(wait_idle)); |
| 675 | wait_idle.in.handle = bo->handles[0].u32; |
| 676 | wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE; |
| 677 | |
| 678 | ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle, |
| 679 | sizeof(wait_idle)); |
| 680 | |
| 681 | if (ret < 0) { |
| 682 | drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret); |
| 683 | return ret; |
| 684 | } |
| 685 | |
| 686 | if (ret == 0 && wait_idle.out.status) |
| 687 | drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n"); |
| 688 | |
| 689 | return 0; |
| 690 | } |
| 691 | |
Gurchetan Singh | 0d44d48 | 2019-06-04 19:39:51 -0700 | [diff] [blame] | 692 | static uint32_t amdgpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags) |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 693 | { |
| 694 | switch (format) { |
Ricky Liang | 0b78e07 | 2017-11-10 09:17:17 +0800 | [diff] [blame] | 695 | case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: |
| 696 | /* Camera subsystem requires NV12. */ |
| 697 | if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) |
| 698 | return DRM_FORMAT_NV12; |
| 699 | /*HACK: See b/28671744 */ |
| 700 | return DRM_FORMAT_XBGR8888; |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 701 | case DRM_FORMAT_FLEX_YCbCr_420_888: |
| 702 | return DRM_FORMAT_NV12; |
| 703 | default: |
| 704 | return format; |
| 705 | } |
| 706 | } |
| 707 | |
Gurchetan Singh | 3e9d383 | 2017-10-31 10:36:25 -0700 | [diff] [blame] | 708 | const struct backend backend_amdgpu = { |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 709 | .name = "amdgpu", |
| 710 | .init = amdgpu_init, |
| 711 | .close = amdgpu_close, |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 712 | .bo_create = amdgpu_create_bo, |
ChromeOS Developer | 9b367b3 | 2020-03-02 13:08:53 +0100 | [diff] [blame] | 713 | .bo_create_with_modifiers = amdgpu_create_bo_with_modifiers, |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 714 | .bo_destroy = amdgpu_destroy_bo, |
| 715 | .bo_import = amdgpu_import_bo, |
| 716 | .bo_map = amdgpu_map_bo, |
| 717 | .bo_unmap = amdgpu_unmap_bo, |
Deepak Sharma | ff66c80 | 2018-11-16 12:10:54 -0800 | [diff] [blame] | 718 | .bo_invalidate = amdgpu_bo_invalidate, |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 719 | .resolve_format = amdgpu_resolve_format, |
ChromeOS Developer | 44588bb | 2020-03-02 16:32:09 +0100 | [diff] [blame] | 720 | .num_planes_from_modifier = dri_num_planes_from_modifier, |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 721 | }; |
| 722 | |
| 723 | #endif |