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Stéphane Marchesin25a26062014-09-12 16:18:59 -07001/*
Daniele Castagna7a755de2016-12-16 17:32:30 -05002 * Copyright 2014 The Chromium OS Authors. All rights reserved.
Stéphane Marchesin25a26062014-09-12 16:18:59 -07003 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_EXYNOS
Stéphane Marchesin25a26062014-09-12 16:18:59 -07008
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -08009// clang-format off
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050010#include <assert.h>
11#include <errno.h>
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070012#include <stdio.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070013#include <string.h>
14#include <xf86drm.h>
15#include <exynos_drm.h>
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080016// clang-format on
Stéphane Marchesin25a26062014-09-12 16:18:59 -070017
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070018#include "drv_priv.h"
Stéphane Marchesin25a26062014-09-12 16:18:59 -070019#include "helpers.h"
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050020#include "util.h"
Stéphane Marchesin25a26062014-09-12 16:18:59 -070021
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070022static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888 };
23
24static const uint32_t texture_source_formats[] = { DRM_FORMAT_NV12 };
Gurchetan Singh179687e2016-10-28 10:07:35 -070025
26static int exynos_init(struct driver *drv)
27{
Gurchetan Singhd3001452017-11-03 17:18:36 -070028 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
29 &LINEAR_METADATA, BO_USE_RENDER_MASK);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070030
Gurchetan Singhd3001452017-11-03 17:18:36 -070031 drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
32 &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070033
34 return drv_modify_linear_combinations(drv);
Gurchetan Singh179687e2016-10-28 10:07:35 -070035}
36
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080037static int exynos_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
Gurchetan Singha1892b22017-09-28 16:40:52 -070038 uint64_t use_flags)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070039{
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050040 size_t plane;
Stéphane Marchesin25a26062014-09-12 16:18:59 -070041
Gurchetan Singhf3b22da2016-11-21 10:46:38 -080042 if (format == DRM_FORMAT_NV12) {
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050043 uint32_t chroma_height;
44 /* V4L2 s5p-mfc requires width to be 16 byte aligned and height 32. */
45 width = ALIGN(width, 16);
46 height = ALIGN(height, 32);
47 chroma_height = ALIGN(height / 2, 32);
Gurchetan Singh298b7572019-09-19 09:55:18 -070048 bo->meta.strides[0] = bo->meta.strides[1] = width;
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050049 /* MFC v8+ requires 64 byte padding in the end of luma and chroma buffers. */
Gurchetan Singh298b7572019-09-19 09:55:18 -070050 bo->meta.sizes[0] = bo->meta.strides[0] * height + 64;
51 bo->meta.sizes[1] = bo->meta.strides[1] * chroma_height + 64;
52 bo->meta.offsets[0] = bo->meta.offsets[1] = 0;
53 bo->meta.total_size = bo->meta.sizes[0] + bo->meta.sizes[1];
Gurchetan Singhf3b22da2016-11-21 10:46:38 -080054 } else if (format == DRM_FORMAT_XRGB8888 || format == DRM_FORMAT_ARGB8888) {
Gurchetan Singh298b7572019-09-19 09:55:18 -070055 bo->meta.strides[0] = drv_stride_from_format(format, width, 0);
56 bo->meta.total_size = bo->meta.sizes[0] = height * bo->meta.strides[0];
57 bo->meta.offsets[0] = 0;
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050058 } else {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -070059 drv_log("unsupported format %X\n", format);
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050060 assert(0);
61 return -EINVAL;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070062 }
Stéphane Marchesin25a26062014-09-12 16:18:59 -070063
Zach Reizner74312362016-05-03 15:45:16 -070064 int ret;
Gurchetan Singh298b7572019-09-19 09:55:18 -070065 for (plane = 0; plane < bo->meta.num_planes; plane++) {
66 size_t size = bo->meta.sizes[plane];
Gurchetan Singh99644382020-10-07 15:28:11 -070067 struct drm_exynos_gem_create gem_create = { 0 };
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050068
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050069 gem_create.size = size;
70 gem_create.flags = EXYNOS_BO_NONCONTIG;
71
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070072 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_EXYNOS_GEM_CREATE, &gem_create);
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050073 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -070074 drv_log("DRM_IOCTL_EXYNOS_GEM_CREATE failed (size=%zu)\n", size);
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -070075 ret = -errno;
Zach Reizner74312362016-05-03 15:45:16 -070076 goto cleanup_planes;
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050077 }
78
79 bo->handles[plane].u32 = gem_create.handle;
80 }
Stéphane Marchesin25a26062014-09-12 16:18:59 -070081
82 return 0;
Zach Reizner74312362016-05-03 15:45:16 -070083
84cleanup_planes:
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080085 for (; plane != 0; plane--) {
Gurchetan Singh99644382020-10-07 15:28:11 -070086 struct drm_gem_close gem_close = { 0 };
87
Zach Reizner74312362016-05-03 15:45:16 -070088 gem_close.handle = bo->handles[plane - 1].u32;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080089 int gem_close_ret = drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
Zach Reizner74312362016-05-03 15:45:16 -070090 if (gem_close_ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -070091 drv_log("DRM_IOCTL_GEM_CLOSE failed: %d\n", gem_close_ret);
Zach Reizner74312362016-05-03 15:45:16 -070092 }
93 }
94
95 return ret;
Stéphane Marchesin25a26062014-09-12 16:18:59 -070096}
97
Gurchetan Singhef920532016-08-12 16:38:25 -070098/*
99 * Use dumb mapping with exynos even though a GEM buffer is created.
100 * libdrm does the same thing in exynos_drm.c
101 */
Gurchetan Singh3e9d3832017-10-31 10:36:25 -0700102const struct backend backend_exynos = {
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700103 .name = "exynos",
Gurchetan Singh179687e2016-10-28 10:07:35 -0700104 .init = exynos_init,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700105 .bo_create = exynos_bo_create,
Gurchetan Singh46faf6b2016-08-05 14:40:07 -0700106 .bo_destroy = drv_gem_bo_destroy,
Gurchetan Singh71611d62017-01-03 16:49:56 -0800107 .bo_import = drv_prime_bo_import,
Gurchetan Singhef920532016-08-12 16:38:25 -0700108 .bo_map = drv_dumb_bo_map,
Gurchetan Singhba6bd502017-09-18 15:29:47 -0700109 .bo_unmap = drv_bo_munmap,
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700110};
111
112#endif