commit 9b140f650f8dbefb2c5047ec8f3470424b8a084a
author Benjamin Peterson <benjamin@python.org> Sat May 15 18:00:56 2010 +0000
committer Benjamin Peterson <benjamin@python.org> Sat May 15 18:00:56 2010 +0000
tree 5cf03f02406534548bc37f904978fcc89b0a2e19
parent 30b038497bd3e2067e21e9ea2a7e02423999f9ae

Merged revisions 81201 via svnmerge from
svn+ssh://pythondev@svn.python.org/python/branches/py3k

................
  r81201 | benjamin.peterson | 2010-05-15 12:52:12 -0500 (Sat, 15 May 2010) | 9 lines

  Merged revisions 81200 via svnmerge from
  svn+ssh://pythondev@svn.python.org/python/trunk

  ........
    r81200 | benjamin.peterson | 2010-05-15 12:48:55 -0500 (Sat, 15 May 2010) | 1 line

    use TestCase skip method
  ........
................

Lib/test/test_signal.py

diff --git a/Lib/test/test_signal.py b/Lib/test/test_signal.py
index ade339a..a246695 100644
--- a/Lib/test/test_signal.py
+++ b/Lib/test/test_signal.py
@@ -431,8 +431,8 @@
             if signal.getitimer(self.itimer) == (0.0, 0.0):
                 break # sig_vtalrm handler stopped this itimer
         else: # Issue 8424
-            raise unittest.SkipTest("timeout: likely cause: machine too slow "
-                                    "or load too high")
+            self.skipTest("timeout: likely cause: machine too slow or load too "
+                          "high")
 
         # virtual itimer should be (0.0, 0.0) now
         self.assertEquals(signal.getitimer(self.itimer), (0.0, 0.0))
@@ -454,8 +454,8 @@
             if signal.getitimer(self.itimer) == (0.0, 0.0):
                 break # sig_prof handler stopped this itimer
         else: # Issue 8424
-            raise unittest.SkipTest("timeout: likely cause: machine too slow "
-                                    "or load too high")
+            self.skipTest("timeout: likely cause: machine too slow or load too "
+                          "high")
 
         # profiling itimer should be (0.0, 0.0) now
         self.assertEquals(signal.getitimer(self.itimer), (0.0, 0.0))