commit a641aec03c07e3ec8a56401a8ee6b4052d6343b8
author cliechti <cliechti@f19166aa-fa4f-0410-85c2-fa1106f25c8a> Wed Jul 22 00:24:41 2009 +0000
committer cliechti <cliechti@f19166aa-fa4f-0410-85c2-fa1106f25c8a> Wed Jul 22 00:24:41 2009 +0000
tree dd6a6544328f1ee01ea09ffa00e7d50ad3f4a8cf
parent 490a5c7b018f7ac7a7d2e0482ddb51e22ee712f7

implement patch from DanielC

pyparallel/CHANGES.txt

diff --git a/pyparallel/CHANGES.txt b/pyparallel/CHANGES.txt
index 94b0269..beef1e2 100644
--- a/pyparallel/CHANGES.txt
+++ b/pyparallel/CHANGES.txt
@@ -2,4 +2,7 @@
     added to CVS
 
 Version 0.2     27 Jan 2005
-    Windows version now using ctypes
\ No newline at end of file
+    Windows version now using ctypes
+
+Version ...     ...
+    added setDataDir to Windows backend

pyparallel/parallel/parallelwin32.py

diff --git a/pyparallel/parallel/parallelwin32.py b/pyparallel/parallel/parallelwin32.py
index 5754578..c8f0d23 100644
--- a/pyparallel/parallel/parallelwin32.py
+++ b/pyparallel/parallel/parallelwin32.py
@@ -77,6 +77,14 @@
     def setData(self, value):
         _pyparallel.outp(self.dataRegAdr, value)
 
+    def setDataDir( self, level):
+        """set for port as input, clear for output"""
+        if level:
+            self.ctrlReg |= 0x20
+        else:
+            self.ctrlReg &= ~0x20
+        _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
+
     # control register output functions
     def setDataStrobe(self, level):
         """data strobe bit"""
@@ -101,7 +109,7 @@
         else:
             self.ctrlReg = self.ctrlReg & ~0x04
         _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
-    
+
     def setSelect(self, level):
         """select bit"""
         if level: