cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 1 | #! /usr/bin/env python |
| 2 | # Python Serial Port Extension for Win32, Linux, BSD, Jython |
| 3 | # see __init__.py |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 4 | # |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 5 | # (C) 2001-2008 Chris Liechti <cliechti@gmx.net> |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 6 | # this is distributed under a free software license, see license.txt |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 7 | |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 8 | """\ |
| 9 | Some tests for the serial module. |
| 10 | Part of pyserial (http://pyserial.sf.net) (C)2001-2008 cliechti@gmx.net |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 11 | |
| 12 | Intended to be run on different platforms, to ensure portability of |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 13 | the code. |
| 14 | |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 15 | For all these tests a simple hardware is required. |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 16 | Loopback HW adapter: |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 17 | Shortcut these pin pairs: |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 18 | TX <-> RX |
| 19 | RTS <-> CTS |
| 20 | DTR <-> DSR |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 21 | |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 22 | On a 9 pole DSUB these are the pins (2-3) (4-6) (7-8) |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 23 | """ |
| 24 | |
| 25 | import unittest, threading, time |
| 26 | import serial |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 27 | |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 28 | #on which port should the tests be performed: |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 29 | PORT=0 |
| 30 | |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 31 | |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 32 | class Test4_Nonblocking(unittest.TestCase): |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 33 | """Test with timeouts""" |
| 34 | timeout=0 |
| 35 | def setUp(self): |
| 36 | self.s = serial.Serial(PORT,timeout=self.timeout) |
| 37 | def tearDown(self): |
| 38 | self.s.close() |
| 39 | |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 40 | def test0_Messy(self): |
| 41 | """NonBlocking (timeout=0)""" |
| 42 | #this is only here to write out the message in verbose mode |
| 43 | #because Test3 and Test4 print the same messages |
| 44 | |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 45 | def test1_ReadEmpty(self): |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 46 | """timeout: After port open, the input buffer must be empty""" |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 47 | self.failUnless(self.s.read(1)=='', "expected empty buffer") |
| 48 | def test2_Loopback(self): |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 49 | """timeout: each sent character should return (binary test). |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 50 | this is also a test for the binary capability of a port.""" |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 51 | for c in map(chr,range(256)): |
| 52 | self.s.write(c) |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 53 | time.sleep(0.02) #there might be a small delay until the character is ready (especialy on win32) |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 54 | self.failUnless(self.s.inWaiting()==1, "expected exactly one character for inWainting()") |
cliechti | 107db8d | 2004-01-15 01:20:23 +0000 | [diff] [blame] | 55 | self.failUnless(self.s.read(1)==c, "expected a '%s' which was written before" % c) |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 56 | self.failUnless(self.s.read(1)=='', "expected empty buffer after all sent chars are read") |
| 57 | def test2_LoopbackTimeout(self): |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 58 | """timeout: test the timeout/immediate return. |
| 59 | partial results should be returned.""" |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 60 | self.s.write("HELLO") |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 61 | time.sleep(0.1) #there might be a small delay until the character is ready (especialy on win32) |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 62 | #read more characters as are available to run in the timeout |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 63 | self.failUnless(self.s.read(10)=='HELLO', "expected the 'HELLO' which was written before") |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 64 | self.failUnless(self.s.read(1)=='', "expected empty buffer after all sent chars are read") |
| 65 | |
| 66 | |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 67 | class Test3_Timeout(Test4_Nonblocking): |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 68 | """Same tests as the NonBlocking ones but this time with timeout""" |
| 69 | timeout=1 |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 70 | def test0_Messy(self): |
| 71 | """Blocking (timeout=1)""" |
| 72 | #this is only here to write out the message in verbose mode |
| 73 | #because Test3 and Test4 print the same messages |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 74 | |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 75 | class SendEvent(threading.Thread): |
| 76 | def __init__(self, serial, delay=1): |
| 77 | threading.Thread.__init__(self) |
| 78 | self.serial = serial |
| 79 | self.delay = delay |
| 80 | self.x = threading.Event() |
| 81 | self.stopped = 0 |
| 82 | self.start() |
| 83 | def run(self): |
| 84 | time.sleep(self.delay) |
| 85 | if not self.stopped: |
| 86 | self.serial.write("E") |
| 87 | self.x.set() |
| 88 | def isSet(self): |
| 89 | return self.x.isSet() |
| 90 | def stop(self): |
| 91 | self.stopped = 1 |
| 92 | self.x.wait() |
| 93 | |
| 94 | class Test1_Forever(unittest.TestCase): |
| 95 | """Tests a port with no timeout. These tests require that a |
| 96 | character is sent after some time to stop the test, this is done |
| 97 | through the SendEvent class and the Loopback HW.""" |
| 98 | def setUp(self): |
cliechti | 6261161 | 2004-04-20 01:55:43 +0000 | [diff] [blame] | 99 | self.s = serial.Serial(PORT, timeout=None) |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 100 | self.event = SendEvent(self.s) |
| 101 | def tearDown(self): |
| 102 | self.event.stop() |
| 103 | self.s.close() |
| 104 | |
| 105 | def test2_ReadEmpty(self): |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 106 | """no timeout: after port open, the input buffer must be empty (read). |
| 107 | a character is sent after some time to terminate the test (SendEvent).""" |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 108 | c = self.s.read(1) |
cliechti | 6261161 | 2004-04-20 01:55:43 +0000 | [diff] [blame] | 109 | if not (self.event.isSet() and c == 'E'): |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 110 | self.fail("expected marker") |
| 111 | |
| 112 | class Test2_Forever(unittest.TestCase): |
| 113 | """Tests a port with no timeout""" |
| 114 | def setUp(self): |
| 115 | self.s = serial.Serial(PORT,timeout=None) |
| 116 | def tearDown(self): |
| 117 | self.s.close() |
| 118 | |
| 119 | def test1_inWaitingEmpty(self): |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 120 | """no timeout: after port open, the input buffer must be empty (inWaiting)""" |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 121 | self.failUnless(self.s.inWaiting()==0, "expected empty buffer") |
| 122 | |
| 123 | def test2_Loopback(self): |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 124 | """no timeout: each sent character should return (binary test). |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 125 | this is also a test for the binary capability of a port.""" |
| 126 | for c in map(chr,range(256)): |
| 127 | self.s.write(c) |
| 128 | time.sleep(0.02) #there might be a small delay until the character is ready (especialy on win32) |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 129 | self.failUnless(self.s.inWaiting()==1, "expected exactly one character for inWainting()") |
cliechti | 1e95baa | 2002-06-04 22:46:50 +0000 | [diff] [blame] | 130 | self.failUnless(self.s.read(1)==c, "expected an '%s' which was written before" % c) |
| 131 | self.failUnless(self.s.inWaiting()==0, "expected empty buffer after all sent chars are read") |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 132 | |
| 133 | |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 134 | class Test0_DataWires(unittest.TestCase): |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 135 | """Test modem control lines""" |
| 136 | def setUp(self): |
| 137 | self.s = serial.Serial(PORT) |
| 138 | def tearDown(self): |
| 139 | self.s.close() |
| 140 | |
| 141 | def test1_RTS(self): |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 142 | """Test RTS/CTS""" |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 143 | self.s.setRTS(0) |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 144 | self.failUnless(not self.s.getCTS(), "CTS -> 0") |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 145 | self.s.setRTS(1) |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 146 | self.failUnless(self.s.getCTS(), "CTS -> 1") |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 147 | |
| 148 | def test2_DTR(self): |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 149 | """Test DTR/DSR""" |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 150 | self.s.setDTR(0) |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 151 | self.failUnless(not self.s.getDSR(), "DSR -> 0") |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 152 | self.s.setDTR(1) |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 153 | self.failUnless(self.s.getDSR(), "DSR -> 1") |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 154 | |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 155 | def test3_RI(self): |
| 156 | """Test RI""" |
cliechti | cb65c68 | 2008-06-22 22:47:02 +0000 | [diff] [blame] | 157 | self.failUnless(not self.s.getRI(), "RI -> 0") |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 158 | |
cliechti | 6261161 | 2004-04-20 01:55:43 +0000 | [diff] [blame] | 159 | class Test_MoreTimeouts(unittest.TestCase): |
| 160 | """Test with timeouts""" |
| 161 | def setUp(self): |
| 162 | self.s = serial.Serial() #create an closed serial port |
| 163 | |
| 164 | def tearDown(self): |
| 165 | self.s.close() |
| 166 | |
| 167 | def test_WriteTimeout(self): |
| 168 | """Test write() timeout.""" |
| 169 | #use xonxoff setting and the loopback adapter to switch traffic on hold |
| 170 | self.s.port = PORT |
| 171 | self.s.writeTimeout = 1 |
| 172 | self.s.xonxoff = 1 |
| 173 | self.s.open() |
| 174 | self.s.write(serial.XOFF) |
| 175 | time.sleep(0.1) #some systems need a little delay so that they can react on XOFF |
| 176 | t1 = time.time() |
| 177 | self.failUnlessRaises(serial.SerialTimeoutException, self.s.write, "timeout please"*100) |
| 178 | t2 = time.time() |
| 179 | self.failUnless( 1 <= (t2-t1) < 2, "Timeout not in the given intervall (%s)" % (t2-t1)) |
| 180 | |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 181 | if __name__ == '__main__': |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 182 | import sys |
| 183 | print __doc__ |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 184 | print "Testing port", PORT |
cliechti | a135a67 | 2002-06-11 15:10:46 +0000 | [diff] [blame] | 185 | sys.argv.append('-v') |
cliechti | d6bf52c | 2003-10-01 02:28:12 +0000 | [diff] [blame] | 186 | # When this module is executed from the command-line, it runs all its tests |
cliechti | c813b21 | 2002-06-04 21:12:10 +0000 | [diff] [blame] | 187 | unittest.main() |