process.c: split struct_user_offsets into architecture-specific include files
* Makefile.am (EXTRA_DIST): Add linux/alpha/userent.h,
linux/arm/userent.h, linux/avr32/userent.h, linux/bfin/userent.h,
linux/crisv10/userent.h, linux/crisv32/userent.h,
linux/i386/userent.h, linux/i386/userent0.h, linux/ia64/userent.h,
linux/m68k/userent.h, linux/microblaze/userent.h,
linux/mips/userent.h, linux/or1k/userent.h, linux/powerpc/userent.h,
linux/s390/userent.h, linux/s390/userent0.h, linux/s390/userent1.h,
linux/s390x/userent.h, linux/sh/userent.h, linux/sh/userent0.h,
linux/sh64/userent.h, linux/sparc/userent.h, linux/sparc64/userent.h,
linux/tile/userent.h, linux/userent.h, linux/userent0.h,
linux/x32/userent.h, linux/x86_64/userent.h, and
linux/xtensa/userent.h.
* process.c (struct_user_offsets): Split into architecture-specific
include files, inculde userent.h.
diff --git a/linux/xtensa/userent.h b/linux/xtensa/userent.h
new file mode 100644
index 0000000..0bee717
--- /dev/null
+++ b/linux/xtensa/userent.h
@@ -0,0 +1,89 @@
+{ REG_A_BASE, "a0" },
+{ REG_A_BASE+1, "a1" },
+{ REG_A_BASE+2, "a2" },
+{ REG_A_BASE+3, "a3" },
+{ REG_A_BASE+4, "a4" },
+{ REG_A_BASE+5, "a5" },
+{ REG_A_BASE+6, "a6" },
+{ REG_A_BASE+7, "a7" },
+{ REG_A_BASE+8, "a8" },
+{ REG_A_BASE+9, "a9" },
+{ REG_A_BASE+10, "a10" },
+{ REG_A_BASE+11, "a11" },
+{ REG_A_BASE+12, "a12" },
+{ REG_A_BASE+13, "a13" },
+{ REG_A_BASE+14, "a14" },
+{ REG_A_BASE+15, "a15" },
+{ REG_PC, "pc" },
+{ SYSCALL_NR, "syscall_nr" },
+{ REG_AR_BASE, "ar0" },
+{ REG_AR_BASE+1, "ar1" },
+{ REG_AR_BASE+2, "ar2" },
+{ REG_AR_BASE+3, "ar3" },
+{ REG_AR_BASE+4, "ar4" },
+{ REG_AR_BASE+5, "ar5" },
+{ REG_AR_BASE+6, "ar6" },
+{ REG_AR_BASE+7, "ar7" },
+{ REG_AR_BASE+8, "ar8" },
+{ REG_AR_BASE+9, "ar9" },
+{ REG_AR_BASE+10, "ar10" },
+{ REG_AR_BASE+11, "ar11" },
+{ REG_AR_BASE+12, "ar12" },
+{ REG_AR_BASE+13, "ar13" },
+{ REG_AR_BASE+14, "ar14" },
+{ REG_AR_BASE+15, "ar15" },
+{ REG_AR_BASE+16, "ar16" },
+{ REG_AR_BASE+17, "ar17" },
+{ REG_AR_BASE+18, "ar18" },
+{ REG_AR_BASE+19, "ar19" },
+{ REG_AR_BASE+20, "ar20" },
+{ REG_AR_BASE+21, "ar21" },
+{ REG_AR_BASE+22, "ar22" },
+{ REG_AR_BASE+23, "ar23" },
+{ REG_AR_BASE+24, "ar24" },
+{ REG_AR_BASE+25, "ar25" },
+{ REG_AR_BASE+26, "ar26" },
+{ REG_AR_BASE+27, "ar27" },
+{ REG_AR_BASE+28, "ar28" },
+{ REG_AR_BASE+29, "ar29" },
+{ REG_AR_BASE+30, "ar30" },
+{ REG_AR_BASE+31, "ar31" },
+{ REG_AR_BASE+32, "ar32" },
+{ REG_AR_BASE+33, "ar33" },
+{ REG_AR_BASE+34, "ar34" },
+{ REG_AR_BASE+35, "ar35" },
+{ REG_AR_BASE+36, "ar36" },
+{ REG_AR_BASE+37, "ar37" },
+{ REG_AR_BASE+38, "ar38" },
+{ REG_AR_BASE+39, "ar39" },
+{ REG_AR_BASE+40, "ar40" },
+{ REG_AR_BASE+41, "ar41" },
+{ REG_AR_BASE+42, "ar42" },
+{ REG_AR_BASE+43, "ar43" },
+{ REG_AR_BASE+44, "ar44" },
+{ REG_AR_BASE+45, "ar45" },
+{ REG_AR_BASE+46, "ar46" },
+{ REG_AR_BASE+47, "ar47" },
+{ REG_AR_BASE+48, "ar48" },
+{ REG_AR_BASE+49, "ar49" },
+{ REG_AR_BASE+50, "ar50" },
+{ REG_AR_BASE+51, "ar51" },
+{ REG_AR_BASE+52, "ar52" },
+{ REG_AR_BASE+53, "ar53" },
+{ REG_AR_BASE+54, "ar54" },
+{ REG_AR_BASE+55, "ar55" },
+{ REG_AR_BASE+56, "ar56" },
+{ REG_AR_BASE+57, "ar57" },
+{ REG_AR_BASE+58, "ar58" },
+{ REG_AR_BASE+59, "ar59" },
+{ REG_AR_BASE+60, "ar60" },
+{ REG_AR_BASE+61, "ar61" },
+{ REG_AR_BASE+62, "ar62" },
+{ REG_AR_BASE+63, "ar63" },
+{ REG_LBEG, "lbeg" },
+{ REG_LEND, "lend" },
+{ REG_LCOUNT, "lcount" },
+{ REG_SAR, "sar" },
+{ REG_WB, "wb" },
+{ REG_WS, "ws" },
+{ REG_PS, "ps" },