[SubZero] Implement Fcmp, ICmp, Cast and Select for vector type
The patch scalarizes Fcmp, ICmp, Cast and Select for operands of vector type.
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/2412053002 .
Patch from Jaydeep Patil <jaydeep.patil@imgtec.com>.
diff --git a/src/IceOperand.h b/src/IceOperand.h
index 457a258..4b7cdfe 100644
--- a/src/IceOperand.h
+++ b/src/IceOperand.h
@@ -979,7 +979,7 @@
void setName(const Cfg *Func, const std::string &NewName) override {
Variable::setName(Func, NewName);
if (!Containers.empty()) {
- for (SizeT i = 0; i < ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < ContainersPerVector; ++i) {
Containers[i]->setName(Func, getName() + "__cont" + std::to_string(i));
}
}
@@ -995,7 +995,7 @@
const VarList &getContainers() const { return Containers; }
void initVecElement(Cfg *Func) {
- for (SizeT i = 0; i < ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < ContainersPerVector; ++i) {
Variable *Var = Func->makeVariable(IceType_i32);
Var->setIsArg(getIsArg());
if (BuildDefs::dump()) {
@@ -1011,13 +1011,13 @@
}
// A 128-bit vector value is mapped onto 4 32-bit register values.
- static constexpr SizeT ElementsPerContainer = 4;
+ static constexpr SizeT ContainersPerVector = 4;
protected:
VariableVecOn32(const Cfg *Func, OperandKind K, Type Ty, SizeT Index)
: Variable(Func, K, Ty, Index) {
assert(typeWidthInBytes(Ty) ==
- ElementsPerContainer * typeWidthInBytes(IceType_i32));
+ ContainersPerVector * typeWidthInBytes(IceType_i32));
}
VarList Containers;
diff --git a/src/IceTargetLowering.h b/src/IceTargetLowering.h
index 82ee5c7..b8bfff0 100644
--- a/src/IceTargetLowering.h
+++ b/src/IceTargetLowering.h
@@ -511,8 +511,11 @@
Variable *T = Func->makeVariable(DestTy);
if (auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T)) {
VarVecOn32->initVecElement(Func);
+ auto *Undef = ConstantUndef::create(Ctx, DestTy);
+ Context.insert<InstAssign>(T, Undef);
+ } else {
+ Context.insert<InstFakeDef>(T);
}
- Context.insert<InstFakeDef>(T);
for (SizeT I = 0; I < NumElements; ++I) {
auto *Index = Ctx->getConstantInt32(I);
diff --git a/src/IceTargetLoweringMIPS32.cpp b/src/IceTargetLoweringMIPS32.cpp
index b7d36a6..73f9919 100644
--- a/src/IceTargetLoweringMIPS32.cpp
+++ b/src/IceTargetLoweringMIPS32.cpp
@@ -238,13 +238,97 @@
void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
constexpr bool NoTailCall = false;
constexpr bool IsTargetHelperCall = true;
+ Variable *Dest = Instr->getDest();
+ const Type DestTy = Dest ? Dest->getType() : IceType_void;
switch (Instr->getKind()) {
default:
return;
+ case Inst::Select: {
+ if (isVectorType(DestTy)) {
+ Operand *SrcT = llvm::cast<InstSelect>(Instr)->getTrueOperand();
+ Operand *SrcF = llvm::cast<InstSelect>(Instr)->getFalseOperand();
+ Operand *Cond = llvm::cast<InstSelect>(Instr)->getCondition();
+ Variable *T = Func->makeVariable(DestTy);
+ auto *Undef = ConstantUndef::create(Ctx, DestTy);
+ Context.insert<InstAssign>(T, Undef);
+ auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
+ VarVecOn32->initVecElement(Func);
+ for (SizeT I = 0; I < typeNumElements(DestTy); ++I) {
+ auto *Index = Ctx->getConstantInt32(I);
+ auto *OpC = Func->makeVariable(typeElementType(Cond->getType()));
+ Context.insert<InstExtractElement>(OpC, Cond, Index);
+ auto *OpT = Func->makeVariable(typeElementType(DestTy));
+ Context.insert<InstExtractElement>(OpT, SrcT, Index);
+ auto *OpF = Func->makeVariable(typeElementType(DestTy));
+ Context.insert<InstExtractElement>(OpF, SrcF, Index);
+ auto *Dst = Func->makeVariable(typeElementType(DestTy));
+ Variable *DestT = Func->makeVariable(DestTy);
+ Context.insert<InstSelect>(Dst, OpC, OpT, OpF);
+ Context.insert<InstInsertElement>(DestT, T, Dst, Index);
+ T = DestT;
+ }
+ Context.insert<InstAssign>(Dest, T);
+ Instr->setDeleted();
+ }
+ return;
+ }
+ case Inst::Fcmp: {
+ if (isVectorType(DestTy)) {
+ InstFcmp::FCond Cond = llvm::cast<InstFcmp>(Instr)->getCondition();
+ Operand *Src0 = Instr->getSrc(0);
+ Operand *Src1 = Instr->getSrc(1);
+ Variable *T = Func->makeVariable(IceType_v4f32);
+ auto *Undef = ConstantUndef::create(Ctx, IceType_v4f32);
+ Context.insert<InstAssign>(T, Undef);
+ auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
+ VarVecOn32->initVecElement(Func);
+ for (SizeT I = 0; I < typeNumElements(IceType_v4f32); ++I) {
+ auto *Index = Ctx->getConstantInt32(I);
+ auto *Op0 = Func->makeVariable(IceType_f32);
+ Context.insert<InstExtractElement>(Op0, Src0, Index);
+ auto *Op1 = Func->makeVariable(IceType_f32);
+ Context.insert<InstExtractElement>(Op1, Src1, Index);
+ auto *Dst = Func->makeVariable(IceType_f32);
+ Variable *DestT = Func->makeVariable(IceType_v4f32);
+ Context.insert<InstFcmp>(Cond, Dst, Op0, Op1);
+ Context.insert<InstInsertElement>(DestT, T, Dst, Index);
+ T = DestT;
+ }
+ Context.insert<InstAssign>(Dest, T);
+ Instr->setDeleted();
+ }
+ return;
+ }
+ case Inst::Icmp: {
+ if (isVectorType(DestTy)) {
+ InstIcmp::ICond Cond = llvm::cast<InstIcmp>(Instr)->getCondition();
+ Operand *Src0 = Instr->getSrc(0);
+ Operand *Src1 = Instr->getSrc(1);
+ const Type SrcType = Src0->getType();
+ Variable *T = Func->makeVariable(DestTy);
+ auto *Undef = ConstantUndef::create(Ctx, DestTy);
+ Context.insert<InstAssign>(T, Undef);
+ auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
+ VarVecOn32->initVecElement(Func);
+ for (SizeT I = 0; I < typeNumElements(SrcType); ++I) {
+ auto *Index = Ctx->getConstantInt32(I);
+ auto *Op0 = Func->makeVariable(typeElementType(SrcType));
+ Context.insert<InstExtractElement>(Op0, Src0, Index);
+ auto *Op1 = Func->makeVariable(typeElementType(SrcType));
+ Context.insert<InstExtractElement>(Op1, Src1, Index);
+ auto *Dst = Func->makeVariable(typeElementType(DestTy));
+ Variable *DestT = Func->makeVariable(DestTy);
+ Context.insert<InstIcmp>(Cond, Dst, Op0, Op1);
+ Context.insert<InstInsertElement>(DestT, T, Dst, Index);
+ T = DestT;
+ }
+ Context.insert<InstAssign>(Dest, T);
+ Instr->setDeleted();
+ }
+ return;
+ }
case Inst::Arithmetic: {
- Variable *Dest = Instr->getDest();
- const Type DestTy = Dest->getType();
const InstArithmetic::OpKind Op =
llvm::cast<InstArithmetic>(Instr)->getOp();
if (isVectorType(DestTy)) {
@@ -307,12 +391,32 @@
llvm::report_fatal_error("Control flow should never have reached here.");
}
case Inst::Cast: {
- Variable *Dest = Instr->getDest();
Operand *Src0 = Instr->getSrc(0);
- const Type DestTy = Dest->getType();
const Type SrcTy = Src0->getType();
auto *CastInstr = llvm::cast<InstCast>(Instr);
const InstCast::OpKind CastKind = CastInstr->getCastKind();
+
+ if (isVectorType(DestTy)) {
+ Variable *T = Func->makeVariable(DestTy);
+ auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
+ VarVecOn32->initVecElement(Func);
+ auto *Undef = ConstantUndef::create(Ctx, DestTy);
+ Context.insert<InstAssign>(T, Undef);
+ for (SizeT I = 0; I < typeNumElements(DestTy); ++I) {
+ auto *Index = Ctx->getConstantInt32(I);
+ auto *Op = Func->makeVariable(typeElementType(SrcTy));
+ Context.insert<InstExtractElement>(Op, Src0, Index);
+ auto *Dst = Func->makeVariable(typeElementType(DestTy));
+ Variable *DestT = Func->makeVariable(DestTy);
+ Context.insert<InstCast>(CastKind, Dst, Op);
+ Context.insert<InstInsertElement>(DestT, T, Dst, Index);
+ T = DestT;
+ }
+ Context.insert<InstAssign>(Dest, T);
+ Instr->setDeleted();
+ return;
+ }
+
switch (CastKind) {
default:
return;
@@ -352,7 +456,7 @@
}
const bool SourceIs32 = SrcTy == IceType_i32;
const bool SourceIsSigned = CastKind == InstCast::Sitofp;
- const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType());
+ const bool DestIsF32 = isFloat32Asserting32Or64(DestTy);
RuntimeHelper RTHFunc = RuntimeHelper::H_Num;
if (SourceIsSigned) {
if (SourceIs32) {
@@ -416,7 +520,7 @@
Context.insert(Call);
// The PNaCl ABI disallows i8/i16 return types, so truncate the helper
// call result to the appropriate type as necessary.
- if (CallDest->getType() != Dest->getType())
+ if (CallDest->getType() != DestTy)
Context.insert<InstCast>(InstCast::Trunc, Dest, CallDest);
Instr->setDeleted();
return;
@@ -450,10 +554,9 @@
llvm::report_fatal_error("Control flow should never have reached here.");
}
case Inst::IntrinsicCall: {
- Variable *Dest = Instr->getDest();
auto *IntrinsicCall = llvm::cast<InstIntrinsicCall>(Instr);
Intrinsics::IntrinsicID ID = IntrinsicCall->getIntrinsicInfo().ID;
- if (Dest && isVectorType(Dest->getType()) && ID == Intrinsics::Fabs) {
+ if (isVectorType(DestTy) && ID == Intrinsics::Fabs) {
Operand *Src0 = IntrinsicCall->getArg(0);
GlobalString FabsFloat = Ctx->getGlobalString("llvm.fabs.f32");
Operand *CallTarget = Ctx->getConstantExternSym(FabsFloat);
@@ -464,11 +567,12 @@
Intrinsics::IntrinsicInfo Info = FullInfo->Info;
Variable *T = Func->makeVariable(IceType_v4f32);
- auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T);
+ auto *Undef = ConstantUndef::create(Ctx, IceType_v4f32);
+ Context.insert<InstAssign>(T, Undef);
+ auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
VarVecOn32->initVecElement(Func);
- Context.insert<InstFakeDef>(T);
- for (SizeT i = 0; i < VarVecOn32->ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < typeNumElements(IceType_v4f32); ++i) {
auto *Index = Ctx->getConstantInt32(i);
auto *Op = Func->makeVariable(IceType_f32);
Context.insert<InstExtractElement>(Op, Src0, Index);
@@ -1099,23 +1203,13 @@
// v4f32 is returned through stack. $4 is setup by the caller and passed as
// first argument implicitly. Callee then copies the return vector at $4.
+ Variable *ImplicitRetVec = nullptr;
if (isVectorFloatingType(Func->getReturnType())) {
- Variable *ImplicitRetVec = Func->makeVariable(IceType_i32);
+ ImplicitRetVec = Func->makeVariable(IceType_i32);
ImplicitRetVec->setName(Func, "ImplicitRet_v4f32");
ImplicitRetVec->setIsArg();
Args.insert(Args.begin(), ImplicitRetVec);
setImplicitRet(ImplicitRetVec);
- Context.insert<InstFakeDef>(ImplicitRetVec);
- for (CfgNode *Node : Func->getNodes()) {
- for (Inst &Instr : Node->getInsts()) {
- if (llvm::isa<InstRet>(&Instr)) {
- Context.setInsertPoint(Instr);
- Context.insert<InstFakeUse>(ImplicitRetVec);
- break;
- }
- }
- }
- Context.setInsertPoint(Context.getCur());
}
for (SizeT i = 0, E = Args.size(); i < E; ++i) {
@@ -1169,6 +1263,19 @@
}
Context.insert<InstAssign>(Arg, RegisterArg);
}
+
+ // Insert fake use of ImplicitRet_v4f32 to keep it live
+ if (ImplicitRetVec) {
+ for (CfgNode *Node : Func->getNodes()) {
+ for (Inst &Instr : Node->getInsts()) {
+ if (llvm::isa<InstRet>(&Instr)) {
+ Context.setInsertPoint(Instr);
+ Context.insert<InstFakeUse>(ImplicitRetVec);
+ break;
+ }
+ }
+ }
+ }
}
Type TargetMIPS32::stackSlotType() { return IceType_i32; }
@@ -2361,7 +2468,7 @@
return;
}
if (isVectorType(Dest->getType())) {
- UnimplementedLoweringError(this, Instr);
+ llvm::report_fatal_error("Arithmetic: Destination type is vector");
return;
}
@@ -2509,6 +2616,20 @@
return;
}
+ // Source type may not be same as destination
+ if (isVectorType(Dest->getType())) {
+ Operand *Src0 = legalizeUndef(Instr->getSrc(0));
+ auto *DstVec = llvm::dyn_cast<VariableVecOn32>(Dest);
+ for (SizeT i = 0; i < DstVec->ContainersPerVector; ++i) {
+ auto *DCont = DstVec->getContainers()[i];
+ auto *SCont =
+ legalize(getOperandAtIndex(Src0, IceType_i32, i), Legal_Reg);
+ auto *TReg = makeReg(IceType_i32);
+ _mov(TReg, SCont);
+ _mov(DCont, TReg);
+ }
+ return;
+ }
Operand *Src0 = Instr->getSrc(0);
assert(Dest->getType() == Src0->getType());
if (Dest->getType() == IceType_i64) {
@@ -2524,18 +2645,6 @@
_mov(DestHi, T_Hi);
return;
}
- if (isVectorType(Dest->getType())) {
- auto *DstVec = llvm::dyn_cast<VariableVecOn32>(Dest);
- for (SizeT i = 0; i < DstVec->ElementsPerContainer; ++i) {
- auto *DCont = DstVec->getContainers()[i];
- auto *SCont =
- legalize(getOperandAtIndex(Src0, IceType_i32, i), Legal_Reg);
- auto *TReg = makeReg(IceType_i32);
- _mov(TReg, SCont);
- _mov(DCont, TReg);
- }
- return;
- }
Operand *SrcR;
if (Dest->hasReg()) {
// If Dest already has a physical register, then legalize the Src operand
@@ -2944,7 +3053,7 @@
ReturnReg = makeReg(Dest->getType(), RegMIPS32::Reg_V0);
auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg);
RetVec->initVecElement(Func);
- for (SizeT i = 0; i < RetVec->ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < RetVec->ContainersPerVector; ++i) {
auto *Var = RetVec->getContainers()[i];
Var->setRegNum(RegNumT::fixme(RegMIPS32::Reg_V0 + i));
}
@@ -3035,7 +3144,7 @@
if (ReturnReg) {
if (RetVecFloat) {
auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
- for (SizeT i = 0; i < DestVecOn32->ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
auto *Var = DestVecOn32->getContainers()[i];
OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
Func, IceType_i32, RetVecFloat,
@@ -3044,7 +3153,7 @@
}
} else if (auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg)) {
auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
- for (SizeT i = 0; i < DestVecOn32->ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
_mov(DestVecOn32->getContainers()[i], RetVec->getContainers()[i]);
}
} else if (ReturnRegHi) {
@@ -3080,7 +3189,7 @@
: (1 << (CHAR_BITS * typeWidthInBytes(Src0Ty))) - 1);
if (isVectorType(DestTy)) {
- UnimplementedLoweringError(this, Instr);
+ llvm::report_fatal_error("Cast: Destination type is vector");
return;
}
switch (CastKind) {
@@ -3243,6 +3352,11 @@
lowerAssign(Assign);
return;
}
+ if (isVectorType(DestTy) || isVectorType(Src0->getType())) {
+ llvm::report_fatal_error(
+ "Bitcast: vector type should have been prelowered.");
+ return;
+ }
switch (DestTy) {
case IceType_NUM:
case IceType_void:
@@ -3292,16 +3406,6 @@
}
break;
}
- case IceType_v8i1:
- assert(Src0->getType() == IceType_i8);
- llvm::report_fatal_error(
- "v8i1 to i8 conversion should have been prelowered.");
- break;
- case IceType_v16i1:
- assert(Src0->getType() == IceType_i16);
- llvm::report_fatal_error(
- "v16i1 to i16 conversion should have been prelowered.");
- break;
default:
UnimplementedLoweringError(this, Instr);
}
@@ -3322,7 +3426,7 @@
auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0);
// Number of elements in each container
uint32_t ElemPerCont =
- typeNumElements(Src0->getType()) / Src0R->ElementsPerContainer;
+ typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
// Position of the element in the container
uint32_t PosInCont = Index % ElemPerCont;
@@ -3362,8 +3466,9 @@
}
}
if (typeElementType(Src0R->getType()) == IceType_i1) {
- _andi(TReg, TDest, 0x1);
- _mov(Dest, TReg);
+ Variable *TReg1 = makeReg(DestTy);
+ _andi(TReg1, TDest, 0x1);
+ _mov(Dest, TReg1);
} else {
_mov(Dest, TDest);
}
@@ -3375,7 +3480,7 @@
void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
Variable *Dest = Instr->getDest();
if (isVectorType(Dest->getType())) {
- UnimplementedLoweringError(this, Instr);
+ llvm::report_fatal_error("Fcmp: Destination type is vector");
return;
}
@@ -3384,7 +3489,7 @@
auto *Zero = getZero();
InstFcmp::FCond Cond = Instr->getCondition();
- auto *DestR = makeReg(Dest->getType());
+ auto *DestR = makeReg(IceType_i32);
auto *Src0R = legalizeToReg(Src0);
auto *Src1R = legalizeToReg(Src1);
const Type Src0Ty = Src0->getType();
@@ -3722,7 +3827,7 @@
}
Variable *Dest = Instr->getDest();
if (isVectorType(Dest->getType())) {
- UnimplementedLoweringError(this, Instr);
+ llvm::report_fatal_error("Icmp: Destination type is vector");
return;
}
InstIcmp::ICond Cond = Instr->getCondition();
@@ -3828,14 +3933,13 @@
if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2)) {
const uint32_t Index = Imm->getValue();
// Vector to insert in
- auto *Src0 = Instr->getSrc(0);
+ auto *Src0 = legalizeUndef(Instr->getSrc(0));
auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0);
// Number of elements in each container
uint32_t ElemPerCont =
- typeNumElements(Src0->getType()) / Src0R->ElementsPerContainer;
+ typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
// Source Element
auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
- Context.insert<InstFakeDef>(SrcE);
// Dest is a vector
auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest);
VDest->initVecElement(Func);
@@ -3855,7 +3959,7 @@
// Position of the element in the container
uint32_t PosInCont = Index % ElemPerCont;
// Load source vector in a temporary vector
- for (SizeT i = 0; i < TVDest->ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < TVDest->ContainersPerVector; ++i) {
auto *DCont = TVDest->getContainers()[i];
// Do not define DstE as we are going to redefine it
if (DCont == DstE)
@@ -4406,7 +4510,6 @@
}
if (isVectorType(Ty)) {
- UnimplementedError(getFlags());
return nullptr;
}
@@ -4549,7 +4652,7 @@
Reg = getImplicitRet();
auto *RegT = legalizeToReg(Reg);
// Return the vector through buffer in implicit argument a0
- for (SizeT i = 0; i < SrcVec->ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < SrcVec->ContainersPerVector; ++i) {
OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
Func, IceType_f32, RegT,
llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4)));
@@ -4575,7 +4678,7 @@
const Type DestTy = Dest->getType();
if (isVectorType(DestTy)) {
- UnimplementedLoweringError(this, Instr);
+ llvm::report_fatal_error("Select: Destination type is vector");
return;
}
@@ -4647,7 +4750,7 @@
_sw(ValueLo, llvm::cast<OperandMIPS32Mem>(loOperand(NewAddr)));
} else if (isVectorType(Value->getType())) {
auto *DataVec = llvm::dyn_cast<VariableVecOn32>(Value);
- for (SizeT i = 0; i < DataVec->ElementsPerContainer; ++i) {
+ for (SizeT i = 0; i < DataVec->ContainersPerVector; ++i) {
auto *DCont = legalizeToReg(DataVec->getContainers()[i]);
auto *MCont = llvm::cast<OperandMIPS32Mem>(
getOperandAtIndex(NewAddr, IceType_i32, i));
diff --git a/tests_lit/llvm2ice_tests/fp.cmp.ll b/tests_lit/llvm2ice_tests/fp.cmp.ll
index 6490819..1ba8815 100644
--- a/tests_lit/llvm2ice_tests/fp.cmp.ll
+++ b/tests_lit/llvm2ice_tests/fp.cmp.ll
@@ -379,8 +379,8 @@
; ARM32-LABEL: fcmpFalseFloat
; ARM32: mov [[R:r[0-9]+]], #0
; MIPS32-LABEL: fcmpFalseFloat
-; MIPS32: addiu
-; MIPS32: sb
+; MIPS32: addiu [[R:.*]], $zero, 0
+; MIPS32: andi [[R]], [[R]], 1
define internal i32 @fcmpFalseDouble(double %a, double %b) {
entry:
@@ -393,8 +393,8 @@
; ARM32-LABEL: fcmpFalseDouble
; ARM32: mov [[R:r[0-9]+]], #0
; MIPS32-LABEL: fcmpFalseDouble
-; MIPS32: addiu
-; MIPS32: sb
+; MIPS32: addiu [[R:.*]], $zero, 0
+; MIPS32: andi [[R]], [[R]], 1
define internal i32 @fcmpOeqFloat(float %a, float %b) {
entry:
@@ -975,8 +975,8 @@
; ARM32-LABEL: fcmpTrueFloat
; ARM32: mov {{r[0-9]+}}, #1
; MIPS32-LABEL: fcmpTrueFloat
-; MIPS32: addiu
-; MIPS32: sb
+; MIPS32: addiu [[R:.*]], $zero, 1
+; MIPS32: andi [[R]], [[R]], 1
define internal i32 @fcmpTrueDouble(double %a, double %b) {
entry:
@@ -989,8 +989,8 @@
; ARM32-LABEL: fcmpTrueDouble
; ARM32: mov {{r[0-9]+}}, #1
; MIPS32-LABEL: fcmpTrueDouble
-; MIPS32: addiu
-; MIPS32: sb
+; MIPS32: addiu [[R:.*]], $zero, 1
+; MIPS32: andi [[R]], [[R]], 1
define internal float @selectFloatVarVar(float %a, float %b) {
entry:
diff --git a/tests_lit/llvm2ice_tests/vector-align.ll b/tests_lit/llvm2ice_tests/vector-align.ll
index 7173140..5e27837 100644
--- a/tests_lit/llvm2ice_tests/vector-align.ll
+++ b/tests_lit/llvm2ice_tests/vector-align.ll
@@ -7,6 +7,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
+; RUN: -i %s --args -O2 --skip-unimplemented \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
define internal <4 x i32> @test_add(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
@@ -18,6 +24,12 @@
; CHECK-NOT: paddd xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: paddd xmm{{.}},
+; MIPS32-LABEL: test_add
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+
define internal <4 x i32> @test_and(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
@@ -29,6 +41,12 @@
; CHECK-NOT: pand xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: pand xmm{{.}},
+; MIPS32-LABEL: test_and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+
define internal <4 x i32> @test_or(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
@@ -40,6 +58,12 @@
; CHECK-NOT: por xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: por xmm{{.}},
+; MIPS32-LABEL: test_or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+
define internal <4 x i32> @test_xor(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
@@ -51,6 +75,12 @@
; CHECK-NOT: pxor xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: pxor xmm{{.}},
+; MIPS32-LABEL: test_xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+
define internal <4 x i32> @test_sub(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
@@ -62,6 +92,12 @@
; CHECK-NOT: psubd xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: psubd xmm{{.}},
+; MIPS32-LABEL: test_sub
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+
define internal <4 x float> @test_fadd(i32 %addr_i, <4 x float> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x float>*
@@ -73,6 +109,12 @@
; CHECK-NOT: addps xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: addps xmm{{.}},
+; MIPS32-LABEL: test_fadd
+; MIPS32: add.s
+; MIPS32: add.s
+; MIPS32: add.s
+; MIPS32: add.s
+
define internal <4 x float> @test_fsub(i32 %addr_i, <4 x float> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x float>*
@@ -83,3 +125,9 @@
; CHECK-LABEL: test_fsub
; CHECK-NOT: subps xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: subps xmm{{.}},
+
+; MIPS32-LABEL: test_fsub
+; MIPS32: sub.s
+; MIPS32: sub.s
+; MIPS32: sub.s
+; MIPS32: sub.s
diff --git a/tests_lit/llvm2ice_tests/vector-fcmp.ll b/tests_lit/llvm2ice_tests/vector-fcmp.ll
index 97e438b..9703d15 100644
--- a/tests_lit/llvm2ice_tests/vector-fcmp.ll
+++ b/tests_lit/llvm2ice_tests/vector-fcmp.ll
@@ -4,6 +4,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble -a -O2 | FileCheck %s
; RUN: %p2i -i %s --filetype=obj --disassemble -a -Om1 | FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
+; RUN: -i %s --args -O2 --skip-unimplemented \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; Check that sext elimination occurs when the result of the comparison
; instruction is alrady sign extended. Sign extension to 4 x i32 uses
; the pslld instruction.
@@ -16,6 +22,19 @@
; CHECK: cmpeqps
; CHECK-NOT: pslld
}
+; MIPS32-LABEL: sextElimination
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpFalseVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -25,6 +44,11 @@
; CHECK-LABEL: fcmpFalseVector
; CHECK: pxor
}
+; MIPS32-LABEL: fcmpFalseVector
+; MIPS32: li v0,0
+; MIPS32: li v1,0
+; MIPS32: li a0,0
+; MIPS32: li a1,0
define internal <4 x i32> @fcmpOeqVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -34,6 +58,19 @@
; CHECK-LABEL: fcmpOeqVector
; CHECK: cmpeqps
}
+; MIPS32-LABEL: fcmpOeqVector
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOgeVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -43,6 +80,19 @@
; CHECK-LABEL: fcmpOgeVector
; CHECK: cmpleps
}
+; MIPS32-LABEL: fcmpOgeVector
+; MIPS32: c.ult.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ult.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ult.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ult.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOgtVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -52,6 +102,19 @@
; CHECK-LABEL: fcmpOgtVector
; CHECK: cmpltps
}
+; MIPS32-LABEL: fcmpOgtVector
+; MIPS32: c.ule.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ule.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ule.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ule.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOleVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -61,6 +124,19 @@
; CHECK-LABEL: fcmpOleVector
; CHECK: cmpleps
}
+; MIPS32-LABEL: fcmpOleVector
+; MIPS32: c.ole.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ole.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ole.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ole.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOltVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -70,6 +146,19 @@
; CHECK-LABEL: fcmpOltVector
; CHECK: cmpltps
}
+; MIPS32-LABEL: fcmpOltVector
+; MIPS32: c.olt.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.olt.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.olt.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.olt.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOneVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -81,6 +170,19 @@
; CHECK: cmpordps
; CHECK: pand
}
+; MIPS32-LABEL: fcmpOneVector
+; MIPS32: c.ueq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ueq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ueq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ueq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOrdVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -90,6 +192,19 @@
; CHECK-LABEL: fcmpOrdVector
; CHECK: cmpordps
}
+; MIPS32-LABEL: fcmpOrdVector
+; MIPS32: c.un.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.un.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.un.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.un.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpTrueVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -99,6 +214,11 @@
; CHECK-LABEL: fcmpTrueVector
; CHECK: pcmpeqd
}
+; MIPS32-LABEL: fcmpTrueVector
+; MIPS32: li v0,1
+; MIPS32: li v1,1
+; MIPS32: li a0,1
+; MIPS32: li a1,1
define internal <4 x i32> @fcmpUeqVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -110,6 +230,19 @@
; CHECK: cmpunordps
; CHECK: por
}
+; MIPS32-LABEL: fcmpUeqVector
+; MIPS32: c.ueq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ueq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ueq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ueq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUgeVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -119,6 +252,19 @@
; CHECK-LABEL: fcmpUgeVector
; CHECK: cmpnltps
}
+; MIPS32-LABEL: fcmpUgeVector
+; MIPS32: c.olt.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.olt.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.olt.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.olt.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUgtVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -128,6 +274,19 @@
; CHECK-LABEL: fcmpUgtVector
; CHECK: cmpnleps
}
+; MIPS32-LABEL: fcmpUgtVector
+; MIPS32: c.ole.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ole.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ole.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.ole.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUleVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -137,6 +296,19 @@
; CHECK-LABEL: fcmpUleVector
; CHECK: cmpnltps
}
+; MIPS32-LABEL: fcmpUleVector
+; MIPS32: c.ule.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ule.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ule.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ule.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUltVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -146,6 +318,19 @@
; CHECK-LABEL: fcmpUltVector
; CHECK: cmpnleps
}
+; MIPS32-LABEL: fcmpUltVector
+; MIPS32: c.ult.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ult.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ult.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.ult.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUneVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -155,6 +340,19 @@
; CHECK-LABEL: fcmpUneVector
; CHECK: cmpneqps
}
+; MIPS32-LABEL: fcmpUneVector
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
+; MIPS32: c.eq.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUnoVector(<4 x float> %a, <4 x float> %b) {
entry:
@@ -164,3 +362,16 @@
; CHECK-LABEL: fcmpUnoVector
; CHECK: cmpunordps
}
+; MIPS32-LABEL: fcmpUnoVector
+; MIPS32: c.un.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.un.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.un.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
+; MIPS32: c.un.s
+; MIPS32: li [[R:.*]],1
+; MIPS32: movf [[R]],zero,$fcc0
diff --git a/tests_lit/llvm2ice_tests/vector-icmp.ll b/tests_lit/llvm2ice_tests/vector-icmp.ll
index 57adc94..c0b8e86 100644
--- a/tests_lit/llvm2ice_tests/vector-icmp.ll
+++ b/tests_lit/llvm2ice_tests/vector-icmp.ll
@@ -4,9 +4,15 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
+; RUN: -i %s --args -O2 --skip-unimplemented \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; Check that sext elimination occurs when the result of the comparison
-; instruction is alrady sign extended. Sign extension to 4 x i32 uses
-; the pslld instruction.
+; instruction is already sign extended. Sign extension to 4 x i32 uses
+; the pslld instruction on x86.
define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) {
entry:
%res.trunc = icmp eq <4 x i32> %a, %b
@@ -15,6 +21,36 @@
; CHECK-LABEL: test_sext_elimination
; CHECK: pcmpeqd
; CHECK-NOT: pslld
+
+; MIPS32-LABEL: test_sext_elimination
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]]
+; MIPS32: sltiu [[R_E0]],[[R_E0]],1
+; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]]
+; MIPS32: sltiu [[R_E1]],[[R_E1]],1
+; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]]
+; MIPS32: sltiu [[R_E2]],[[R_E2]],1
+; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]]
+; MIPS32: sltiu [[R_E3]],[[R_E3]],1
+; MIPS32: andi [[R_E0]],[[R_E0]],0x1
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: sra [[R_E0]],[[R_E0]],0x1f
+; MIPS32: andi [[R_E1]],[[R_E1]],0x1
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: sra [[R_E1]],[[R_E1]],0x1f
+; MIPS32: andi [[R_E2]],[[R_E2]],0x1
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: sra [[R_E2]],[[R_E2]],0x1f
+; MIPS32: andi [[R_E3]],[[R_E3]],0x1
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: sra [[R_E3]],[[R_E3]],0x1f
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <4 x i1> @test_icmp_v4i32_eq(<4 x i32> %a, <4 x i32> %b) {
@@ -23,6 +59,24 @@
ret <4 x i1> %res
; CHECK-LABEL: test_icmp_v4i32_eq
; CHECK: pcmpeqd
+
+; MIPS32-LABEL: test_icmp_v4i32_eq
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]]
+; MIPS32: sltiu [[R_E0]],[[R_E0]],1
+; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]]
+; MIPS32: sltiu [[R_E1]],[[R_E1]],1
+; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]]
+; MIPS32: sltiu [[R_E2]],[[R_E2]],1
+; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]]
+; MIPS32: sltiu [[R_E3]],[[R_E3]],1
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <4 x i1> @test_icmp_v4i32_ne(<4 x i32> %a, <4 x i32> %b) {
@@ -32,6 +86,24 @@
; CHECK-LABEL: test_icmp_v4i32_ne
; CHECK: pcmpeqd
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v4i32_ne
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]]
+; MIPS32: sltu [[R_E0]],zero,[[R_E0]]
+; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]]
+; MIPS32: sltu [[R_E1]],zero,[[R_E1]]
+; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]]
+; MIPS32: sltu [[R_E2]],zero,[[R_E2]]
+; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]]
+; MIPS32: sltu [[R_E3]],zero,[[R_E3]]
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <4 x i1> @test_icmp_v4i32_sgt(<4 x i32> %a, <4 x i32> %b) {
@@ -39,6 +111,16 @@
%res = icmp sgt <4 x i32> %a, %b
ret <4 x i1> %res
; CHECK: pcmpgtd
+
+; MIPS32-LABEL: test_icmp_v4i32_sgt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: slt [[R_E0:.*]],[[B_E0]],a0
+; MIPS32: slt [[R_E1:.*]],[[B_E1]],a1
+; MIPS32: slt [[R_E2:.*]],[[B_E2]],a2
+; MIPS32: slt [[R_E3:.*]],[[B_E3]],a3
}
define internal <4 x i1> @test_icmp_v4i32_sle(<4 x i32> %a, <4 x i32> %b) {
@@ -48,6 +130,20 @@
; CHECK-LABEL: test_icmp_v4i32_sle
; CHECK: pcmpgtd
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v4i32_sle
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: slt [[R_E0:.*]],[[B_E0]],a0
+; MIPS32: xori [[R_E0]],[[R_E0]],0x1
+; MIPS32: slt [[R_E1:.*]],[[B_E1]],a1
+; MIPS32: xori [[R_E1]],[[R_E1]],0x1
+; MIPS32: slt [[R_E2:.*]],[[B_E2]],a2
+; MIPS32: xori [[R_E2]],[[R_E2]],0x1
+; MIPS32: slt [[R_E3:.*]],[[B_E3]],a3
+; MIPS32: xori [[R_E3]],[[R_E3]],0x1
}
define internal <4 x i1> @test_icmp_v4i32_slt(<4 x i32> %a, <4 x i32> %b) {
@@ -56,6 +152,16 @@
ret <4 x i1> %res
; CHECK-LABEL: test_icmp_v4i32_slt
; CHECK: pcmpgtd
+
+; MIPS32-LABEL: test_icmp_v4i32_slt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: slt [[R_E0:.*]],a0,[[B_E0]]
+; MIPS32: slt [[R_E1:.*]],a1,[[B_E1]]
+; MIPS32: slt [[R_E2:.*]],a2,[[B_E2]]
+; MIPS32: slt [[R_E3:.*]],a3,[[B_E3]]
}
define internal <4 x i1> @test_icmp_v4i32_uge(<4 x i32> %a, <4 x i32> %b) {
@@ -66,6 +172,20 @@
; CHECK: pxor
; CHECK: pcmpgtd
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v4i32_uge
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: sltu [[R_E0:.*]],a0,[[B_E0]]
+; MIPS32: xori [[R_E0]],[[R_E0]],0x1
+; MIPS32: sltu [[R_E1:.*]],a1,[[B_E1]]
+; MIPS32: xori [[R_E1]],[[R_E1]],0x1
+; MIPS32: sltu [[R_E2:.*]],a2,[[B_E2]]
+; MIPS32: xori [[R_E2]],[[R_E2]],0x1
+; MIPS32: sltu [[R_E3:.*]],a3,[[B_E3]]
+; MIPS32: xori [[R_E3]],[[R_E3]],0x1
}
define internal <4 x i1> @test_icmp_v4i32_ugt(<4 x i32> %a, <4 x i32> %b) {
@@ -75,6 +195,16 @@
; CHECK-LABEL: test_icmp_v4i32_ugt
; CHECK: pxor
; CHECK: pcmpgtd
+
+; MIPS32-LABEL: test_icmp_v4i32_ugt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: sltu [[R_E0:.*]],[[B_E0]],a0
+; MIPS32: sltu [[R_E1:.*]],[[B_E1]],a1
+; MIPS32: sltu [[R_E2:.*]],[[B_E2]],a2
+; MIPS32: sltu [[R_E3:.*]],[[B_E3]],a3
}
define internal <4 x i1> @test_icmp_v4i32_ule(<4 x i32> %a, <4 x i32> %b) {
@@ -85,6 +215,20 @@
; CHECK: pxor
; CHECK: pcmpgtd
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v4i32_ule
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: sltu [[R_E0:.*]],[[B_E0]],a0
+; MIPS32: xori [[R_E0]],[[R_E0]],0x1
+; MIPS32: sltu [[R_E1:.*]],[[B_E1]],a1
+; MIPS32: xori [[R_E1]],[[R_E1]],0x1
+; MIPS32: sltu [[R_E2:.*]],[[B_E2]],a2
+; MIPS32: xori [[R_E2]],[[R_E2]],0x1
+; MIPS32: sltu [[R_E3:.*]],[[B_E3]],a3
+; MIPS32: xori [[R_E3]],[[R_E3]],0x1
}
define internal <4 x i1> @test_icmp_v4i32_ult(<4 x i32> %a, <4 x i32> %b) {
@@ -94,6 +238,16 @@
; CHECK-LABEL: test_icmp_v4i32_ult
; CHECK: pxor
; CHECK: pcmpgtd
+
+; MIPS32-LABEL: test_icmp_v4i32_ult
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: sltu [[R_E0:.*]],a0,[[B_E0]]
+; MIPS32: sltu [[R_E1:.*]],a1,[[B_E1]]
+; MIPS32: sltu [[R_E2:.*]],a2,[[B_E2]]
+; MIPS32: sltu [[R_E3:.*]],a3,[[B_E3]]
}
define internal <4 x i1> @test_icmp_v4i1_eq(<4 x i1> %a, <4 x i1> %b) {
@@ -102,6 +256,40 @@
ret <4 x i1> %res
; CHECK-LABEL: test_icmp_v4i1_eq
; CHECK: pcmpeqd
+
+; MIPS32-LABEL: test_icmp_v4i1_eq
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[R_E0:.*]],a0,0x1
+; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: xor [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: sltiu [[R_E0]],[[R_E0]],1
+; MIPS32: andi [[R_E1:.*]],a1,0x1
+; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: xor [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: sltiu [[R_E1]],[[R_E1]],1
+; MIPS32: andi [[R_E2:.*]],a2,0x1
+; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: xor [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: sltiu [[R_E2]],[[R_E2]],1
+; MIPS32: andi [[R_E3:.*]],a3,0x1
+; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: xor [[R_E3]],[[R_E3]],[[T_E3]]
+; MIPS32: sltiu [[R_E3]],[[R_E3]],1
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <4 x i1> @test_icmp_v4i1_ne(<4 x i1> %a, <4 x i1> %b) {
@@ -111,6 +299,40 @@
; CHECK-LABEL: test_icmp_v4i1_ne
; CHECK: pcmpeqd
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v4i1_ne
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[R_E0:.*]],a0,0x1
+; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: xor [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: sltu [[R_E0]],zero,[[R_E0]]
+; MIPS32: andi [[R_E1:.*]],a1,0x1
+; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: xor [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: sltu [[R_E1]],zero,[[R_E1]]
+; MIPS32: andi [[R_E2:.*]],a2,0x1
+; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: xor [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: sltu [[R_E2]],zero,[[R_E2]]
+; MIPS32: andi [[R_E3:.*]],a3,0x1
+; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: xor [[R_E3]],[[R_E3]],[[T_E3]]
+; MIPS32: sltu [[R_E3]],zero,[[R_E3]]
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <4 x i1> @test_icmp_v4i1_sgt(<4 x i1> %a, <4 x i1> %b) {
@@ -119,6 +341,32 @@
ret <4 x i1> %res
; CHECK-LABEL: test_icmp_v4i1_sgt
; CHECK: pcmpgtd
+
+; MIPS32-LABEL: test_icmp_v4i1_sgt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[T_E0:.*]],a0,0x1
+; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: andi [[T_E1:.*]],a1,0x1
+; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: andi [[T_E2:.*]],a2,0x1
+; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: andi [[T_E3:.*]],a3,0x1
+; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]]
}
define internal <4 x i1> @test_icmp_v4i1_sle(<4 x i1> %a, <4 x i1> %b) {
@@ -128,6 +376,36 @@
; CHECK-LABEL: test_icmp_v4i1_sle
; CHECK: pcmpgtd
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v4i1_sle
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[T_E0:.*]],a0,0x1
+; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: xori [[R_E0]],[[R_E0]],0x1
+; MIPS32: andi [[T_E1:.*]],a1,0x1
+; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: xori [[R_E1]],[[R_E1]],0x1
+; MIPS32: andi [[T_E2:.*]],a2,0x1
+; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: xori [[R_E2]],[[R_E2]],0x1
+; MIPS32: andi [[T_E3:.*]],a3,0x1
+; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]]
+; MIPS32: xori [[R_E3]],[[R_E3]],0x1
}
define internal <4 x i1> @test_icmp_v4i1_slt(<4 x i1> %a, <4 x i1> %b) {
@@ -136,6 +414,36 @@
ret <4 x i1> %res
; CHECK-LABEL: test_icmp_v4i1_slt
; CHECK: pcmpgtd
+
+; MIPS32-LABEL: test_icmp_v4i1_slt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[R_E0:.*]],a0,0x1
+; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: andi [[R_E1:.*]],a1,0x1
+; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: andi [[R_E2:.*]],a2,0x1
+; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: andi [[R_E3:.*]],a3,0x1
+; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]]
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <4 x i1> @test_icmp_v4i1_uge(<4 x i1> %a, <4 x i1> %b) {
@@ -146,6 +454,40 @@
; CHECK: pxor
; CHECK: pcmpgtd
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v4i1_uge
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[R_E0:.*]],a0,0x1
+; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: xori [[R_E0]],[[R_E0]],0x1
+; MIPS32: andi [[R_E1:.*]],a1,0x1
+; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: xori [[R_E1]],[[R_E1]],0x1
+; MIPS32: andi [[R_E2:.*]],a2,0x1
+; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: xori [[R_E2]],[[R_E2]],0x1
+; MIPS32: andi [[R_E3:.*]],a3,0x1
+; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]]
+; MIPS32: xori [[R_E3]],[[R_E3]],0x1
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <4 x i1> @test_icmp_v4i1_ugt(<4 x i1> %a, <4 x i1> %b) {
@@ -155,6 +497,32 @@
; CHECK-LABEL: test_icmp_v4i1_ugt
; CHECK: pxor
; CHECK: pcmpgtd
+
+; MIPS32-LABEL: test_icmp_v4i1_ugt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[T_E0:.*]],a0,0x1
+; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: andi [[T_E1:.*]],a1,0x1
+; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: andi [[T_E2:.*]],a2,0x1
+; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: andi [[T_E3:.*]],a3,0x1
+; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]]
}
define internal <4 x i1> @test_icmp_v4i1_ule(<4 x i1> %a, <4 x i1> %b) {
@@ -165,6 +533,36 @@
; CHECK: pxor
; CHECK: pcmpgtd
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v4i1_ule
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[T_E0:.*]],a0,0x1
+; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: xori [[R_E0]],[[R_E0]],0x1
+; MIPS32: andi [[T_E1:.*]],a1,0x1
+; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: xori [[R_E1]],[[R_E1]],0x1
+; MIPS32: andi [[T_E2:.*]],a2,0x1
+; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: xori [[R_E2]],[[R_E2]],0x1
+; MIPS32: andi [[T_E3:.*]],a3,0x1
+; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]]
+; MIPS32: xori [[R_E3]],[[R_E3]],0x1
}
define internal <4 x i1> @test_icmp_v4i1_ult(<4 x i1> %a, <4 x i1> %b) {
@@ -174,6 +572,36 @@
; CHECK-LABEL: test_icmp_v4i1_ult
; CHECK: pxor
; CHECK: pcmpgtd
+
+; MIPS32-LABEL: test_icmp_v4i1_ult
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: andi [[R_E0:.*]],a0,0x1
+; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1
+; MIPS32: sll [[R_E0]],[[R_E0]],0x1f
+; MIPS32: sll [[T_E0]],[[T_E0]],0x1f
+; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]]
+; MIPS32: andi [[R_E1:.*]],a1,0x1
+; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1
+; MIPS32: sll [[R_E1]],[[R_E1]],0x1f
+; MIPS32: sll [[T_E1]],[[T_E1]],0x1f
+; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]]
+; MIPS32: andi [[R_E2:.*]],a2,0x1
+; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1
+; MIPS32: sll [[R_E2]],[[R_E2]],0x1f
+; MIPS32: sll [[T_E2]],[[T_E2]],0x1f
+; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]]
+; MIPS32: andi [[R_E3:.*]],a3,0x1
+; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1
+; MIPS32: sll [[R_E3]],[[R_E3]],0x1f
+; MIPS32: sll [[T_E3]],[[T_E3]],0x1f
+; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]]
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <8 x i1> @test_icmp_v8i16_eq(<8 x i16> %a, <8 x i16> %b) {
@@ -182,6 +610,109 @@
ret <8 x i1> %res
; CHECK-LABEL: test_icmp_v8i16_eq
; CHECK: pcmpeqw
+
+; MIPS32-LABEL: test_icmp_v8i16_eq
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; *** icmp a[0] and b[0] ***
+; MIPS32: andi [[T2:.*]],a0,0xffff
+; MIPS32: andi [[T3:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: xor [[T2]],[[T2]],[[T3]]
+; MIPS32: sltiu [[T2]],[[T2]],1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T4:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; *** icmp a[1] and b[1] ***
+; MIPS32: srl [[R_E0:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[R_E0]],[[R_E0]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: xor [[R_E0]],[[R_E0]],[[T5]]
+; MIPS32: sltiu [[R_E0]],[[R_E0]],1
+; MIPS32: sll [[R_E0]],[[R_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E0]],[[R_E0]],[[T2]]
+; *** icmp a[2] and b[2] ***
+; MIPS32: andi [[T2:.*]],a1,0xffff
+; MIPS32: andi [[T3:.*]],[[B_E1]],0xffff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: xor [[T2]],[[T2]],[[T3]]
+; MIPS32: sltiu [[T2]],[[T2]],1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T4:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; *** icmp a[3] and b[3] ***
+; MIPS32: srl [[R_E1:.*]],a1,0x10
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: sll [[R_E1]],[[R_E1]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: xor [[R_E1]],[[R_E1]],[[T5]]
+; MIPS32: sltiu [[R_E1]],[[R_E1]],1
+; MIPS32: sll [[R_E1]],[[R_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E1]],[[R_E1]],[[T2]]
+; *** icmp a[4] and b[4] ***
+; MIPS32: andi [[T2:.*]],a2,0xffff
+; MIPS32: andi [[T3:.*]],[[B_E2]],0xffff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: xor [[T2]],[[T2]],[[T3]]
+; MIPS32: sltiu [[T2]],[[T2]],1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T4:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; *** icmp a[5] and b[5] ***
+; MIPS32: srl [[R_E2:.*]],a2,0x10
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: sll [[R_E2]],[[R_E2]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: xor [[R_E2]],[[R_E2]],[[T5]]
+; MIPS32: sltiu [[R_E2]],[[R_E2]],1
+; MIPS32: sll [[R_E2]],[[R_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E2]],[[R_E2]],[[T2]]
+; *** icmp a[6] and b[6] ***
+; MIPS32: andi [[T2:.*]],a3,0xffff
+; MIPS32: andi [[T3:.*]],[[B_E3]],0xffff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: xor [[T2]],[[T2]],[[T3]]
+; MIPS32: sltiu [[T2]],[[T2]],1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T5:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; *** icmp a[7] and b[7] ***
+; MIPS32: srl [[R_E3:.*]],a3,0x10
+; MIPS32: srl [[T6:.*]],[[B_E3]],0x10
+; MIPS32: sll [[R_E3]],[[R_E3]],0x10
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: xor [[R_E3]],[[R_E3]],[[T6]]
+; MIPS32: sltiu [[R_E3]],[[R_E3]],1
+; MIPS32: sll [[R_E3]],[[R_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E3]],[[R_E3]],[[T2]]
+; *** move result to $2:$3:$4:$5 ***
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <8 x i1> @test_icmp_v8i16_ne(<8 x i16> %a, <8 x i16> %b) {
@@ -191,6 +722,109 @@
; CHECK-LABEL: test_icmp_v8i16_ne
; CHECK: pcmpeqw
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v8i16_ne
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; *** icmp a[0] and b[0] ***
+; MIPS32: andi [[T2:.*]],a0,0xffff
+; MIPS32: andi [[T3:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: xor [[T2]],[[T2]],[[T3]]
+; MIPS32: sltu [[T2]],zero,[[T2]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T4:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; *** icmp a[1] and b[1] ***
+; MIPS32: srl [[R_E0:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[R_E0]],[[R_E0]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: xor [[R_E0]],[[R_E0]],[[T5]]
+; MIPS32: sltu [[R_E0]],zero,[[R_E0]]
+; MIPS32: sll [[R_E0]],[[R_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E0]],[[R_E0]],[[T2]]
+; *** icmp a[2] and b[2] ***
+; MIPS32: andi [[T2:.*]],a1,0xffff
+; MIPS32: andi [[T3:.*]],[[B_E1]],0xffff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: xor [[T2]],[[T2]],[[T3]]
+; MIPS32: sltu [[T2]],zero,[[T2]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T4:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; *** icmp a[3] and b[3] ***
+; MIPS32: srl [[R_E1:.*]],a1,0x10
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: sll [[R_E1]],[[R_E1]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: xor [[R_E1]],[[R_E1]],[[T5]]
+; MIPS32: sltu [[R_E1]],zero,[[R_E1]]
+; MIPS32: sll [[R_E1]],[[R_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E1]],[[R_E1]],[[T2]]
+; *** icmp a[4] and b[4] ***
+; MIPS32: andi [[T2:.*]],a2,0xffff
+; MIPS32: andi [[T3:.*]],[[B_E2]],0xffff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: xor [[T2]],[[T2]],[[T3]]
+; MIPS32: sltu [[T2]],zero,[[T2]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T4:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; *** icmp a[5] and b[5] ***
+; MIPS32: srl [[R_E2:.*]],a2,0x10
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: sll [[R_E2]],[[R_E2]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: xor [[R_E2]],[[R_E2]],[[T5]]
+; MIPS32: sltu [[R_E2]],zero,[[R_E2]]
+; MIPS32: sll [[R_E2]],[[R_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E2]],[[R_E2]],[[T2]]
+; *** icmp a[6] and b[6] ***
+; MIPS32: andi [[T2:.*]],a3,0xffff
+; MIPS32: andi [[T3:.*]],[[B_E3]],0xffff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: xor [[T2]],[[T2]],[[T3]]
+; MIPS32: sltu [[T2]],zero,[[T2]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T5:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; *** icmp a[7] and b[7] ***
+; MIPS32: srl [[R_E3:.*]],a3,0x10
+; MIPS32: srl [[T6:.*]],[[B_E3]],0x10
+; MIPS32: sll [[R_E3]],[[R_E3]],0x10
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: xor [[R_E3]],[[R_E3]],[[T6]]
+; MIPS32: sltu [[R_E3]],zero,[[R_E3]]
+; MIPS32: sll [[R_E3]],[[R_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E3]],[[R_E3]],[[T2]]
+; *** move result to $2:$3:$4:$5 ***
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <8 x i1> @test_icmp_v8i16_sgt(<8 x i16> %a, <8 x i16> %b) {
@@ -199,6 +833,88 @@
ret <8 x i1> %res
; CHECK-LABEL: test_icmp_v8i16_sgt
; CHECK: pcmpgtw
+
+; MIPS32-LABEL: test_icmp_v8i16_sgt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: slt [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: slt [[T5]],[[T5]],[[T4]]
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
+; MIPS32: andi [[T4]],a1,0xffff
+; MIPS32: andi [[T3]],[[B_E1]],0xffff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: slt [[T3]],[[T3]],[[T4]]
+; MIPS32: andi [[T3]],[[T3]],0xffff
+; MIPS32: srl [[T6:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: or [[T3]],[[T3]],[[T6]]
+; MIPS32: srl [[T7:.*]],a1,0x10
+; MIPS32: srl [[T8:.*]],[[B_E1]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: slt [[T8]],[[T8]],[[T7]]
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: srl [[T3]],[[T3]],0x10
+; MIPS32: or [[R_E1:.*]],[[T8]],[[T3]]
+; MIPS32: andi [[T4]],a2,0xffff
+; MIPS32: andi [[T7]],[[B_E2]],0xffff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: slt [[T7]],[[T7]],[[T4]]
+; MIPS32: andi [[T7]],[[T7]],0xffff
+; MIPS32: srl [[T9:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T9]],[[T9]],0x10
+; MIPS32: or [[T7]],[[T7]],[[T9]]
+; MIPS32: srl [[T10:.*]],a2,0x10
+; MIPS32: srl [[T11:.*]],[[B_E2]],0x10
+; MIPS32: sll [[T10]],[[T10]],0x10
+; MIPS32: sll [[T11]],[[T11]],0x10
+; MIPS32: slt [[T11]],[[T11]],[[T10]]
+; MIPS32: sll [[T11]],[[T11]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: srl [[T7]],[[T7]],0x10
+; MIPS32: or [[R_E2:.*]],[[T11]],[[T7]]
+; MIPS32: andi [[T4]],a3,0xffff
+; MIPS32: andi [[T7]],[[B_E3]],0xffff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: slt [[T7]],[[T7]],[[T4]]
+; MIPS32: andi [[T7]],[[T7]],0xffff
+; MIPS32: srl [[T12:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T12]],[[T12]],0x10
+; MIPS32: or [[T7]],[[T7]],[[T12]]
+; MIPS32: srl [[T13:.*]],a3,0x10
+; MIPS32: srl [[T14:.*]],[[B_E3]],0x10
+; MIPS32: sll [[T13]],[[T13]],0x10
+; MIPS32: sll [[T14]],[[T14]],0x10
+; MIPS32: slt [[T14]],[[T14]],[[T13]]
+; MIPS32: sll [[T14]],[[T14]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: srl [[T7]],[[T7]],0x10
+; MIPS32: or [[R_E3:.*]],[[T14]],[[T7]]
}
define internal <8 x i1> @test_icmp_v8i16_sle(<8 x i16> %a, <8 x i16> %b) {
@@ -208,6 +924,96 @@
; CHECK-LABEL: test_icmp_v8i16_sle
; CHECK: pcmpgtw
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v8i16_sle
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: slt [[T2]],[[T2]],[[T1]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: slt [[T5]],[[T5]],[[T4]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
+; MIPS32: andi [[T4]],a1,0xffff
+; MIPS32: andi [[T3]],[[B_E1]],0xffff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: slt [[T3]],[[T3]],[[T4]]
+; MIPS32: xori [[T3]],[[T3]],0x1
+; MIPS32: andi [[T3]],[[T3]],0xffff
+; MIPS32: srl [[T6:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: or [[T3]],[[T3]],[[T6]]
+; MIPS32: srl [[T7:.*]],a1,0x10
+; MIPS32: srl [[T8:.*]],[[B_E1]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: slt [[T8]],[[T8]],[[T7]]
+; MIPS32: xori [[T8]],[[T8]],0x1
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: srl [[T3]],[[T3]],0x10
+; MIPS32: or [[R_E1:.*]],[[T8]],[[T3]]
+; MIPS32: andi [[T4]],a2,0xffff
+; MIPS32: andi [[T7]],[[B_E2]],0xffff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: slt [[T7]],[[T7]],[[T4]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: andi [[T7]],[[T7]],0xffff
+; MIPS32: srl [[T9:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T9]],[[T9]],0x10
+; MIPS32: or [[T7]],[[T7]],[[T9]]
+; MIPS32: srl [[T10:.*]],a2,0x10
+; MIPS32: srl [[T11:.*]],[[B_E2]],0x10
+; MIPS32: sll [[T10]],[[T10]],0x10
+; MIPS32: sll [[T11]],[[T11]],0x10
+; MIPS32: slt [[T11]],[[T11]],[[T10]]
+; MIPS32: xori [[T11]],[[T11]],0x1
+; MIPS32: sll [[T11]],[[T11]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: srl [[T7]],[[T7]],0x10
+; MIPS32: or [[R_E2:.*]],[[T11]],[[T7]]
+; MIPS32: andi [[T4]],a3,0xffff
+; MIPS32: andi [[T7]],[[B_E3]],0xffff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: slt [[T7]],[[T7]],[[T4]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: andi [[T7]],[[T7]],0xffff
+; MIPS32: srl [[T12:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T12]],[[T12]],0x10
+; MIPS32: or [[T7]],[[T7]],[[T12]]
+; MIPS32: srl [[T13:.*]],a3,0x10
+; MIPS32: srl [[T14:.*]],[[B_E3]],0x10
+; MIPS32: sll [[T13]],[[T13]],0x10
+; MIPS32: sll [[T14]],[[T14]],0x10
+; MIPS32: slt [[T14]],[[T14]],[[T13]]
+; MIPS32: xori [[T14]],[[T14]],0x1
+; MIPS32: sll [[T14]],[[T14]],0x10
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: srl [[T7]],[[T7]],0x10
+; MIPS32: or [[R_E3:.*]],[[T14]],[[T7]]
}
define internal <8 x i1> @test_icmp_v8i16_slt(<8 x i16> %a, <8 x i16> %b) {
@@ -216,6 +1022,88 @@
ret <8 x i1> %res
; CHECK-LABEL: test_icmp_v8i16_slt
; CHECK: pcmpgtw
+
+; MIPS32-LABEL: test_icmp_v8i16_slt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: slt [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: slt [[T4]],[[T4]],[[T5]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a1,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: slt [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a1,0x10
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: slt [[T4]],[[T4]],[[T5]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a2,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: slt [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a2,0x10
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: slt [[T4]],[[T4]],[[T5]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a3,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: slt [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a3,0x10
+; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: slt [[T4]],[[T4]],[[T5]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
}
define internal <8 x i1> @test_icmp_v8i16_uge(<8 x i16> %a, <8 x i16> %b) {
@@ -226,6 +1114,100 @@
; CHECK: pxor
; CHECK: pcmpgtw
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v8i16_uge
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a1,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a1,0x10
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a2,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a2,0x10
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a3,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a3,0x10
+; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <8 x i1> @test_icmp_v8i16_ugt(<8 x i16> %a, <8 x i16> %b) {
@@ -235,6 +1217,89 @@
; CHECK-LABEL: test_icmp_v8i16_ugt
; CHECK: pxor
; CHECK: pcmpgtw
+
+; MIPS32-LABEL: test_icmp_v8i16_ugt
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T5]],[[T5]],[[T4]]
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
+; MIPS32: andi [[T1:.*]],a1,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a1,0x10
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T5]],[[T5]],[[T4]]
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E1:.*]],[[T5]],[[T2]]
+; MIPS32: andi [[T1:.*]],a2,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a2,0x10
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T5]],[[T5]],[[T4]]
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E2:.*]],[[T5]],[[T2]]
+; MIPS32: andi [[T1:.*]],a3,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a3,0x10
+; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T5]],[[T5]],[[T4]]
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E3:.*]],[[T5]],[[T2]]
+
}
define internal <8 x i1> @test_icmp_v8i16_ule(<8 x i16> %a, <8 x i16> %b) {
@@ -245,6 +1310,96 @@
; CHECK: pxor
; CHECK: pcmpgtw
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v8i16_ule
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T5]],[[T5]],[[T4]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]]
+; MIPS32: andi [[T1:.*]],a1,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a1,0x10
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T5]],[[T5]],[[T4]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E1:.*]],[[T5]],[[T2]]
+; MIPS32: andi [[T1:.*]],a2,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a2,0x10
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T5]],[[T5]],[[T4]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E2:.*]],[[T5]],[[T2]]
+; MIPS32: andi [[T1:.*]],a3,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T2]],[[T2]],[[T3]]
+; MIPS32: srl [[T4:.*]],a3,0x10
+; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T5]],[[T5]],[[T4]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: or [[R_E3:.*]],[[T5]],[[T2]]
}
define internal <8 x i1> @test_icmp_v8i16_ult(<8 x i16> %a, <8 x i16> %b) {
@@ -254,6 +1409,92 @@
; CHECK-LABEL: test_icmp_v8i16_ult
; CHECK: pxor
; CHECK: pcmpgtw
+
+; MIPS32-LABEL: test_icmp_v8i16_ult
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a1,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a1,0x10
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a2,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a2,0x10
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a3,0xffff
+; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a3,0x10
+; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <8 x i1> @test_icmp_v8i1_eq(<8 x i1> %a, <8 x i1> %b) {
@@ -262,6 +1503,116 @@
ret <8 x i1> %res
; CHECK-LABEL: test_icmp_v8i1_eq
; CHECK: pcmpeqw
+
+; MIPS32-LABEL: test_icmp_v8i1_eq
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T1]],[[T1]],[[T2]]
+; MIPS32: sltiu [[T1]],[[T1]],1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a1,0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T1]],[[T1]],[[T2]]
+; MIPS32: sltiu [[T1]],[[T1]],1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a2,0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T1]],[[T1]],[[T2]]
+; MIPS32: sltiu [[T1]],[[T1]],1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a3,0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T1]],[[T1]],[[T2]]
+; MIPS32: sltiu [[T1]],[[T1]],1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <8 x i1> @test_icmp_v8i1_ne(<8 x i1> %a, <8 x i1> %b) {
@@ -271,6 +1622,116 @@
; CHECK-LABEL: test_icmp_v8i1_ne
; CHECK: pcmpeqw
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v8i1_ne
+; MIPS32: lw [[B_E0:.*]],
+; MIPS32: lw [[B_E1:.*]],
+; MIPS32: lw [[B_E2:.*]],
+; MIPS32: lw [[B_E3:.*]],
+; MIPS32: move [[T1_E0:.*]],zero
+; MIPS32: move [[T1_E1:.*]],zero
+; MIPS32: move [[T1_E2:.*]],zero
+; MIPS32: move [[T1_E3:.*]],zero
+; MIPS32: andi [[T1:.*]],a0,0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T1]],[[T1]],[[T2]]
+; MIPS32: sltu [[T1]],zero,[[T1]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a0,0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5:.*]],[[B_E0]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a1,0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T1]],[[T1]],[[T2]]
+; MIPS32: sltu [[T1]],zero,[[T1]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5:.*]],[[B_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a2,0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T1]],[[T1]],[[T2]]
+; MIPS32: sltu [[T1]],zero,[[T1]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5:.*]],[[B_E2]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T1:.*]],a3,0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T1]],[[T1]],[[T2]]
+; MIPS32: sltu [[T1]],zero,[[T1]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T3]]
+; MIPS32: srl [[T4:.*]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5:.*]],[[B_E3]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]]
+; MIPS32: move v0,[[R_E0]]
+; MIPS32: move v1,[[R_E1]]
+; MIPS32: move a0,[[R_E2]]
+; MIPS32: move a1,[[R_E3]]
}
define internal <8 x i1> @test_icmp_v8i1_sgt(<8 x i1> %a, <8 x i1> %b) {
@@ -279,6 +1740,104 @@
ret <8 x i1> %res
; CHECK-LABEL: test_icmp_v8i1_sgt
; CHECK: pcmpgtw
+
+; MIPS32-LABEL: test_icmp_v8i1_sgt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
}
define internal <8 x i1> @test_icmp_v8i1_sle(<8 x i1> %a, <8 x i1> %b) {
@@ -288,6 +1847,112 @@
; CHECK-LABEL: test_icmp_v8i1_sle
; CHECK: pcmpgtw
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v8i1_sle
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
}
define internal <8 x i1> @test_icmp_v8i1_slt(<8 x i1> %a, <8 x i1> %b) {
@@ -296,6 +1961,104 @@
ret <8 x i1> %res
; CHECK-LABEL: test_icmp_v8i1_slt
; CHECK: pcmpgtw
+
+; MIPS32-LABEL: test_icmp_v8i1_slt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T3]],[[T3]],[[T4]]
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T3]],[[T3]],[[T4]]
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T3]],[[T3]],[[T4]]
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T3]],[[T3]],[[T4]]
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
}
define internal <8 x i1> @test_icmp_v8i1_uge(<8 x i1> %a, <8 x i1> %b) {
@@ -306,6 +2069,112 @@
; CHECK: pxor
; CHECK: pcmpgtw
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v8i1_uge
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: xori [[T3]],[[T3]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: xori [[T3]],[[T3]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: xori [[T3]],[[T3]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: xori [[T3]],[[T3]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
}
define internal <8 x i1> @test_icmp_v8i1_ugt(<8 x i1> %a, <8 x i1> %b) {
@@ -315,6 +2184,104 @@
; CHECK-LABEL: test_icmp_v8i1_ugt
; CHECK: pxor
; CHECK: pcmpgtw
+
+; MIPS32-LABEL: test_icmp_v8i1_ugt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
}
define internal <8 x i1> @test_icmp_v8i1_ule(<8 x i1> %a, <8 x i1> %b) {
@@ -325,6 +2292,112 @@
; CHECK: pxor
; CHECK: pcmpgtw
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v8i1_ule
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T0:.*]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T3:.*]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]]
}
define internal <8 x i1> @test_icmp_v8i1_ult(<8 x i1> %a, <8 x i1> %b) {
@@ -334,6 +2407,104 @@
; CHECK-LABEL: test_icmp_v8i1_ult
; CHECK: pxor
; CHECK: pcmpgtw
+
+; MIPS32-LABEL: test_icmp_v8i1_ult
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T0:.*]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xffff
+; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: sll [[T3]],[[T3]],0x10
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]]
}
define internal <16 x i1> @test_icmp_v16i8_eq(<16 x i8> %a, <16 x i8> %b) {
@@ -342,6 +2513,208 @@
ret <16 x i1> %res
; CHECK-LABEL: test_icmp_v16i8_eq
; CHECK: pcmpeqb
+
+; MIPS32-LABEL: test_icmp_v16i8_eq
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: xor [[T0]],[[T0]],[[T1]]
+; MIPS32: sltiu [[T0]],[[T0]],1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: xor [[T2]],[[T2]],[[T1]]
+; MIPS32: sltiu [[T2]],[[T2]],1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: xor [[T0]],[[T0]],[[T1]]
+; MIPS32: sltiu [[T0]],[[T0]],1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: xor [[T3]],[[T3]],[[T4]]
+; MIPS32: sltiu [[T3]],[[T3]],1
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T2]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: xor [[T2]],[[T2]],[[T5]]
+; MIPS32: sltiu [[T2]],[[T2]],1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: xor [[T6]],[[T6]],[[T7]]
+; MIPS32: sltiu [[T6]],[[T6]],1
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T7]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: xor [[T7]],[[T7]],[[T2]]
+; MIPS32: sltiu [[T7]],[[T7]],1
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T2]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: xor [[T9]],[[T9]],[[T10]]
+; MIPS32: sltiu [[T9]],[[T9]],1
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T7]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: xor [[T7]],[[T7]],[[T10]]
+; MIPS32: sltiu [[T7]],[[T7]],1
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T10]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: xor [[T12]],[[T12]],[[T13]]
+; MIPS32: sltiu [[T12]],[[T12]],1
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) {
@@ -351,6 +2724,208 @@
; CHECK-LABEL: test_icmp_v16i8_ne
; CHECK: pcmpeqb
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v16i8_ne
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: xor [[T0]],[[T0]],[[T1]]
+; MIPS32: sltu [[T0]],zero,[[T0]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: xor [[T2]],[[T2]],[[T1]]
+; MIPS32: sltu [[T2]],zero,[[T2]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: xor [[T0]],[[T0]],[[T1]]
+; MIPS32: sltu [[T0]],zero,[[T0]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: xor [[T3]],[[T3]],[[T4]]
+; MIPS32: sltu [[T3]],zero,[[T3]]
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T2]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: xor [[T2]],[[T2]],[[T5]]
+; MIPS32: sltu [[T2]],zero,[[T2]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: xor [[T6]],[[T6]],[[T7]]
+; MIPS32: sltu [[T6]],zero,[[T6]]
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T7]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: xor [[T7]],[[T7]],[[T2]]
+; MIPS32: sltu [[T7]],zero,[[T7]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T2]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: xor [[T9]],[[T9]],[[T10]]
+; MIPS32: sltu [[T9]],zero,[[T9]]
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T7]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: xor [[T7]],[[T7]],[[T10]]
+; MIPS32: sltu [[T7]],zero,[[T7]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: xor [[T4]],[[T4]],[[T10]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: xor [[T12]],[[T12]],[[T13]]
+; MIPS32: sltu [[T12]],zero,[[T12]]
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) {
@@ -359,6 +2934,192 @@
ret <16 x i1> %res
; CHECK-LABEL: test_icmp_v16i8_sgt
; CHECK: pcmpgtb
+
+; MIPS32-LABEL: test_icmp_v16i8_sgt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T0]],[[BV_E0]],0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: slt [[T0]],[[T0]],[[T2]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T1]],[[T1]],[[T2]]
+; MIPS32: or [[T0]],[[T0]],[[T1]]
+; MIPS32: srl [[T2]],a0,0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: slt [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T0]],[[T0]],[[T2]]
+; MIPS32: or [[T1]],[[T1]],[[T0]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x8
+; MIPS32: srl [[T1]],[[T1]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T3]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T3]],a1,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: slt [[T5]],[[T5]],[[T3]]
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T5]],[[T5]],[[T2]]
+; MIPS32: srl [[T3]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T2]],[[BV_E1]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T5]],[[T5]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: slt [[T7]],[[T7]],[[T6]]
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: srl [[T2]],[[T2]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
+; MIPS32: andi [[T3]],a2,0xff
+; MIPS32: andi [[T6]],[[BV_E2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T8]]
+; MIPS32: srl [[T3]],a2,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T6]]
+; MIPS32: srl [[T3]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T6]],[[BV_E2]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T2]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: slt [[T10]],[[T10]],[[T9]]
+; MIPS32: srl [[T10]],[[T10]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
+; MIPS32: andi [[T3]],a3,0xff
+; MIPS32: andi [[T6]],[[BV_E3]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T11]]
+; MIPS32: srl [[T3]],a3,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T9]],[[BV_E3]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: slt [[T9]],[[T9]],[[T3]]
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T9]],[[T9]],[[T6]]
+; MIPS32: srl [[T3]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T6]],[[BV_E3]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T9]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: slt [[T13]],[[T13]],[[T12]]
+; MIPS32: srl [[T13]],[[T13]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
}
define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) {
@@ -368,6 +3129,208 @@
; CHECK-LABEL: test_icmp_v16i8_sle
; CHECK: pcmpgtb
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v16i8_sle
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T0]],[[BV_E0]],0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: slt [[T0]],[[T0]],[[T2]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T1]],[[T1]],[[T2]]
+; MIPS32: or [[T0]],[[T0]],[[T1]]
+; MIPS32: srl [[T2]],a0,0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: slt [[T1]],[[T1]],[[T2]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T0]],[[T0]],[[T2]]
+; MIPS32: or [[T1]],[[T1]],[[T0]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x8
+; MIPS32: srl [[T1]],[[T1]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T3]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T3]],a1,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: slt [[T5]],[[T5]],[[T3]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T5]],[[T5]],[[T2]]
+; MIPS32: srl [[T3]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T2]],[[BV_E1]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T5]],[[T5]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: slt [[T7]],[[T7]],[[T6]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: srl [[T2]],[[T2]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
+; MIPS32: andi [[T3]],a2,0xff
+; MIPS32: andi [[T6]],[[BV_E2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T8]]
+; MIPS32: srl [[T3]],a2,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T6]]
+; MIPS32: srl [[T3]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T6]],[[BV_E2]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T2]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: slt [[T10]],[[T10]],[[T9]]
+; MIPS32: xori [[T10]],[[T10]],0x1
+; MIPS32: srl [[T10]],[[T10]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
+; MIPS32: andi [[T3]],a3,0xff
+; MIPS32: andi [[T6]],[[BV_E3]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T11]]
+; MIPS32: srl [[T3]],a3,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T9]],[[BV_E3]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: slt [[T9]],[[T9]],[[T3]]
+; MIPS32: xori [[T9]],[[T9]],0x1
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T9]],[[T9]],[[T6]]
+; MIPS32: srl [[T3]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T6]],[[BV_E3]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T9]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: slt [[T13]],[[T13]],[[T12]]
+; MIPS32: xori [[T13]],[[T13]],0x1
+; MIPS32: srl [[T13]],[[T13]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
}
define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) {
@@ -376,6 +3339,192 @@
ret <16 x i1> %res
; CHECK-LABEL: test_icmp_v16i8_slt
; CHECK: pcmpgtb
+
+; MIPS32-LABEL: test_icmp_v16i8_slt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: slt [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: slt [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: slt [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: slt [[T3]],[[T3]],[[T4]]
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T4]],[[T4]],[[T2]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: slt [[T2]],[[T2]],[[T5]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: slt [[T4]],[[T4]],[[T5]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: slt [[T6]],[[T6]],[[T7]]
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: slt [[T4]],[[T4]],[[T7]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T7]],[[T7]],[[T2]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: slt [[T4]],[[T4]],[[T2]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: slt [[T9]],[[T9]],[[T10]]
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: slt [[T4]],[[T4]],[[T7]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: slt [[T7]],[[T7]],[[T10]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: slt [[T4]],[[T4]],[[T10]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: slt [[T12]],[[T12]],[[T13]]
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) {
@@ -386,6 +3535,208 @@
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v16i8_uge
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: xori [[T3]],[[T3]],0x1
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T2]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T5]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T7]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T7]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T7]],[[T7]],[[T2]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T2]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: sltu [[T9]],[[T9]],[[T10]]
+; MIPS32: xori [[T9]],[[T9]],0x1
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T7]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: sltu [[T7]],[[T7]],[[T10]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T10]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: sltu [[T12]],[[T12]],[[T13]]
+; MIPS32: xori [[T12]],[[T12]],0x1
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) {
@@ -395,6 +3746,192 @@
; CHECK-LABEL: test_icmp_v16i8_ugt
; CHECK: pxor
; CHECK: pcmpgtb
+
+; MIPS32-LABEL: test_icmp_v16i8_ugt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T0]],[[BV_E0]],0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sltu [[T0]],[[T0]],[[T2]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T1]],[[T1]],[[T2]]
+; MIPS32: or [[T0]],[[T0]],[[T1]]
+; MIPS32: srl [[T2]],a0,0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T0]],[[T0]],[[T2]]
+; MIPS32: or [[T1]],[[T1]],[[T0]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x8
+; MIPS32: srl [[T1]],[[T1]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T3]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T3]],a1,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: sltu [[T5]],[[T5]],[[T3]]
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T5]],[[T5]],[[T2]]
+; MIPS32: srl [[T3]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T2]],[[BV_E1]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T5]],[[T5]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sltu [[T7]],[[T7]],[[T6]]
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: srl [[T2]],[[T2]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
+; MIPS32: andi [[T3]],a2,0xff
+; MIPS32: andi [[T6]],[[BV_E2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T8]]
+; MIPS32: srl [[T3]],a2,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T6]]
+; MIPS32: srl [[T3]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T6]],[[BV_E2]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T2]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: sltu [[T10]],[[T10]],[[T9]]
+; MIPS32: srl [[T10]],[[T10]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
+; MIPS32: andi [[T3]],a3,0xff
+; MIPS32: andi [[T6]],[[BV_E3]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T11]]
+; MIPS32: srl [[T3]],a3,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T9]],[[BV_E3]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sltu [[T9]],[[T9]],[[T3]]
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T9]],[[T9]],[[T6]]
+; MIPS32: srl [[T3]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T6]],[[BV_E3]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T9]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: sltu [[T13]],[[T13]],[[T12]]
+; MIPS32: srl [[T13]],[[T13]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
}
define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) {
@@ -405,6 +3942,208 @@
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v16i8_ule
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T0]],[[BV_E0]],0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sltu [[T0]],[[T0]],[[T2]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T1]],[[T1]],[[T2]]
+; MIPS32: or [[T0]],[[T0]],[[T1]]
+; MIPS32: srl [[T2]],a0,0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T0]],[[T0]],[[T2]]
+; MIPS32: or [[T1]],[[T1]],[[T0]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x8
+; MIPS32: srl [[T1]],[[T1]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T3]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T3]],a1,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: sltu [[T5]],[[T5]],[[T3]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T5]],[[T5]],[[T2]]
+; MIPS32: srl [[T3]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T2]],[[BV_E1]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T5]],[[T5]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sltu [[T7]],[[T7]],[[T6]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: srl [[T2]],[[T2]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
+; MIPS32: andi [[T3]],a2,0xff
+; MIPS32: andi [[T6]],[[BV_E2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T8]]
+; MIPS32: srl [[T3]],a2,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T6]]
+; MIPS32: srl [[T3]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T6]],[[BV_E2]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T2]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: sltu [[T10]],[[T10]],[[T9]]
+; MIPS32: xori [[T10]],[[T10]],0x1
+; MIPS32: srl [[T10]],[[T10]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
+; MIPS32: andi [[T3]],a3,0xff
+; MIPS32: andi [[T6]],[[BV_E3]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T11]]
+; MIPS32: srl [[T3]],a3,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T9]],[[BV_E3]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sltu [[T9]],[[T9]],[[T3]]
+; MIPS32: xori [[T9]],[[T9]],0x1
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T9]],[[T9]],[[T6]]
+; MIPS32: srl [[T3]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: srl [[T6]],[[BV_E3]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T9]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: sltu [[T13]],[[T13]],[[T12]]
+; MIPS32: xori [[T13]],[[T13]],0x1
+; MIPS32: srl [[T13]],[[T13]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
}
define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) {
@@ -414,6 +4153,192 @@
; CHECK-LABEL: test_icmp_v16i8_ult
; CHECK: pxor
; CHECK: pcmpgtb
+
+; MIPS32-LABEL: test_icmp_v16i8_ult
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[TV_E0]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x18
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: sll [[T3]],[[T3]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T2]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[TV_E1]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: sltu [[T2]],[[T2]],[[T5]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T5]],[[T5]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sltu [[T6]],[[T6]],[[T7]]
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T7]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[TV_E2]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T7]],[[T7]],[[T2]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T2]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: sll [[T9]],[[T9]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: sltu [[T9]],[[T9]],[[T10]]
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T7]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[TV_E3]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: sltu [[T7]],[[T7]],[[T10]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x18
+; MIPS32: sll [[T10]],[[T10]],0x18
+; MIPS32: sltu [[T4]],[[T4]],[[T10]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: sll [[T12]],[[T12]],0x18
+; MIPS32: sll [[T13]],[[T13]],0x18
+; MIPS32: sltu [[T12]],[[T12]],[[T13]]
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) {
@@ -422,6 +4347,240 @@
ret <16 x i1> %res
; CHECK-LABEL: test_icmp_v16i1_eq
; CHECK: pcmpeqb
+
+; MIPS32-LABEL: test_icmp_v16i1_eq
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: xor [[T0]],[[T0]],[[T1]]
+; MIPS32: sltiu [[T0]],[[T0]],1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: xor [[T2]],[[T2]],[[T1]]
+; MIPS32: sltiu [[T2]],[[T2]],1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: xor [[T0]],[[T0]],[[T1]]
+; MIPS32: sltiu [[T0]],[[T0]],1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: xor [[T3]],[[T3]],[[T4]]
+; MIPS32: sltiu [[T3]],[[T3]],1
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T2]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T2]],[[T2]],[[T5]]
+; MIPS32: sltiu [[T2]],[[T2]],1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: xor [[T6]],[[T6]],[[T7]]
+; MIPS32: sltiu [[T6]],[[T6]],1
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T7]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T7]],[[T7]],[[T2]]
+; MIPS32: sltiu [[T7]],[[T7]],1
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T2]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: xor [[T9]],[[T9]],[[T10]]
+; MIPS32: sltiu [[T9]],[[T9]],1
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T7]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: xor [[T7]],[[T7]],[[T10]]
+; MIPS32: sltiu [[T7]],[[T7]],1
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T10]]
+; MIPS32: sltiu [[T4]],[[T4]],1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: xor [[T12]],[[T12]],[[T13]]
+; MIPS32: sltiu [[T12]],[[T12]],1
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) {
@@ -431,6 +4590,240 @@
; CHECK-LABEL: test_icmp_v16i1_ne
; CHECK: pcmpeqb
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v16i1_ne
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: xor [[T0]],[[T0]],[[T1]]
+; MIPS32: sltu [[T0]],zero,[[T0]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: xor [[T2]],[[T2]],[[T1]]
+; MIPS32: sltu [[T2]],zero,[[T2]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: xor [[T0]],[[T0]],[[T1]]
+; MIPS32: sltu [[T0]],zero,[[T0]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: xor [[T3]],[[T3]],[[T4]]
+; MIPS32: sltu [[T3]],zero,[[T3]]
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T2]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T2]],[[T2]],[[T5]]
+; MIPS32: sltu [[T2]],zero,[[T2]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T5]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: xor [[T6]],[[T6]],[[T7]]
+; MIPS32: sltu [[T6]],zero,[[T6]]
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T7]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T7]],[[T7]],[[T2]]
+; MIPS32: sltu [[T7]],zero,[[T7]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T2]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: xor [[T9]],[[T9]],[[T10]]
+; MIPS32: sltu [[T9]],zero,[[T9]]
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T7]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: xor [[T7]],[[T7]],[[T10]]
+; MIPS32: sltu [[T7]],zero,[[T7]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: xor [[T4]],[[T4]],[[T10]]
+; MIPS32: sltu [[T4]],zero,[[T4]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: xor [[T12]],[[T12]],[[T13]]
+; MIPS32: sltu [[T12]],zero,[[T12]]
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) {
@@ -439,6 +4832,224 @@
ret <16 x i1> %res
; CHECK-LABEL: test_icmp_v16i1_sgt
; CHECK: pcmpgtb
+
+; MIPS32-LABEL: test_icmp_v16i1_sgt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T0]],[[BV_E0]],0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: slt [[T0]],[[T0]],[[T2]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T1]],[[T1]],[[T2]]
+; MIPS32: or [[T0]],[[T0]],[[T1]]
+; MIPS32: srl [[T2]],a0,0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T0]],[[T0]],[[T2]]
+; MIPS32: or [[T1]],[[T1]],[[T0]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x8
+; MIPS32: srl [[T1]],[[T1]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T3]],a1,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T3]],a1,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: slt [[T5]],[[T5]],[[T3]]
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T5]],[[T5]],[[T2]]
+; MIPS32: srl [[T3]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T2]],[[BV_E1]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T5]],[[T5]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: slt [[T7]],[[T7]],[[T6]]
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: srl [[T2]],[[T2]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
+; MIPS32: andi [[T3]],a2,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T6]],[[BV_E2]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T8]]
+; MIPS32: srl [[T3]],a2,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T6]]
+; MIPS32: srl [[T3]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T6]],[[BV_E2]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T2]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: slt [[T10]],[[T10]],[[T9]]
+; MIPS32: srl [[T10]],[[T10]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
+; MIPS32: andi [[T3]],a3,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T6]],[[BV_E3]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T11]]
+; MIPS32: srl [[T3]],a3,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T9]],[[BV_E3]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: slt [[T9]],[[T9]],[[T3]]
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T9]],[[T9]],[[T6]]
+; MIPS32: srl [[T3]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T6]],[[BV_E3]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T9]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: slt [[T13]],[[T13]],[[T12]]
+; MIPS32: srl [[T13]],[[T13]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
}
define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) {
@@ -448,6 +5059,240 @@
; CHECK-LABEL: test_icmp_v16i1_sle
; CHECK: pcmpgtb
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v16i1_sle
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T0]],[[BV_E0]],0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: slt [[T0]],[[T0]],[[T2]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T1]],[[T1]],[[T2]]
+; MIPS32: or [[T0]],[[T0]],[[T1]]
+; MIPS32: srl [[T2]],a0,0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T1]],[[T1]],[[T2]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T0]],[[T0]],[[T2]]
+; MIPS32: or [[T1]],[[T1]],[[T0]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x8
+; MIPS32: srl [[T1]],[[T1]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T3]],a1,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T3]],a1,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: slt [[T5]],[[T5]],[[T3]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T5]],[[T5]],[[T2]]
+; MIPS32: srl [[T3]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T2]],[[BV_E1]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T5]],[[T5]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: slt [[T7]],[[T7]],[[T6]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: srl [[T2]],[[T2]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
+; MIPS32: andi [[T3]],a2,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T6]],[[BV_E2]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T8]]
+; MIPS32: srl [[T3]],a2,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T6]]
+; MIPS32: srl [[T3]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T6]],[[BV_E2]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T2]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: slt [[T10]],[[T10]],[[T9]]
+; MIPS32: xori [[T10]],[[T10]],0x1
+; MIPS32: srl [[T10]],[[T10]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
+; MIPS32: andi [[T3]],a3,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T6]],[[BV_E3]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T11]]
+; MIPS32: srl [[T3]],a3,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T9]],[[BV_E3]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: slt [[T9]],[[T9]],[[T3]]
+; MIPS32: xori [[T9]],[[T9]],0x1
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T9]],[[T9]],[[T6]]
+; MIPS32: srl [[T3]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T6]],[[BV_E3]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T9]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: slt [[T13]],[[T13]],[[T12]]
+; MIPS32: xori [[T13]],[[T13]],0x1
+; MIPS32: srl [[T13]],[[T13]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
}
define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) {
@@ -456,6 +5301,224 @@
ret <16 x i1> %res
; CHECK-LABEL: test_icmp_v16i1_slt
; CHECK: pcmpgtb
+
+; MIPS32-LABEL: test_icmp_v16i1_slt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: slt [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: slt [[T3]],[[T3]],[[T4]]
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T2]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: slt [[T2]],[[T2]],[[T5]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T5]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: slt [[T6]],[[T6]],[[T7]]
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T7]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T7]],[[T7]],[[T2]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T2]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: slt [[T9]],[[T9]],[[T10]]
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T7]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: slt [[T7]],[[T7]],[[T10]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: slt [[T4]],[[T4]],[[T10]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: slt [[T12]],[[T12]],[[T13]]
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) {
@@ -466,6 +5529,240 @@
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v16i1_uge
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: xori [[T3]],[[T3]],0x1
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T2]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T5]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T7]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T7]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T7]],[[T7]],[[T2]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T2]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: sltu [[T9]],[[T9]],[[T10]]
+; MIPS32: xori [[T9]],[[T9]],0x1
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T7]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: sltu [[T7]],[[T7]],[[T10]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T10]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: sltu [[T12]],[[T12]],[[T13]]
+; MIPS32: xori [[T12]],[[T12]],0x1
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) {
@@ -475,6 +5772,224 @@
; CHECK-LABEL: test_icmp_v16i1_ugt
; CHECK: pxor
; CHECK: pcmpgtb
+
+; MIPS32-LABEL: test_icmp_v16i1_ugt
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T0]],[[BV_E0]],0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T2]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T1]],[[T1]],[[T2]]
+; MIPS32: or [[T0]],[[T0]],[[T1]]
+; MIPS32: srl [[T2]],a0,0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T0]],[[T0]],[[T2]]
+; MIPS32: or [[T1]],[[T1]],[[T0]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x8
+; MIPS32: srl [[T1]],[[T1]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T3]],a1,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T3]],a1,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: sltu [[T5]],[[T5]],[[T3]]
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T5]],[[T5]],[[T2]]
+; MIPS32: srl [[T3]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T2]],[[BV_E1]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T5]],[[T5]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sltu [[T7]],[[T7]],[[T6]]
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: srl [[T2]],[[T2]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
+; MIPS32: andi [[T3]],a2,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T6]],[[BV_E2]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T8]]
+; MIPS32: srl [[T3]],a2,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T6]]
+; MIPS32: srl [[T3]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T6]],[[BV_E2]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T2]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: sltu [[T10]],[[T10]],[[T9]]
+; MIPS32: srl [[T10]],[[T10]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
+; MIPS32: andi [[T3]],a3,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T6]],[[BV_E3]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T11]]
+; MIPS32: srl [[T3]],a3,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T9]],[[BV_E3]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sltu [[T9]],[[T9]],[[T3]]
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T9]],[[T9]],[[T6]]
+; MIPS32: srl [[T3]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T6]],[[BV_E3]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T9]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: sltu [[T13]],[[T13]],[[T12]]
+; MIPS32: srl [[T13]],[[T13]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
}
define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) {
@@ -485,6 +6000,240 @@
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: pxor
+
+; MIPS32-LABEL: test_icmp_v16i1_ule
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T0]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T1]],[[T1]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T0]],[[BV_E0]],0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T2]]
+; MIPS32: xori [[T0]],[[T0]],0x1
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T1]],[[T1]],[[T2]]
+; MIPS32: or [[T0]],[[T0]],[[T1]]
+; MIPS32: srl [[T2]],a0,0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T1]],[[T1]],[[T2]]
+; MIPS32: xori [[T1]],[[T1]],0x1
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: sll [[T1]],[[T1]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T0]],[[T0]],[[T2]]
+; MIPS32: or [[T1]],[[T1]],[[T0]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T3]]
+; MIPS32: xori [[T4]],[[T4]],0x1
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T1]],[[T1]],0x8
+; MIPS32: srl [[T1]],[[T1]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]]
+; MIPS32: andi [[T3]],a1,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T3]],a1,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: sltu [[T5]],[[T5]],[[T3]]
+; MIPS32: xori [[T5]],[[T5]],0x1
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T5]],[[T5]],[[T2]]
+; MIPS32: srl [[T3]],a1,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T2]],[[BV_E1]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T5]],[[T5]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T5]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sltu [[T7]],[[T7]],[[T6]]
+; MIPS32: xori [[T7]],[[T7]],0x1
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: srl [[T2]],[[T2]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]]
+; MIPS32: andi [[T3]],a2,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T6]],[[BV_E2]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T8]]
+; MIPS32: srl [[T3]],a2,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T3]]
+; MIPS32: xori [[T2]],[[T2]],0x1
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T2]],[[T2]],[[T6]]
+; MIPS32: srl [[T3]],a2,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T6]],[[BV_E2]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T2]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: sltu [[T10]],[[T10]],[[T9]]
+; MIPS32: xori [[T10]],[[T10]],0x1
+; MIPS32: srl [[T10]],[[T10]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]]
+; MIPS32: andi [[T3]],a3,0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T6]],[[BV_E3]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T6]],[[T6]],[[T11]]
+; MIPS32: srl [[T3]],a3,0x8
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T9]],[[BV_E3]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sltu [[T9]],[[T9]],[[T3]]
+; MIPS32: xori [[T9]],[[T9]],0x1
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T3]],0xffff
+; MIPS32: ori [[T3]],[[T3]],0xff
+; MIPS32: and [[T6]],[[T6]],[[T3]]
+; MIPS32: or [[T9]],[[T9]],[[T6]]
+; MIPS32: srl [[T3]],a3,0x10
+; MIPS32: andi [[T3]],[[T3]],0xff
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T6]],[[BV_E3]],0x10
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T3]]
+; MIPS32: xori [[T6]],[[T6]],0x1
+; MIPS32: andi [[T6]],[[T6]],0xff
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: lui [[T3]],0xff00
+; MIPS32: ori [[T3]],[[T3]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T3]]
+; MIPS32: or [[T6]],[[T6]],[[T9]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: sltu [[T13]],[[T13]],[[T12]]
+; MIPS32: xori [[T13]],[[T13]],0x1
+; MIPS32: srl [[T13]],[[T13]],0x18
+; MIPS32: sll [[T6]],[[T6]],0x8
+; MIPS32: srl [[T6]],[[T6]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]]
}
define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) {
@@ -494,4 +6243,222 @@
; CHECK-LABEL: test_icmp_v16i1_ult
; CHECK: pxor
; CHECK: pcmpgtb
+
+; MIPS32-LABEL: test_icmp_v16i1_ult
+; MIPS32: lw [[BV_E0:.*]],
+; MIPS32: lw [[BV_E1:.*]],
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; MIPS32: move [[TV_E0:.*]],zero
+; MIPS32: move [[TV_E1:.*]],zero
+; MIPS32: move [[TV_E2:.*]],zero
+; MIPS32: move [[TV_E3:.*]],zero
+; MIPS32: andi [[T0:.*]],a0,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T2]],a0,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T1]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T1]],0xffff
+; MIPS32: ori [[T1]],[[T1]],0xff
+; MIPS32: and [[T0]],[[T0]],[[T1]]
+; MIPS32: or [[T2]],[[T2]],[[T0]]
+; MIPS32: srl [[T0]],a0,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[BV_E0]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: sll [[T0]],[[T0]],0x1f
+; MIPS32: sll [[T1]],[[T1]],0x1f
+; MIPS32: sltu [[T0]],[[T0]],[[T1]]
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: sll [[T0]],[[T0]],0x10
+; MIPS32: lui [[T1]],0xff00
+; MIPS32: ori [[T1]],[[T1]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T1]]
+; MIPS32: or [[T0]],[[T0]],[[T2]]
+; MIPS32: srl [[T3:.*]],a0,0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: sll [[T3]],[[T3]],0x1f
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sltu [[T3]],[[T3]],[[T4]]
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: sll [[T0]],[[T0]],0x8
+; MIPS32: srl [[T0]],[[T0]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]]
+; MIPS32: andi [[T4]],a1,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T2]],[[BV_E1]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T2]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8
+; MIPS32: sll [[T5]],[[T5]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T5]]
+; MIPS32: srl [[T2]],a1,0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x8
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: sltu [[T2]],[[T2]],[[T5]]
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: sll [[T2]],[[T2]],0x8
+; MIPS32: lui [[T5]],0xffff
+; MIPS32: ori [[T5]],[[T5]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T5]]
+; MIPS32: or [[T2]],[[T2]],[[T4]]
+; MIPS32: srl [[T4]],a1,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T5]],[[BV_E1]],0x10
+; MIPS32: andi [[T5]],[[T5]],0xff
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T5]],[[T5]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T5]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T5]],0xff00
+; MIPS32: ori [[T5]],[[T5]],0xffff
+; MIPS32: and [[T2]],[[T2]],[[T5]]
+; MIPS32: or [[T4]],[[T4]],[[T2]]
+; MIPS32: srl [[T6:.*]],a1,0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T6]],[[T6]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sltu [[T6]],[[T6]],[[T7]]
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]]
+; MIPS32: andi [[T4]],a2,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E2]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T7]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T8]]
+; MIPS32: srl [[T7]],a2,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x8
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T7]],[[T7]],[[T2]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T2]],0xffff
+; MIPS32: ori [[T2]],[[T2]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T2]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a2,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T2]],[[BV_E2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0xff
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T2]],[[T2]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T2]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T2]],0xff00
+; MIPS32: ori [[T2]],[[T2]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T2]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T9:.*]],a2,0x18
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T9]],[[T9]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: sltu [[T9]],[[T9]],[[T10]]
+; MIPS32: srl [[T9]],[[T9]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]]
+; MIPS32: andi [[T4]],a3,0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: andi [[T7]],[[BV_E3]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T7]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T4]],[[T4]],[[T11]]
+; MIPS32: srl [[T7]],a3,0x8
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x8
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T7]],[[T7]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: sltu [[T7]],[[T7]],[[T10]]
+; MIPS32: andi [[T7]],[[T7]],0xff
+; MIPS32: sll [[T7]],[[T7]],0x8
+; MIPS32: lui [[T10]],0xffff
+; MIPS32: ori [[T10]],[[T10]],0xff
+; MIPS32: and [[T4]],[[T4]],[[T10]]
+; MIPS32: or [[T7]],[[T7]],[[T4]]
+; MIPS32: srl [[T4]],a3,0x10
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: srl [[T10]],[[BV_E3]],0x10
+; MIPS32: andi [[T10]],[[T10]],0xff
+; MIPS32: andi [[T10]],[[T10]],0x1
+; MIPS32: sll [[T4]],[[T4]],0x1f
+; MIPS32: sll [[T10]],[[T10]],0x1f
+; MIPS32: sltu [[T4]],[[T4]],[[T10]]
+; MIPS32: andi [[T4]],[[T4]],0xff
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: lui [[T10]],0xff00
+; MIPS32: ori [[T10]],[[T10]],0xffff
+; MIPS32: and [[T7]],[[T7]],[[T10]]
+; MIPS32: or [[T4]],[[T4]],[[T7]]
+; MIPS32: srl [[T12:.*]],a3,0x18
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: sll [[T12]],[[T12]],0x1f
+; MIPS32: sll [[T13]],[[T13]],0x1f
+; MIPS32: sltu [[T12]],[[T12]],[[T13]]
+; MIPS32: srl [[T12]],[[T12]],0x18
+; MIPS32: sll [[T4]],[[T4]],0x8
+; MIPS32: srl [[T4]],[[T4]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]]
}
diff --git a/tests_lit/llvm2ice_tests/vector-ops.ll b/tests_lit/llvm2ice_tests/vector-ops.ll
index 7114187..679b565 100644
--- a/tests_lit/llvm2ice_tests/vector-ops.ll
+++ b/tests_lit/llvm2ice_tests/vector-ops.ll
@@ -9,6 +9,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
; RUN: | FileCheck --check-prefix=SSE41 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
+; RUN: -i %s --args -O2 --skip-unimplemented \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; insertelement operations
define internal <4 x float> @insertelement_v4f32_0(<4 x float> %vec,
@@ -21,6 +27,24 @@
; SSE41-LABEL: insertelement_v4f32_0
; SSE41: insertps {{.*}},{{.*}},0x0
+
+; *** a0 - implicit return <4 x float>
+; *** a1 - unused due to alignment of %vec
+; *** a2:a3:sp[16]:s[20] - %vec
+; *** sp[24] - %elt
+; MIPS32-LABEL: insertelement_v4f32_0
+; *** Load element 2 and 3 of %vec
+; MIPS32: lw [[BV_E2:.*]],
+; MIPS32: lw [[BV_E3:.*]],
+; *** Load %elt
+; MIPS32: lwc1 [[ELT:.*]],
+; *** Insert %elt at %vec[0]
+; MIPS32: mfc1 [[RV_E0:.*]],[[ELT]]
+; MIPS32: move [[RET_PTR:.*]],a0
+; MIPS32: sw [[RV_E0]],0([[RET_PTR]])
+; MIPS32: sw a3,4([[RET_PTR]])
+; MIPS32: sw [[BV_E2]],8([[RET_PTR]])
+; MIPS32: sw [[BV_E3]],12([[RET_PTR]])
}
define internal <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
@@ -33,6 +57,15 @@
; SSE41-LABEL: insertelement_v4i32_0
; SSE41: pinsrd {{.*}},{{.*}},0x0
+
+; *** a0:a1:a2:a3 - %vec
+; *** sp[16] - %elt
+; MIPS32-LABEL: insertelement_v4i32_0
+; *** Load %elt
+; MIPS32: lw v0,16(sp)
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
@@ -47,6 +80,17 @@
; SSE41-LABEL: insertelement_v4f32_1
; SSE41: insertps {{.*}},{{.*}},0x10
+
+; MIPS32-LABEL: insertelement_v4f32_1
+; MIPS32: lw [[VEC_E2:.*]],16(sp)
+; MIPS32: lw [[VEC_E3:.*]],20(sp)
+; MIPS32: lwc1 [[ELT:.*]],24(sp)
+; MIPS32: mfc1 [[R_E1:.*]],[[ELT]]
+; MIPS32: move [[PTR:.*]],a0
+; MIPS32: sw a2,0([[PTR]])
+; MIPS32: sw [[R_E1]],4([[PTR]])
+; MIPS32: sw [[VEC_E2]],8([[PTR]])
+; MIPS32: sw [[VEC_E3]],12([[PTR]])
}
define internal <4 x i32> @insertelement_v4i32_1(<4 x i32> %vec, i32 %elt) {
@@ -59,6 +103,13 @@
; SSE41-LABEL: insertelement_v4i32_1
; SSE41: pinsrd {{.*}},{{.*}},0x1
+
+; MIPS32-LABEL: insertelement_v4i32_1
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: move v1,[[ELT]]
+; MIPS32: move v0,a0
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
define internal <8 x i16> @insertelement_v8i16(<8 x i16> %vec, i32 %elt.arg) {
@@ -71,6 +122,16 @@
; SSE41-LABEL: insertelement_v8i16
; SSE41: pinsrw
+
+; MIPS32-LABEL: insertelement_v8i16
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: sll [[ELT]],[[ELT]],0x10
+; MIPS32: sll a0,a0,0x10
+; MIPS32: srl a0,a0,0x10
+; MIPS32: or v0,[[ELT]],a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
define internal <16 x i8> @insertelement_v16i8(<16 x i8> %vec, i32 %elt.arg) {
@@ -85,6 +146,18 @@
; SSE41-LABEL: insertelement_v16i8
; SSE41: pinsrb
+
+; MIPS32-LABEL: insertelement_v16i8
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: andi [[ELT]],[[ELT]],0xff
+; MIPS32: sll [[ELT]],[[ELT]],0x8
+; MIPS32: lui [[T:.*]],0xffff
+; MIPS32: ori [[T]],[[T]],0xff
+; MIPS32: and a0,a0,[[T]]
+; MIPS32: or v0,v0,a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
define internal <4 x i1> @insertelement_v4i1_0(<4 x i1> %vec, i32 %elt.arg) {
@@ -97,6 +170,12 @@
; SSE41-LABEL: insertelement_v4i1_0
; SSE41: pinsrd {{.*}},{{.*}},0x0
+
+; MIPS32-LABEL: insertelement_v4i1_0
+; MIPS32: lw v0,16(sp)
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
define internal <4 x i1> @insertelement_v4i1_1(<4 x i1> %vec, i32 %elt.arg) {
@@ -110,6 +189,13 @@
; SSE41-LABEL: insertelement_v4i1_1
; SSE41: pinsrd {{.*}},{{.*}},0x1
+
+; MIPS32-LABEL: insertelement_v4i1_1
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: move v1,[[ELT]]
+; MIPS32: move v0,a0
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
define internal <8 x i1> @insertelement_v8i1(<8 x i1> %vec, i32 %elt.arg) {
@@ -122,6 +208,16 @@
; SSE41-LABEL: insertelement_v8i1
; SSE41: pinsrw
+
+; MIPS32-LABEL: insertelement_v8i1
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: sll [[ELT]],[[ELT]],0x10
+; MIPS32: sll a0,a0,0x10
+; MIPS32: srl a0,a0,0x10
+; MIPS32: or v0,[[ELT]],a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
define internal <16 x i1> @insertelement_v16i1(<16 x i1> %vec, i32 %elt.arg) {
@@ -136,6 +232,18 @@
; SSE41-LABEL: insertelement_v16i1
; SSE41: pinsrb
+
+; MIPS32-LABEL: insertelement_v16i1
+; MIPS32: lw [[ELT:.*]],16(sp)
+; MIPS32: andi [[ELT]],[[ELT]],0xff
+; MIPS32: sll [[ELT]],[[ELT]],0x8
+; MIPS32: lui [[T:.*]],0xffff
+; MIPS32: ori [[T]],[[T]],0xff
+; MIPS32: and a0,a0,[[T]]
+; MIPS32: or v0,[[ELT]],a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
; extractelement operations
@@ -149,6 +257,9 @@
; SSE41-LABEL: extractelement_v4f32
; SSE41: pshufd
+
+; MIPS32-LABEL: extractelement_v4f32
+; MIPS32: mtc1 a1,$f0
}
define internal i32 @extractelement_v4i32(<4 x i32> %vec) {
@@ -161,6 +272,9 @@
; SSE41-LABEL: extractelement_v4i32
; SSE41: pextrd
+
+; MIPS32-LABEL: extractelement_v4i32
+; MIPS32L move v0,a1
}
define internal i32 @extractelement_v8i16(<8 x i16> %vec) {
@@ -173,6 +287,11 @@
; SSE41-LABEL: extractelement_v8i16
; SSE41: pextrw
+
+; MIPS32-LABEL: extractelement_v8i16
+; MIPS32: srl a0,a0,0x10
+; MIPS32: andi a0,a0,0xffff
+; MIPS32: move v0,a0
}
define internal i32 @extractelement_v16i8(<16 x i8> %vec) {
@@ -187,6 +306,12 @@
; SSE41-LABEL: extractelement_v16i8
; SSE41: pextrb
+
+; MIPS32-LABEL: extractelement_v16i8
+; MIPS32: srl a0,a0,0x8
+; MIPS32: andi a0,a0,0xff
+; MIPS32: andi a0,a0,0xff
+; MIPS32: move v0,a0
}
define internal i32 @extractelement_v4i1(<4 x i1> %vec) {
@@ -199,6 +324,11 @@
; SSE41-LABEL: extractelement_v4i1
; SSE41: pextrd
+
+; MIPS32-LABEL: extractelement_v4i1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: move v0,a1
}
define internal i32 @extractelement_v8i1(<8 x i1> %vec) {
@@ -211,6 +341,12 @@
; SSE41-LABEL: extractelement_v8i1
; SSE41: pextrw
+
+; MIPS32-LABEL: extractelement_v8i1
+; MIPS32: srl a0,a0,0x10
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: move v0,a0
}
define internal i32 @extractelement_v16i1(<16 x i1> %vec) {
@@ -225,4 +361,11 @@
; SSE41-LABEL: extractelement_v16i1
; SSE41: pextrb
+
+; MIPS32-LABEL: extractelement_v16i1
+; MIPS32: srl a0,a0,0x8
+; MIPS32: andi a0,a0,0xff
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: move v0,a0
}
diff --git a/tests_lit/llvm2ice_tests/vector-select.ll b/tests_lit/llvm2ice_tests/vector-select.ll
index 6e08d3f..0affb13 100644
--- a/tests_lit/llvm2ice_tests/vector-select.ll
+++ b/tests_lit/llvm2ice_tests/vector-select.ll
@@ -9,6 +9,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
; RUN: | FileCheck --check-prefix=SSE41 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
+; RUN: -i %s --args -O2 --skip-unimplemented \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
define internal <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1,
<16 x i8> %arg2) {
entry:
@@ -21,6 +27,204 @@
; SSE41-LABEL: test_select_v16i8
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
+
+; MIPS32-LABEL: test_select_v16i8
+; MIPS32: lw [[T0:.*]],36(sp)
+; MIPS32: lw [[T1:.*]],40(sp)
+; MIPS32: lw [[T2:.*]],44(sp)
+; MIPS32: lw [[T3:.*]],48(sp)
+; MIPS32: lw [[T4:.*]],52(sp)
+; MIPS32: lw [[T5:.*]],56(sp)
+; MIPS32: lw [[T6:.*]],60(sp)
+; MIPS32: lw [[T7:.*]],64(sp)
+; MIPS32: move [[T8:.*]],zero
+; MIPS32: move [[T9:.*]],zero
+; MIPS32: move [[T10:.*]],zero
+; MIPS32: move [[T11:.*]],zero
+; MIPS32: andi [[T12:.*]],a0,0xff
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: andi [[T13:.*]],[[T0]],0xff
+; MIPS32: andi [[T14:.*]],[[T4]],0xff
+; MIPS32: movn [[T14]],[[T13]],[[T12]]
+; MIPS32: andi [[T14]],[[T14]],0xff
+; MIPS32: srl [[T8]],[[T8]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T14]],[[T14]],[[T8]]
+; MIPS32: srl [[T8]],a0,0x8
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: andi [[T8]],[[T8]],0x1
+; MIPS32: srl [[T12]],[[T0]],0x8
+; MIPS32: andi [[T12]],[[T12]],0xff
+; MIPS32: srl [[T13]],[[T4]],0x8
+; MIPS32: andi [[T13]],[[T13]],0xff
+; MIPS32: movn [[T13]],[[T12]],[[T8]]
+; MIPS32: andi [[T13]],[[T13]],0xff
+; MIPS32: sll [[T13]],[[T13]],0x8
+; MIPS32: lui [[T8]],0xffff
+; MIPS32: ori [[T8]],[[T8]],0xff
+; MIPS32: and [[T14]],[[T14]],[[T8]]
+; MIPS32: or [[T13]],[[T13]],[[T14]]
+; MIPS32: srl [[T8]],a0,0x10
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: andi [[T8]],[[T8]],0x1
+; MIPS32: srl [[T12]],[[T0]],0x10
+; MIPS32: andi [[T12]],[[T12]],0xff
+; MIPS32: srl [[T14]],[[T4]],0x10
+; MIPS32: andi [[T14]],[[T14]],0xff
+; MIPS32: movn [[T14]],[[T12]],[[T8]]
+; MIPS32: andi [[T14]],[[T14]],0xff
+; MIPS32: sll [[T14]],[[T14]],0x10
+; MIPS32: lui [[T8]],0xff00
+; MIPS32: ori [[T8]],[[T8]],0xffff
+; MIPS32: and [[T13]],[[T13]],[[T8]]
+; MIPS32: or [[T14]],[[T14]],[[T13]]
+; MIPS32: srl [[T15:.*]],a0,0x18
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: srl [[T0]],[[T0]],0x18
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: movn [[T4]],[[T0]],[[T15]]
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T14]],[[T14]],0x8
+; MIPS32: srl [[T14]],[[T14]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
+; MIPS32: andi [[T0]],a1,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T15]],[[T1]],0xff
+; MIPS32: andi [[T8]],[[T5]],0xff
+; MIPS32: movn [[T8]],[[T15]],[[T0]]
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: srl [[T9]],[[T9]],0x8
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: or [[T8]],[[T8]],[[T9]]
+; MIPS32: srl [[T0]],a1,0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T15]],[[T1]],0x8
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: srl [[T9]],[[T5]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: movn [[T9]],[[T15]],[[T0]]
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T0]],0xffff
+; MIPS32: ori [[T0]],[[T0]],0xff
+; MIPS32: and [[T8]],[[T8]],[[T0]]
+; MIPS32: or [[T9]],[[T9]],[[T8]]
+; MIPS32: srl [[T0]],a1,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T15]],[[T1]],0x10
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: srl [[T8]],[[T5]],0x10
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: movn [[T8]],[[T15]],[[T0]]
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: lui [[T0]],0xff00
+; MIPS32: ori [[T0]],[[T0]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T0]]
+; MIPS32: or [[T8]],[[T8]],[[T9]]
+; MIPS32: srl [[T16:.*]],a1,0x18
+; MIPS32: andi [[T16]],[[T16]],0x1
+; MIPS32: srl [[T1]],[[T1]],0x18
+; MIPS32: srl [[T5]],[[T5]],0x18
+; MIPS32: movn [[T5]],[[T1]],[[T16]]
+; MIPS32: srl [[T5]],[[T5]],0x18
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: srl [[T8]],[[T8]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
+; MIPS32: andi [[T0]],a2,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1]],[[T2]],0xff
+; MIPS32: andi [[T15]],[[T6]],0xff
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: srl [[T10]],[[T10]],0x8
+; MIPS32: sll [[T10]],[[T10]],0x8
+; MIPS32: or [[T15]],[[T15]],[[T10]]
+; MIPS32: srl [[T0]],a2,0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[T2]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T16]],[[T6]],0x8
+; MIPS32: andi [[T16]],[[T16]],0xff
+; MIPS32: movn [[T16]],[[T1]],[[T0]]
+; MIPS32: andi [[T16]],[[T16]],0xff
+; MIPS32: sll [[T16]],[[T16]],0x8
+; MIPS32: lui [[T0]],0xffff
+; MIPS32: ori [[T0]],[[T0]],0xff
+; MIPS32: and [[T15]],[[T15]],[[T0]]
+; MIPS32: or [[T16]],[[T16]],[[T15]]
+; MIPS32: srl [[T0]],a2,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[T2]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T15]],[[T6]],0x10
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: sll [[T15]],[[T15]],0x10
+; MIPS32: lui [[T0]],0xff00
+; MIPS32: ori [[T0]],[[T0]],0xffff
+; MIPS32: and [[T16]],[[T16]],[[T0]]
+; MIPS32: or [[T15]],[[T15]],[[T16]]
+; MIPS32: srl [[T17:.*]],a2,0x18
+; MIPS32: andi [[T17]],[[T17]],0x1
+; MIPS32: srl [[T2]],[[T2]],0x18
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: movn [[T6]],[[T2]],[[T17]]
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T15]],[[T15]],0x8
+; MIPS32: srl [[T15]],[[T15]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
+; MIPS32: andi [[T0]],a3,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1]],[[T3]],0xff
+; MIPS32: andi [[T15]],[[T7]],0xff
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: srl [[T11]],[[T11]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T15]],[[T15]],[[T11]]
+; MIPS32: srl [[T0]],a3,0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[T3]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T16]],[[T7]],0x8
+; MIPS32: andi [[T16]],[[T16]],0xff
+; MIPS32: movn [[T16]],[[T1]],[[T0]]
+; MIPS32: andi [[T16]],[[T16]],0xff
+; MIPS32: sll [[T16]],[[T16]],0x8
+; MIPS32: lui [[T0]],0xffff
+; MIPS32: ori [[T0]],[[T0]],0xff
+; MIPS32: and [[T15]],[[T15]],[[T0]]
+; MIPS32: or [[T16]],[[T16]],[[T15]]
+; MIPS32: srl [[T0]],a3,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[T3]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: srl [[T15]],[[T7]],0x10
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: sll [[T15]],[[T15]],0x10
+; MIPS32: lui [[T0]],0xff00
+; MIPS32: ori [[T0]],[[T0]],0xffff
+; MIPS32: and [[T16]],[[T16]],[[T0]]
+; MIPS32: or [[T15]],[[T15]],[[T16]]
+; MIPS32: srl [[T18:.*]],a3,0x18
+; MIPS32: andi [[T18]],[[T18]],0x1
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: movn [[T7]],[[T3]],[[T18]]
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T15]],[[T15]],0x8
+; MIPS32: srl [[T15]],[[T15]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
}
define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1,
@@ -35,6 +239,236 @@
; SSE41-LABEL: test_select_v16i1
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
+
+; MIPS32-LABEL: test_select_v16i1
+; MIPS32: lw [[T0:.*]],36(sp)
+; MIPS32: lw [[T1:.*]],40(sp)
+; MIPS32: lw [[T2:.*]],44(sp)
+; MIPS32: lw [[T3:.*]],48(sp)
+; MIPS32: lw [[T4:.*]],52(sp)
+; MIPS32: lw [[T5:.*]],56(sp)
+; MIPS32: lw [[T6:.*]],60(sp)
+; MIPS32: lw [[T7:.*]],64(sp)
+; MIPS32: move [[T8:.*]],zero
+; MIPS32: move [[T9:.*]],zero
+; MIPS32: move [[T10:.*]],zero
+; MIPS32: move [[T11:.*]],zero
+; MIPS32: andi [[T12:.*]],a0,0xff
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: andi [[T13:.*]],[[T0]],0xff
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: andi [[T14:.*]],[[T4]],0xff
+; MIPS32: andi [[T14]],[[T14]],0x1
+; MIPS32: movn [[T14]],[[T13]],[[T12]]
+; MIPS32: andi [[T14]],[[T14]],0xff
+; MIPS32: srl [[T8]],[[T8]],0x8
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: or [[T14]],[[T14]],[[T8]]
+; MIPS32: srl [[T8]],a0,0x8
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: andi [[T8]],[[T8]],0x1
+; MIPS32: srl [[T12]],[[T0]],0x8
+; MIPS32: andi [[T12]],[[T12]],0xff
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T13]],[[T4]],0x8
+; MIPS32: andi [[T13]],[[T13]],0xff
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: movn [[T13]],[[T12]],[[T8]]
+; MIPS32: andi [[T13]],[[T13]],0xff
+; MIPS32: sll [[T13]],[[T13]],0x8
+; MIPS32: lui [[T8]],0xffff
+; MIPS32: ori [[T8]],[[T8]],0xff
+; MIPS32: and [[T14]],[[T14]],[[T8]]
+; MIPS32: or [[T13]],[[T13]],[[T14]]
+; MIPS32: srl [[T8]],a0,0x10
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: andi [[T8]],[[T8]],0x1
+; MIPS32: srl [[T12]],[[T0]],0x10
+; MIPS32: andi [[T12]],[[T12]],0xff
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: srl [[T14]],[[T4]],0x10
+; MIPS32: andi [[T14]],[[T14]],0xff
+; MIPS32: andi [[T14]],[[T14]],0x1
+; MIPS32: movn [[T14]],[[T12]],[[T8]]
+; MIPS32: andi [[T14]],[[T14]],0xff
+; MIPS32: sll [[T14]],[[T14]],0x10
+; MIPS32: lui [[T8]],0xff00
+; MIPS32: ori [[T8]],[[T8]],0xffff
+; MIPS32: and [[T13]],[[T13]],[[T8]]
+; MIPS32: or [[T14]],[[T14]],[[T13]]
+; MIPS32: srl [[T15:.*]],a0,0x18
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: srl [[T0]],[[T0]],0x18
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: movn [[T4]],[[T0]],[[T15]]
+; MIPS32: srl [[T4]],[[T4]],0x18
+; MIPS32: sll [[T14]],[[T14]],0x8
+; MIPS32: srl [[T14]],[[T14]],0x8
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
+; MIPS32: andi [[T0]],a1,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T15]],[[T1]],0xff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: andi [[T8]],[[T5]],0xff
+; MIPS32: andi [[T8]],[[T8]],0x1
+; MIPS32: movn [[T8]],[[T15]],[[T0]]
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: srl [[T9]],[[T9]],0x8
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: or [[T8]],[[T8]],[[T9]]
+; MIPS32: srl [[T0]],a1,0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T15]],[[T1]],0x8
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: srl [[T9]],[[T5]],0x8
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: andi [[T9]],[[T9]],0x1
+; MIPS32: movn [[T9]],[[T15]],[[T0]]
+; MIPS32: andi [[T9]],[[T9]],0xff
+; MIPS32: sll [[T9]],[[T9]],0x8
+; MIPS32: lui [[T0]],0xffff
+; MIPS32: ori [[T0]],[[T0]],0xff
+; MIPS32: and [[T8]],[[T8]],[[T0]]
+; MIPS32: or [[T9]],[[T9]],[[T8]]
+; MIPS32: srl [[T0]],a1,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T15]],[[T1]],0x10
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: srl [[T8]],[[T5]],0x10
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: andi [[T8]],[[T8]],0x1
+; MIPS32: movn [[T8]],[[T15]],[[T0]]
+; MIPS32: andi [[T8]],[[T8]],0xff
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: lui [[T0]],0xff00
+; MIPS32: ori [[T0]],[[T0]],0xffff
+; MIPS32: and [[T9]],[[T9]],[[T0]]
+; MIPS32: or [[T8]],[[T8]],[[T9]]
+; MIPS32: srl [[T16:.*]],a1,0x18
+; MIPS32: andi [[T16]],[[T16]],0x1
+; MIPS32: srl [[T1]],[[T1]],0x18
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: srl [[T5]],[[T5]],0x18
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: movn [[T5]],[[T1]],[[T16]]
+; MIPS32: srl [[T5]],[[T5]],0x18
+; MIPS32: sll [[T8]],[[T8]],0x8
+; MIPS32: srl [[T8]],[[T8]],0x8
+; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
+; MIPS32: andi [[T0]],a2,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1]],[[T2]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T15]],[[T6]],0xff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: srl [[T10]],[[T10]],0x8
+; MIPS32: sll [[T10]],[[T10]],0x8
+; MIPS32: or [[T15]],[[T15]],[[T10]]
+; MIPS32: srl [[T0]],a2,0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[T2]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: srl [[T16]],[[T6]],0x8
+; MIPS32: andi [[T16]],[[T16]],0xff
+; MIPS32: andi [[T16]],[[T16]],0x1
+; MIPS32: movn [[T16]],[[T1]],[[T0]]
+; MIPS32: andi [[T16]],[[T16]],0xff
+; MIPS32: sll [[T16]],[[T16]],0x8
+; MIPS32: lui [[T0]],0xffff
+; MIPS32: ori [[T0]],[[T0]],0xff
+; MIPS32: and [[T15]],[[T15]],[[T0]]
+; MIPS32: or [[T16]],[[T16]],[[T15]]
+; MIPS32: srl [[T0]],a2,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[T2]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: srl [[T15]],[[T6]],0x10
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: sll [[T15]],[[T15]],0x10
+; MIPS32: lui [[T0]],0xff00
+; MIPS32: ori [[T0]],[[T0]],0xffff
+; MIPS32: and [[T16]],[[T16]],[[T0]]
+; MIPS32: or [[T15]],[[T15]],[[T16]]
+; MIPS32: srl [[T17:.*]],a2,0x18
+; MIPS32: andi [[T17]],[[T17]],0x1
+; MIPS32: srl [[T2]],[[T2]],0x18
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: movn [[T6]],[[T2]],[[T17]]
+; MIPS32: srl [[T6]],[[T6]],0x18
+; MIPS32: sll [[T15]],[[T15]],0x8
+; MIPS32: srl [[T15]],[[T15]],0x8
+; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
+; MIPS32: andi [[T0]],a3,0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1]],[[T3]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T15]],[[T7]],0xff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: srl [[T11]],[[T11]],0x8
+; MIPS32: sll [[T11]],[[T11]],0x8
+; MIPS32: or [[T15]],[[T15]],[[T11]]
+; MIPS32: srl [[T0]],a3,0x8
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[T3]],0x8
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: srl [[T16]],[[T7]],0x8
+; MIPS32: andi [[T16]],[[T16]],0xff
+; MIPS32: andi [[T16]],[[T16]],0x1
+; MIPS32: movn [[T16]],[[T1]],[[T0]]
+; MIPS32: andi [[T16]],[[T16]],0xff
+; MIPS32: sll [[T16]],[[T16]],0x8
+; MIPS32: lui [[T0]],0xffff
+; MIPS32: ori [[T0]],[[T0]],0xff
+; MIPS32: and [[T15]],[[T15]],[[T0]]
+; MIPS32: or [[T16]],[[T16]],[[T15]]
+; MIPS32: srl [[T0]],a3,0x10
+; MIPS32: andi [[T0]],[[T0]],0xff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T1]],[[T3]],0x10
+; MIPS32: andi [[T1]],[[T1]],0xff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: srl [[T15]],[[T7]],0x10
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xff
+; MIPS32: sll [[T15]],[[T15]],0x10
+; MIPS32: lui [[T0]],0xff00
+; MIPS32: ori [[T0]],[[T0]],0xffff
+; MIPS32: and [[T16]],[[T16]],[[T0]]
+; MIPS32: or [[T15]],[[T15]],[[T16]]
+; MIPS32: srl [[T18:.*]],a3,0x18
+; MIPS32: andi [[T18]],[[T18]],0x1
+; MIPS32: srl [[T3]],[[T3]],0x18
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: movn [[T7]],[[T3]],[[T18]]
+; MIPS32: srl [[T7]],[[T7]],0x18
+; MIPS32: sll [[T15]],[[T15]],0x8
+; MIPS32: srl [[T15]],[[T15]],0x8
+; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
}
define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1,
@@ -49,6 +483,92 @@
; SSE41-LABEL: test_select_v8i16
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
+
+; MIPS32-LABEL: test_select_v8i16
+; MIPS32: lw [[T0:.*]],36(sp)
+; MIPS32: lw [[T1:.*]],40(sp)
+; MIPS32: lw [[T2:.*]],44(sp)
+; MIPS32: lw [[T3:.*]],48(sp)
+; MIPS32: lw [[T4:.*]],52(sp)
+; MIPS32: lw [[T5:.*]],56(sp)
+; MIPS32: lw [[T6:.*]],60(sp)
+; MIPS32: lw [[T7:.*]],64(sp)
+; MIPS32: move [[T8:.*]],zero
+; MIPS32: move [[T9:.*]],zero
+; MIPS32: move [[T10:.*]],zero
+; MIPS32: move [[T11:.*]],zero
+; MIPS32: andi [[T12:.*]],a0,0xffff
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: andi [[T13:.*]],[[T0]],0xffff
+; MIPS32: andi [[T14:.*]],[[T4]],0xffff
+; MIPS32: movn [[T14]],[[T13]],[[T12]]
+; MIPS32: andi [[T14]],[[T14]],0xffff
+; MIPS32: srl [[T8]],[[T8]],0x10
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: or [[T14]],[[T14]],[[T8]]
+; MIPS32: srl [[T15:.*]],a0,0x10
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: srl [[T4]],[[T4]],0x10
+; MIPS32: movn [[T4]],[[T0]],[[T15]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T14]],[[T14]],0x10
+; MIPS32: srl [[T14]],[[T14]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
+; MIPS32: andi [[T0]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T15]],[[T1]],0xffff
+; MIPS32: andi [[T8]],[[T5]],0xffff
+; MIPS32: movn [[T8]],[[T15]],[[T0]]
+; MIPS32: andi [[T8]],[[T8]],0xffff
+; MIPS32: srl [[T9]],[[T9]],0x10
+; MIPS32: sll [[T9]],[[T9]],0x10
+; MIPS32: or [[T8]],[[T8]],[[T9]]
+; MIPS32: srl [[T16:.*]],a1,0x10
+; MIPS32: andi [[T16]],[[T16]],0x1
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: srl [[T5]],[[T5]],0x10
+; MIPS32: movn [[T5]],[[T1]],[[T16]]
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: srl [[T8]],[[T8]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
+; MIPS32: andi [[T0]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1]],[[T2]],0xffff
+; MIPS32: andi [[T15]],[[T6]],0xffff
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xffff
+; MIPS32: srl [[T10]],[[T10]],0x10
+; MIPS32: sll [[T10]],[[T10]],0x10
+; MIPS32: or [[T15]],[[T15]],[[T10]]
+; MIPS32: srl [[T17:.*]],a2,0x10
+; MIPS32: andi [[T17]],[[T17]],0x1
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: srl [[T6]],[[T6]],0x10
+; MIPS32: movn [[T6]],[[T2]],[[T17]]
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: sll [[T15]],[[T15]],0x10
+; MIPS32: srl [[T15]],[[T15]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
+; MIPS32: andi [[T0]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1]],[[T3]],0xffff
+; MIPS32: andi [[T15]],[[T7]],0xffff
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xffff
+; MIPS32: srl [[T11]],[[T11]],0x10
+; MIPS32: sll [[T11]],[[T11]],0x10
+; MIPS32: or [[T15]],[[T15]],[[T11]]
+; MIPS32: srl [[T18:.*]],a3,0x10
+; MIPS32: andi [[T18]],[[T18]],0x1
+; MIPS32: srl [[T3]],[[T3]],0x10
+; MIPS32: srl [[T7]],[[T7]],0x10
+; MIPS32: movn [[T7]],[[T3]],[[T18]]
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: sll [[T15]],[[T15]],0x10
+; MIPS32: srl [[T15]],[[T15]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
}
define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1,
@@ -63,6 +583,108 @@
; SSE41-LABEL: test_select_v8i1
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
+
+; MIPS32-LABEL: test_select_v8i1
+; MIPS32: lw [[T0:.*]],36(sp)
+; MIPS32: lw [[T1:.*]],40(sp)
+; MIPS32: lw [[T2:.*]],44(sp)
+; MIPS32: lw [[T3:.*]],48(sp)
+; MIPS32: lw [[T4:.*]],52(sp)
+; MIPS32: lw [[T5:.*]],56(sp)
+; MIPS32: lw [[T6:.*]],60(sp)
+; MIPS32: lw [[T7:.*]],64(sp)
+; MIPS32: move [[T8:.*]],zero
+; MIPS32: move [[T9:.*]],zero
+; MIPS32: move [[T10:.*]],zero
+; MIPS32: move [[T11:.*]],zero
+; MIPS32: andi [[T12:.*]],a0,0xffff
+; MIPS32: andi [[T12]],[[T12]],0x1
+; MIPS32: andi [[T13:.*]],[[T0]],0xffff
+; MIPS32: andi [[T13]],[[T13]],0x1
+; MIPS32: andi [[T14:.*]],[[T4]],0xffff
+; MIPS32: andi [[T14]],[[T14]],0x1
+; MIPS32: movn [[T14]],[[T13]],[[T12]]
+; MIPS32: andi [[T14]],[[T14]],0xffff
+; MIPS32: srl [[T8]],[[T8]],0x10
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: or [[T14]],[[T14]],[[T8]]
+; MIPS32: srl [[T15:.*]],a0,0x10
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: srl [[T0]],[[T0]],0x10
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: srl [[T4]],[[T4]],0x10
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: movn [[T4]],[[T0]],[[T15]]
+; MIPS32: sll [[T4]],[[T4]],0x10
+; MIPS32: sll [[T14]],[[T14]],0x10
+; MIPS32: srl [[T14]],[[T14]],0x10
+; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
+; MIPS32: andi [[T0]],a1,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T15]],[[T1]],0xffff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: andi [[T8]],[[T5]],0xffff
+; MIPS32: andi [[T8]],[[T8]],0x1
+; MIPS32: movn [[T8]],[[T15]],[[T0]]
+; MIPS32: andi [[T8]],[[T8]],0xffff
+; MIPS32: srl [[T9]],[[T9]],0x10
+; MIPS32: sll [[T9]],[[T9]],0x10
+; MIPS32: or [[T8]],[[T8]],[[T9]]
+; MIPS32: srl [[T16:.*]],a1,0x10
+; MIPS32: andi [[T16]],[[T16]],0x1
+; MIPS32: srl [[T1]],[[T1]],0x10
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: srl [[T5]],[[T5]],0x10
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: movn [[T5]],[[T1]],[[T16]]
+; MIPS32: sll [[T5]],[[T5]],0x10
+; MIPS32: sll [[T8]],[[T8]],0x10
+; MIPS32: srl [[T8]],[[T8]],0x10
+; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
+; MIPS32: andi [[T0]],a2,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1]],[[T2]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T15]],[[T6]],0xffff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xffff
+; MIPS32: srl [[T10]],[[T10]],0x10
+; MIPS32: sll [[T10]],[[T10]],0x10
+; MIPS32: or [[T15]],[[T15]],[[T10]]
+; MIPS32: srl [[T17:.*]],a2,0x10
+; MIPS32: andi [[T17]],[[T17]],0x1
+; MIPS32: srl [[T2]],[[T2]],0x10
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: srl [[T6]],[[T6]],0x10
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: movn [[T6]],[[T2]],[[T17]]
+; MIPS32: sll [[T6]],[[T6]],0x10
+; MIPS32: sll [[T15]],[[T15]],0x10
+; MIPS32: srl [[T15]],[[T15]],0x10
+; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
+; MIPS32: andi [[T0]],a3,0xffff
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T1]],[[T3]],0xffff
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T15]],[[T7]],0xffff
+; MIPS32: andi [[T15]],[[T15]],0x1
+; MIPS32: movn [[T15]],[[T1]],[[T0]]
+; MIPS32: andi [[T15]],[[T15]],0xffff
+; MIPS32: srl [[T11]],[[T11]],0x10
+; MIPS32: sll [[T11]],[[T11]],0x10
+; MIPS32: or [[T15]],[[T15]],[[T11]]
+; MIPS32: srl [[T18:.*]],a3,0x10
+; MIPS32: andi [[T18]],[[T18]],0x1
+; MIPS32: srl [[T3]],[[T3]],0x10
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: srl [[T7]],[[T7]],0x10
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: movn [[T7]],[[T3]],[[T18]]
+; MIPS32: sll [[T7]],[[T7]],0x10
+; MIPS32: sll [[T15]],[[T15]],0x10
+; MIPS32: srl [[T15]],[[T15]],0x10
+; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
}
define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1,
@@ -78,6 +700,28 @@
; SSE41-LABEL: test_select_v4i32
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
+
+; MIPS32-LABEL: test_select_v4i32
+; MIPS32: lw [[T0:.*]],16(sp)
+; MIPS32: lw [[T1:.*]],20(sp)
+; MIPS32: lw [[T2:.*]],24(sp)
+; MIPS32: lw [[T3:.*]],28(sp)
+; MIPS32: lw [[T4:.*]],32(sp)
+; MIPS32: lw [[T5:.*]],36(sp)
+; MIPS32: lw [[T6:.*]],40(sp)
+; MIPS32: lw [[T7:.*]],44(sp)
+; MIPS32: andi [[T8:.*]],a0,0x1
+; MIPS32: movn [[T4]],[[T0]],[[T8]]
+; MIPS32: andi [[T9:.*]],a1,0x1
+; MIPS32: movn [[T5]],[[T1]],[[T9]]
+; MIPS32: andi [[T10:.*]],a2,0x1
+; MIPS32: movn [[T6]],[[T2]],[[T10]]
+; MIPS32: andi [[T11:.*]],a3,0x1
+; MIPS32: movn [[T7]],[[T3]],[[T11]]
+; MIPS32: move v0,[[T4]]
+; MIPS32: move v1,[[T5]]
+; MIPS32: move a0,[[T6]]
+; MIPS32: move a1,[[T7]]
}
define internal <4 x float> @test_select_v4f32(
@@ -93,6 +737,44 @@
; SSE41-LABEL: test_select_v4f32
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
+
+; MIPS32-LABEL: test_select_v4f32
+; MIPS32: lw [[T0:.*]],16(sp)
+; MIPS32: lw [[T1:.*]],20(sp)
+; MIPS32: lw [[T2:.*]],24(sp)
+; MIPS32: lw [[T3:.*]],28(sp)
+; MIPS32: lw [[T4:.*]],32(sp)
+; MIPS32: lw [[T5:.*]],36(sp)
+; MIPS32: lw [[T6:.*]],40(sp)
+; MIPS32: lw [[T7:.*]],44(sp)
+; MIPS32: lw [[T8:.*]],48(sp)
+; MIPS32: lw [[T9:.*]],52(sp)
+; MIPS32: andi [[T10:.*]],a2,0x1
+; MIPS32: mtc1 [[T2]],[[F0:.*]]
+; MIPS32: mtc1 [[T6]],[[F1:.*]]
+; MIPS32: movn.s [[T11:.*]],[[F0]],[[T10]]
+; MIPS32: mfc1 v0,[[T11]]
+; MIPS32: andi [[T12:.*]],a3,0x1
+; MIPS32: mtc1 [[T3]],[[F0]]
+; MIPS32: mtc1 [[T7]],[[T11]]
+; MIPS32: movn.s [[T11]],[[F0]],[[T12]]
+; MIPS32: mfc1 v1,[[T11]]
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: mtc1 [[T4]],[[F0]]
+; MIPS32: mtc1 [[T8]],[[T11]]
+; MIPS32: movn.s [[T11]],[[F0]],[[T0]]
+; MIPS32: mfc1 a1,[[T11]]
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: mtc1 [[T5]],[[F0]]
+; MIPS32: mtc1 [[T9]],[[T11]]
+; MIPS32: movn.s [[T11]],[[F0]],[[T1]]
+; MIPS32: mfc1 a2,[[T11]]
+; MIPS32: move [[RET:.*]],a0
+; MIPS32: sw v0,0([[RET]])
+; MIPS32: sw v1,4([[RET]])
+; MIPS32: sw a1,8([[RET]])
+; MIPS32: sw a2,12([[RET]])
+; MIPS32: move v0,a0
}
define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1,
@@ -108,4 +790,34 @@
; SSE41-LABEL: test_select_v4i1
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
+
+; MIPS32-LABEL: test_select_v4i1
+; MIPS32: lw [[T0:.*]],16(sp)
+; MIPS32: lw [[T1:.*]],20(sp)
+; MIPS32: lw [[T2:.*]],24(sp)
+; MIPS32: lw [[T3:.*]],28(sp)
+; MIPS32: lw [[T4:.*]],32(sp)
+; MIPS32: lw [[T5:.*]],36(sp)
+; MIPS32: lw [[T6:.*]],40(sp)
+; MIPS32: lw [[T7:.*]],44(sp)
+; MIPS32: andi [[T8:.*]],a0,0x1
+; MIPS32: andi [[T0]],[[T0]],0x1
+; MIPS32: andi [[T4]],[[T4]],0x1
+; MIPS32: movn [[T4]],[[T0]],[[T8]]
+; MIPS32: andi [[T9:.*]],a1,0x1
+; MIPS32: andi [[T1]],[[T1]],0x1
+; MIPS32: andi [[T5]],[[T5]],0x1
+; MIPS32: movn [[T5]],[[T1]],[[T9]]
+; MIPS32: andi [[T10:.*]],a2,0x1
+; MIPS32: andi [[T2]],[[T2]],0x1
+; MIPS32: andi [[T6]],[[T6]],0x1
+; MIPS32: movn [[T6]],[[T2]],[[T10]]
+; MIPS32: andi [[T11:.*]],a3,0x1
+; MIPS32: andi [[T3]],[[T3]],0x1
+; MIPS32: andi [[T7]],[[T7]],0x1
+; MIPS32: movn [[T7]],[[T3]],[[T11]]
+; MIPS32: move v0,[[T4]]
+; MIPS32: move v1,[[T5]]
+; MIPS32: move a0,[[T6]]
+; MIPS32: move a1,[[T7]]
}