Subzero: Use the linear-scan register allocator for Om1 as well.
This removes the need for Om1's postLower() code which did its own ad-hoc register allocation. And it actually speeds up Om1 translation significantly.
This mode of register allocation only allocates for infinite-weight Variables, while respecting live ranges of pre-colored Variables.
BUG= none
R=jvoung@chromium.org
Review URL: https://codereview.chromium.org/733643005
diff --git a/src/IceTargetLowering.h b/src/IceTargetLowering.h
index a8b0fcc..07d665f 100644
--- a/src/IceTargetLowering.h
+++ b/src/IceTargetLowering.h
@@ -195,7 +195,7 @@
virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
RegSetMask Exclude) const = 0;
virtual const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const = 0;
- void regAlloc();
+ void regAlloc(RegAllocKind Kind);
virtual void emitVariable(const Variable *Var) const = 0;
@@ -236,11 +236,7 @@
virtual void doAddressOptStore() {}
virtual void randomlyInsertNop(float Probability) = 0;
// This gives the target an opportunity to post-process the lowered
- // expansion before returning. The primary intention is to do some
- // Register Manager activity as necessary, specifically to eagerly
- // allocate registers based on affinity and other factors. The
- // simplest lowering does nothing here and leaves it all to a
- // subsequent global register allocation pass.
+ // expansion before returning.
virtual void postLower() {}
Cfg *Func;