Subzero: Make the register allocator more robust with -reg-use and -reg-exclude.
The problem is that if you too aggressively -reg-use or -reg-exclude, you can get failures because of inherently high register pressure, and there are also contributions from the "specialty" register classes.
For example, when you combine load optimization, address mode inference, local register availability optimization, and the div instruction, you can end up needing 5 simultaneously live infinite-weight registers.
The fix/enhancement here is to keep track of the "reserve" set of registers for each register class, and allow the register allocator to draw from that as a last resort. This behavior is guarded by the -reg-reserve flag.
This CL also includes two improvements in lowering sequences to reduce register pressure.
BUG= none
R=kschimpf@google.com
Review URL: https://codereview.chromium.org/1641653004 .
diff --git a/src/IceTargetLowering.h b/src/IceTargetLowering.h
index 3d3452e..d406fb5 100644
--- a/src/IceTargetLowering.h
+++ b/src/IceTargetLowering.h
@@ -275,8 +275,15 @@
virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
RegSetMask Exclude) const = 0;
+ /// Get the set of physical registers available for the specified Variable's
+ /// register class, applying register restrictions from the command line.
virtual const llvm::SmallBitVector &
getRegistersForVariable(const Variable *Var) const = 0;
+ /// Get the set of *all* physical registers available for the specified
+ /// Variable's register class, *not* applying register restrictions from the
+ /// command line.
+ virtual const llvm::SmallBitVector &
+ getAllRegistersForVariable(const Variable *Var) const = 0;
virtual const llvm::SmallBitVector &getAliasesForRegister(SizeT) const = 0;
void regAlloc(RegAllocKind Kind);