Merge "Fix ARM assembler to work with clang's as." am: c2d40e53e5 am: 16873a6b40 am: 5943036c6e am: 11c8562287
Original change: https://android-review.googlesource.com/c/platform/external/tremolo/+/1692372
Change-Id: I7a964a474c73cb9332fc7f7dc1743501e2e72822
diff --git a/Android.bp b/Android.bp
index 58f339e..692be12 100644
--- a/Android.bp
+++ b/Android.bp
@@ -51,17 +51,14 @@
arch: {
arm: {
+ cflags: ["-D_ARM_ASSEM_"],
+ instruction_set: "arm",
srcs: [
"Tremolo/bitwiseARM.s",
"Tremolo/dpen.s",
"Tremolo/floor1ARM.s",
"Tremolo/mdctARM.s",
],
- cflags: ["-D_ARM_ASSEM_"],
- // Assembly code in asm_arm.h does not compile with Clang.
- clang_asflags: ["-no-integrated-as"],
-
- instruction_set: "arm",
},
arm64: {
cflags: ["-DONLY_C"],
diff --git a/Tremolo/dpen.s b/Tremolo/dpen.s
index 3ed3b36..cc492cf 100644
--- a/Tremolo/dpen.s
+++ b/Tremolo/dpen.s
@@ -143,7 +143,7 @@
BLT duff
CMP r8, r7 @ if bit==0 (chase+bit==chase) (sets C)
- LDRNEB r14,[r6, r7] @ r14= t[chase]
+ LDRBNE r14,[r6, r7] @ r14= t[chase]
MOVEQ r14,#128
ADC r12,r8, r6 @ r12= chase+bit+1+t
LDRB r14,[r12,r14,LSR #7] @ r14= t[chase+bit+1+(!bit || t[chase]0x0x80)]
@@ -202,7 +202,7 @@
MOV r7, r7, LSL #1
CMP r8, r7 @ if bit==0 (chase+bit==chase) sets C
- LDRNEH r14,[r6, r7] @ r14= t[chase]
+ LDRHNE r14,[r6, r7] @ r14= t[chase]
MOVEQ r14,#0x8000
ADC r12,r8, r14,LSR #15 @ r12= 1+((chase+bit)<<1)+(!bit || t[chase]0x0x8000)
ADC r12,r12,r14,LSR #15 @ r12= t + (1+chase+bit+(!bit || t[chase]0x0x8000))<<1
diff --git a/Tremolo/mdctARM.s b/Tremolo/mdctARM.s
index c403f6c..c16c5e9 100644
--- a/Tremolo/mdctARM.s
+++ b/Tremolo/mdctARM.s
@@ -55,6 +55,14 @@
.hidden sincos_lookup0
.hidden sincos_lookup1
+ @ clang doesn't support ADRL.
+ @ Workaround based on that at https://bugs.llvm.org/show_bug.cgi?id=24350.
+ .macro ADRL reg:req, label:req
+ add \reg, pc, #((\label - .L_adrl_\@) & 0xff00)
+ add \reg, \reg, #((\label - .L_adrl_\@) - ((\label - .L_adrl_\@) & 0xff00))
+ .L_adrl_\@:
+ .endm
+
mdct_unroll_prelap:
@ r0 = out
@ r1 = post