tree bdc2a6417b93553f6c641d77bc7e5fd7547364e8
parent 94b756f3318b5dea3c1aefa670f43ae85d780144
author Masahiro Yamada <yamada.masahiro@socionext.com> 1456464098 +0900
committer Masahiro Yamada <yamada.masahiro@socionext.com> 1456685416 +0900

ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings

These settings were used only for the PH1-sLD3 and older SoCs.  The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>