fsl-ddr: make the self refresh idle threshold configurable
Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.
If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 0006c21..b213af3 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -146,6 +146,10 @@
unsigned int bstopre;
unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
+
+ /* Automatic self refresh */
+ unsigned int auto_self_refresh_en;
+ unsigned int sr_it;
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);