| commit | 454e725b3a9537b7f273bbd0cbca180f23a7a6e8 | [log] [tgz] |
|---|---|---|
| author | TsiChung Liew <Tsi-Chung.Liew@freescale.com> | Fri Aug 15 18:24:25 2008 +0000 |
| committer | John Rigby <jrigby@freescale.com> | Thu Aug 28 09:16:53 2008 -0600 |
| tree | ebff207846e99262f8d2fa717a2a87a96fd7adcc | |
| parent | 79e0799cf6e88d98d77b216a55234bf674b59a4e [diff] |
ColdFire: Change the SDRAM BRD2WT timing from 3 to 7 The user manuals recommend 7. Signed-off-by: Kurt Mahan <kmahan@freescale.com> Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>