| commit | 499b84752140a8b40f8f0956c72357743f755250 | [log] [tgz] |
|---|---|---|
| author | Matthias Schiffer <mschiffer@universe-factory.net> | Sat Mar 05 04:15:40 2016 +0100 |
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | Wed Mar 09 11:00:40 2016 +0100 |
| tree | 35d06f159bdc7df5a9fa8819c7d68801fa4506cb | |
| parent | deff6fb3a7790e93264292982000275e78bb12e5 [diff] |
MIPS: fix mips_cache fallback without __builtin_mips_cache
The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.
Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>