ARM: k2g: Update PLL Multiplier and divider values

Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18

[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
1 file changed