tree 9c06698652d1ee3e40044d62cdd60f59437d0c9e
parent 4021b4381d8d3c18a3d8732967eec3ec1624ab7b
author Masahiro Yamada <yamada.masahiro@socionext.com> 1456464101 +0900
committer Masahiro Yamada <yamada.masahiro@socionext.com> 1456685416 +0900

ARM: uniphier: merge DDR PHY init code for 3 SoCs

Now these three are almost the same.  The only difference is the DTPR1
register dependency on the DRAM size, but it can be ignored.  (It has
already been ignored in PH1-sLD8 and PH1-Pro4.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>