| commit | 562de1d6da5bdc1789bd258d464d6ca57571861d | [log] [tgz] |
|---|---|---|
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | Thu Dec 12 12:09:01 2013 +0530 |
| committer | York Sun <yorksun@freescale.com> | Thu Jan 02 14:10:13 2014 -0800 |
| tree | 84ada120ab90055522b69a080817f2c5bbb13bc4 | |
| parent | fbe76ae4e3bacd5183294488947ec148df28d55b [diff] |
board/t1040qds: Relax IFC FPGA timings Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) is 0 i.e. 0 ns hold time on writes. This may not work on higher clock freqencies. So, Increase TCH as 0x8 i.e. 8 ip_clk. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>