commit 60acde43d71cf0701b1124998bf4ab457c6640b6
author Yen Lin <yelin@nvidia.com> Wed Dec 18 11:18:46 2013 -0700
committer Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Thu Dec 19 00:00:51 2013 +0530
tree d78d680d6ee6100717a4a78472a82b796a83c4b5
parent 16f47c9c510a61ee91d6b9d02dd723522beff80f

spi: tegra: clear RDY bit prior to every transfer

The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).

It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.

Signed-off-by: Yen Lin <yelin@nvidia.com>
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

drivers/spi/tegra114_spi.c

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 4d2af48..810fa47 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -289,9 +289,6 @@
 	reg = readl(&regs->fifo_status);
 	writel(reg, &regs->fifo_status);
 
-	/* clear ready bit */
-	setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
-
 	clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
 			SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
 			(slave->cs << SPI_CMD1_CS_SEL_SHIFT));
@@ -305,7 +302,6 @@
 	/* handle data in 32-bit chunks */
 	while (num_bytes > 0) {
 		int bytes;
-		int is_read = 0;
 		int tm, i;
 
 		tmpdout = 0;
@@ -319,6 +315,9 @@
 
 		num_bytes -= bytes;
 
+		/* clear ready bit */
+		setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
+
 		clrsetbits_le32(&regs->command1,
 				SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
 				(bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
@@ -329,20 +328,14 @@
 		 * Wait for SPI transmit FIFO to empty, or to time out.
 		 * The RX FIFO status will be read and cleared last
 		 */
-		for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+		for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
 			u32 fifo_status, xfer_status;
 
-			fifo_status = readl(&regs->fifo_status);
-
-			/* We can exit when we've had both RX and TX activity */
-			if (is_read &&
-			    (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY))
-				break;
-
 			xfer_status = readl(&regs->xfer_status);
 			if (!(xfer_status & SPI_XFER_STS_RDY))
 				continue;
 
+			fifo_status = readl(&regs->fifo_status);
 			if (fifo_status & SPI_FIFO_STS_ERR) {
 				debug("%s: got a fifo error: ", __func__);
 				if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
@@ -367,7 +360,6 @@
 
 			if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
 				tmpdin = readl(&regs->rx_fifo);
-				is_read = 1;
 
 				/* swap bytes read in */
 				if (din != NULL) {
@@ -377,6 +369,9 @@
 					}
 					din += bytes;
 				}
+
+				/* We can exit when we've had both RX and TX */
+				break;
 			}
 		}