tree eadbd6bb5af57cc360c6a23bd9708e1bb86573f8
parent c292adae170fa8c27dca75963bdb0a9afc640e57
author Murali Karicheri <m-karicheri2@ti.com> 1410353699 +0300
committer Tom Rini <trini@ti.com> 1411002416 -0400

ARM: keystone: ddr3: workaround for ddr3a/3b memory issue

This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>