| commit | 9c6b47d53ed329b31c5f26e9ec710f67559c07f0 | [log] [tgz] |
|---|---|---|
| author | Matthew McClintock <msm@freescale.com> | Mon Aug 13 08:10:37 2012 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Thu Aug 23 10:24:16 2012 -0500 |
| tree | e249bf392017d29d3a90389685ac2f972c5fc4a9 | |
| parent | be7bebeac24f33bd7eef2f5047579c1a680d8df1 [diff] |
p1014rdb: set ddr bus width properly depending on SVR Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>