| commit | a9aff2f46a7f7d29a662531dbc181773f16a606d | [log] [tgz] |
|---|---|---|
| author | Simon Glass <sjg@chromium.org> | Mon Jan 19 22:16:13 2015 -0700 |
| committer | Simon Glass <sjg@chromium.org> | Sat Jan 24 06:13:45 2015 -0700 |
| tree | 4c340ea0b74ccb57fae8987f13b1aae994ef77b3 | |
| parent | 146251f87eaebbd77ca9596391890b44cbda47fb [diff] |
x86: dts: Add SPI flash MRC details for chromebook_link Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>