Merge with /home/raj/git/u-boot
diff --git a/CHANGELOG b/CHANGELOG
index 0c70d3c..a586c77 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -4,6 +4,174 @@
* Add initial support for PCI-Express on PPC440SPe (Yucca board).
+* Fix compiler warning for TRAB board.
+ Patch by Martin Krause, 07 Aug 2006
+
+* Prevent USB commands from working when USB is stopped.
+
+* Add rudimentary handling of alternate settings of USB interfaces.
+ This is in order to fix issues with some USB sticks timing out
+ during initialization. Some code readability improvements.
+
+* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
+ AMCC suggested to set the PMU bit to 0 for best performace on
+ the PPC440 DDR controller.
+ Please see doc/README.440-DDR-performance for details.
+ Patch by Stefan Roese, 28 Jul 2006
+
+* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
+ Please see doc/README.bamboo for details.
+ Patch by Stefan Roese, 27 Jul 2006
+
+* Fix CONFIG_CMDLINE_EDITING implementation
+ Patch by Stefan Roese, 27 Jul 2006
+
+* Fix preboot message on TQM5200 after switching to hush parser.
+
+* MCC200: set default configuration to low_boot DDR,
+ and support for configurable options high_boot and/or SDRAM.
+
+* Add support for 256 MB SDRAM on CPU87
+ Patch by Josef Wagner, 25 Nov 2005
+
+* Add configuration for cam5200 board (based on TQM5200S).
+
+* More code cleanup
+
+* Disabled kvme080 board in MAKEALL because of build problems.
+
+* Code cleanup
+
+* Update NetStar board
+ Patch by Ladislav Michl, 03 Nov 2005
+
+* Make code better readable.
+ Patch by Ladislav Michl, 14 Sep 2005
+
+* Enable initrd ATAG for xm250 board.
+ Patch by Josef Wagner, 05 Sep 2005
+
+* Add readline cmdline-editing extension
+ Patch by JinHua Luo, 01 Sep 2005
+
+* Add support for friendly-arm SBC-2410X board
+ Patch by JinHua Luo, 01 Sep 2005
+
+* Fix multi-part image support on i386 platform.
+ Patch by David Updegraff, 19 Aug 2005
+
+* Add support for KVME080 board
+ Patch by Sangmoon Kim, 18 Aug 2005
+
+* Fix MIPS LE build problem
+ Patch by Matej Kupljen, 10 Aug 2005
+
+* Check argument count in "mii" command.
+ Problem pointed out by Andrew Dyer, 13 Jun 2005
+
+* Cleanup TQM5200 board configurations:
+ - make highboot configurations use environment at high end, too,
+ to avoid flash fragmentation
+ - always use redundand environment
+ - don't enable video code for modules without graphics controller
+ - provide useful (though different) mtdparts settings
+ - get rid of CONFIG_CS_AUTOCONF which was always set anyway
+
+* Extend mkconfig tool to print more useful target name
+
+* Add support for high-boot on TQM5200 and TQM5200S boards.
+ Hint: the CPLD on the TQM5200 must be programmed with a software
+ version supporting the high boot option! The new TQM5200S is
+ already supporting this option. On the TQM5200 this option will be
+ supported in configurations with MPC5200 rev B processors.
+ To actually "high boot", set jumper X30 on the STK52xx.
+ Patch by Martin Krause, 12 Jul 2006
+
+* Add support for new TQM5200 revisions
+ - Support for TQM5200S (short version without graphic controller)
+ - Support for modules with 'N' type S29GL128N Spansion flashes
+ (requires changes to flash layout)
+ - Support for MPC5200B cpu (mostly support for second SDRAM bank)
+ Patch by Martin Krause, 07 Jul 2006
+
+* Fix support for PS/2 keyboard on TQM85xx boards
+ The PS/2 keyobard driver for the TQM85xx modules only supports the
+ internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
+ include a DUART, the TQM8560 modules can't be used with the PS/2
+ keyboard controller on the STK85xx board.
+ The PS/2 keyboard driver should work with the modules TQM8540,
+ TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
+ Make sure the PS/2 controller on the STK85xx is programmed. Jumper
+ settings: X66 1-2, 9-10; X61 2-3
+ Patch by Martin Krause, 21 Jun 2006
+
+* Adjust RTC century handling on STK52xx board to match Linux driver.
+ Patch by Martin Krause, 12 Jun 2006
+
+* Adjust filenames for USB update images on TRAB board.
+ During an automatic update via USB stick, U-Boot searches for
+ images with the name "firmware.img" and "kernel.img". This names
+ are now changed to "firmw_01.img" and "kernl_01.img". This is done,
+ to prevent updates of new boards (with the new macronics "c" step
+ flashes) with old, incompatible firmware or kernel versions.
+ Patch by Martin Krause, 21 Jun 2006
+
+* Bugfix in VFD routine on TRAB board.
+ Make sure upper lext pixel can be set to blue, too
+ (so far only red was possible).
+ Patch by Martin Krause, 15 Feb 2006
+
+* Enable buffered flash writes for TB5200 board.
+
+* Fix some bugs in TRAB board flash driver.
+ - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
+ - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
+ - remove "Unlock Bypass" mode, because macronix flashes do not support
+ this mode officially
+ - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
+ for Intel compatible flashes, not for AMD compatible.
+ Patch by Martin Krause, 15 Feb 2006
+
+* Add additional error messages to flash driver on TRAB board
+ (for erase errors and timeout errors)
+ Patch by Martin Krause, 14 Feb 2006
+
+* Add support for TB5200 board
+ The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
+ integrated in a little aluminium case.
+ Patch by Martin Krause, 8 Jun 2006
+
+* Enable buffered flash writes for TQM5200 board.
+
+* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick.
+
+* Add support for TQM885D board.
+ Patch by Martin Krause, 20 Mar 2006
+
+* Fix FEC initialisation: All MII configuration is done via FEC1
+ registers, but MII_SPEED was configured according to FEC used. So
+ if only FEC2 was used, this caused the real MII_SPEED register in
+ FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages.
+ Fix: always configure MII_SPEED on FEC1 only.
+ Patch by Markus Klotzbuecher, 12 Jul 2006
+
+* Add support for SPC1920 board.
+ Patch by Markus Klotzbuecher, 12 Jul 2006
+
+* MCC200 board: support console on any one of the Quad UART ports.
+
+* Fix error in flash protection calculation on MCC200 board.
+
+* Major PCMCIA Cleanup to make code better readable and maintainable.
+ Notes:
+ - Board-dependend code for RPXLITE and RPXCLASSIC-based boards
+ placed to the drivers/rpx_pmcia.c file to avoid duplication.
+ Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
+ - drivers/i82365.c has been split into two parts located at
+ board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
+ the only boards using CONFIG_82365).
+ - Changes were tested for clean build and *very* *few* boards.
+
* Fix timer problems on AMCC yucca board.
Set Timer Clock Select to use CPU clock as a timer input source.
@@ -31,14 +199,14 @@
* VoiceBlue update: use new MTD flash partitioning methods, use more
reasonable TEXT_BASE, update default environment and enable keyed
autoboot.
- Patch by Ladislav Michl, 16. Aug 2005
+ Patch by Ladislav Michl, 16. Aug 2005
* Add forgotten changes for the PLEB 2 Board.
Patch by David Snowdon, 13. Aug 2005
* Add support for wrPPMC7xx/74xx boards
Patch by Richard Danter, 12 Aug 2005
-
+
* Add support for gth2 board
Patch by Thomas Lange, Aug 11 2005
@@ -60,7 +228,7 @@
With this fix pin I2CSCL (PG6) is really configured as GPIO
so the clock pulses are really generated.
Patch by Martin Krause, 04 Apr 2006
-
+
* Fix DDR6 errata on TQM834x boards
Patch by Thomas Waehner, 07 Mar 2006
@@ -77,7 +245,7 @@
has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
- In tsc2000_read_channel() the delay after setting the multiplexer
+ In tsc2000_read_channel() the delay after setting the multiplexer
to a temperature channel is increased from 1,5 ms to 10 ms. This
is to allow the multiplexer inputs to stabilize after huge steps
of the input signal level.
diff --git a/CREDITS b/CREDITS
index 94153a7..32d3060 100644
--- a/CREDITS
+++ b/CREDITS
@@ -233,6 +233,7 @@
N: Sangmoon Kim
E: dogoil@etinsys.com
D: Support for debris board
+D: Support for KVME080 board
N: Frederick W. Klatt
E: fred.klatt@windriver.com
diff --git a/MAINTAINERS b/MAINTAINERS
index aaf91cd..e1baa42 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -197,6 +197,7 @@
Sangmoon Kim <dogoil@etinsys.com>
debris MPC8245
+ KVME080 MPC8245
Thomas Lange <thomas@corelatus.se>
diff --git a/MAKEALL b/MAKEALL
index 0e80855..467a9be 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -27,14 +27,14 @@
LIST_5xxx=" \
BC3450 cpci5200 EVAL5200 icecube_5100 \
icecube_5200 lite5200b mcc200 o2dnt \
- pf5200 PM520 Total5100 Total5200 \
- Total5200_Rev2 TQM5200 \
+ pf5200 PM520 TB5200 Total5100 \
+ Total5200 Total5200_Rev2 TQM5200 TQM5200_B \
+ TQM5200S \
"
#########################################################################
## MPC8xx Systems
#########################################################################
-
LIST_8xx=" \
Adder87x GENIETV MBX860T R360MPI \
AdderII GTH MHPC RBC823 \
@@ -44,16 +44,18 @@
CCM IP860 NETPHONE RPXlite_DW \
cogent_mpc8xx IVML24 NETTA RRvision \
ELPT860 IVML24_128 NETTA2 SM850 \
- EP88x IVML24_256 NETTA_ISDN SPD823TS \
- ESTEEM192E IVMS8 NETVIA svm_sc8xx \
- ETX094 IVMS8_128 NETVIA_V2 SXNI855T \
- FADS823 IVMS8_256 NX823 TOP860 \
- FADS850SAR KUP4K pcu_e TQM823L \
- FADS860T KUP4X QS823 TQM823L_LCD \
- FLAGADM LANTEC QS850 TQM850L \
- FPS850L lwmon QS860T TQM855L \
- GEN860T MBX quantum TQM860L \
- GEN860T_SC uc100 \
+ EP88x IVML24_256 NETTA_ISDN spc1920 \
+ ESTEEM192E IVMS8 NETVIA SPD823TS \
+ ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \
+ FADS823 IVMS8_256 NX823 SXNI855T \
+ FADS850SAR KUP4K pcu_e TOP860 \
+ FADS860T KUP4X QS823 TQM823L \
+ FLAGADM LANTEC QS850 TQM823L_LCD \
+ FPS850L lwmon QS860T TQM850L \
+ GEN860T MBX quantum TQM855L \
+ GEN860T_SC TQM860L \
+ TQM885D \
+ uc100 \
v37 \
"
@@ -93,9 +95,9 @@
LIST_824x=" \
A3000 barco BMW CPC45 \
CU824 debris eXalion HIDDEN_DRAGON \
- MOUSSE MUSENKI MVBLUE OXC \
- PN62 Sandpoint8240 Sandpoint8245 sbc8240 \
- SL8245 utx8245 \
+ MOUSSE MUSENKI MVBLUE \
+ OXC PN62 Sandpoint8240 Sandpoint8245 \
+ sbc8240 SL8245 utx8245 \
"
#########################################################################
@@ -179,9 +181,10 @@
ap966 cp920t cp922_XA10 cp926ejs \
cp946es cp966 lpd7a400 mp2usb \
mx1ads mx1fs2 netstar omap1510inn \
- omap1610h2 omap1610inn omap730p2 scb9328 \
- smdk2400 smdk2410 trab VCMA9 \
- versatile versatileab versatilepb voiceblue
+ omap1610h2 omap1610inn omap730p2 sbc2410x \
+ scb9328 smdk2400 smdk2410 trab \
+ VCMA9 versatile versatileab versatilepb \
+ voiceblue \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 48b53f0..128ae59 100644
--- a/Makefile
+++ b/Makefile
@@ -7,7 +7,7 @@
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
+# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
@@ -323,13 +323,25 @@
@./mkconfig -a IceCube ppc mpc5xxx icecube
mcc200_config \
-mcc200_lowboot_config: unconfig
+mcc200_SDRAM \
+mcc200_highboot \
+mcc200_highboot_SDRAM: unconfig
@ >include/config.h
- @[ -z "$(findstring lowboot_,$@)" ] || \
- { echo "TEXT_BASE = 0xFC000000" >board/mcc200/config.tmp ; \
- echo "... with lowboot configuration" ; \
+ @[ -n "$(findstring highboot,$@)" ] || \
+ { echo "... with lowboot configuration" ; \
}
- @./mkconfig mcc200 ppc mpc5xxx mcc200
+ @[ -z "$(findstring highboot,$@)" ] || \
+ { echo "TEXT_BASE = 0xFFF00000" >board/mcc200/config.tmp ; \
+ echo "... with highboot configuration" ; \
+ }
+ @[ -n "$(findstring _SDRAM,$@)" ] || \
+ { echo "... with DDR" ; \
+ }
+ @[ -z "$(findstring _SDRAM,$@)" ] || \
+ { echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \
+ echo "... with SDRAM" ; \
+ }
+ @./mkconfig -a mcc200 ppc mpc5xxx mcc200
o2dnt_config:
@./mkconfig o2dnt ppc mpc5xxx o2dnt
@@ -356,15 +368,21 @@
@./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
spieval_config: unconfig
- @echo "#define CONFIG_CS_AUTOCONF">>include/config.h
- @echo "... with automatic CS configuration"
@./mkconfig -a spieval ppc mpc5xxx tqm5200
+TB5200_B_config \
+TB5200_config: unconfig
+ @[ -z "$(findstring _B,$@)" ] || \
+ { echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
+ echo "... with MPC5200B processor" ; \
+ }
+ @./mkconfig -n $@ -a TB5200 ppc mpc5xxx tqm5200
+
MINI5200_config \
EVAL5200_config \
TOP5200_config: unconfig
@ echo "#define CONFIG_$(@:_config=) 1" >include/config.h
- @./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
+ @./mkconfig -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
Total5100_config \
Total5200_config \
@@ -395,20 +413,39 @@
@./mkconfig -a Total5200 ppc mpc5xxx total5200
TQM5200_config \
+TQM5200_B_config \
+TQM5200_B_HIGHBOOT_config \
+TQM5200S_config \
+TQM5200S_HIGHBOOT_config \
TQM5200_STK100_config \
+cam5200_config \
MiniFAP_config: unconfig
@ >include/config.h
@[ -z "$(findstring MiniFAP,$@)" ] || \
{ echo "#define CONFIG_MINIFAP" >>include/config.h ; \
echo "... TQM5200_AC on MiniFAP" ; \
}
+ @[ -z "$(findstring cam5200,$@)" ] || \
+ { echo "#define CONFIG_CAM5200" >>include/config.h ; \
+ echo "#define CONFIG_TQM5200S" >>include/config.h ; \
+ echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
+ echo "... TQM5200S on Cam5200" ; \
+ }
@[ -z "$(findstring STK100,$@)" ] || \
{ echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \
echo "... on a STK52XX.100 base board" ; \
}
- @echo "#define CONFIG_CS_AUTOCONF">>include/config.h ;
- @echo "... with automatic CS configuration" ;
- @./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
+ @[ -z "$(findstring TQM5200_B,$@)" ] || \
+ { echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
+ }
+ @[ -z "$(findstring TQM5200S,$@)" ] || \
+ { echo "#define CONFIG_TQM5200S" >>include/config.h ; \
+ echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
+ }
+ @[ -z "$(findstring HIGHBOOT,$@)" ] || \
+ { echo "TEXT_BASE = 0xFFF00000" >board/tqm5200/config.tmp ; \
+ }
+ @./mkconfig -n $@ -a TQM5200 ppc mpc5xxx tqm5200
#########################################################################
## MPC8xx Systems
@@ -705,6 +742,9 @@
SM850_config : unconfig
@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
+spc1920_config:
+ @./mkconfig $(@:_config=) ppc mpc8xx spc1920
+
SPD823TS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx spd8xx
@@ -742,6 +782,7 @@
TQM860M_config \
TQM862M_config \
TQM866M_config \
+TQM885D_config \
virtlab2_config: unconfig
@ >include/config.h
@[ -z "$(findstring _LCD,$@)" ] || \
@@ -1034,6 +1075,9 @@
HIDDEN_DRAGON_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
+kvme080_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc824x kvme080 etin
+
MOUSSE_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x mousse
@@ -1457,7 +1501,7 @@
ppmc7xx_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
-
+
#========================================================================
# ARM
#========================================================================
@@ -1591,6 +1635,9 @@
fi;
@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
+sbc2410x_config: unconfig
+ @./mkconfig $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
+
scb9328_config : unconfig
@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
diff --git a/README b/README
index 5ed30f2..e772c1a 100644
--- a/README
+++ b/README
@@ -306,7 +306,7 @@
CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250,
CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110,
- CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
+ CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400,
CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
@@ -1490,6 +1490,12 @@
of the backslashes before semicolons and special
symbols.
+- Commandline Editing and History:
+ CONFIG_CMDLINE_EDITING
+
+ Enable editiong and History functions for interactive
+ commandline input operations
+
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c
index 86448e3..6388052 100644
--- a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c
@@ -147,14 +147,14 @@
if (EVT.oldMove != -1) {
EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */
EVT.evtq[EVT.oldMove].where_y = evt.where_y;
-/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; // TODO! */
-/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; // TODO! */
+/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; / / TODO! */
+/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; / / TODO! */
evt.what = 0;
}
else {
EVT.oldMove = EVT.freeHead; /* Save id of this move event */
-/* evt.relative_x = mickeyX; // TODO! */
-/* evt.relative_y = mickeyY; // TODO! */
+/* evt.relative_x = mickeyX; / / TODO! */
+/* evt.relative_y = mickeyY; / / TODO! */
}
}
else
diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h
index 081d5fd..c413439 100644
--- a/board/Marvell/include/core.h
+++ b/board/Marvell/include/core.h
@@ -91,7 +91,10 @@
#define _1G 0x40000000
#define _2G 0x80000000
+#ifndef BOOL_WAS_DEFINED
+#define BOOL_WAS_DEFINED
typedef enum _bool{false,true} bool;
+#endif
/* Little to Big endian conversion macros */
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
index 35cb655..9d7f4c3 100644
--- a/board/amcc/bamboo/config.mk
+++ b/board/amcc/bamboo/config.mk
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -21,7 +21,7 @@
# MA 02111-1307 USA
#
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFA0000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
index 86d0db7..92dc9d4 100644
--- a/board/amcc/yellowstone/yellowstone.c
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -313,13 +313,13 @@
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
+ mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram(mem_cfg0, 0x84000000); /* Enable */
+ mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 6742441..7f2e718 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -309,13 +309,13 @@
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
+ mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram(mem_cfg0, 0x84000000); /* Enable */
+ mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
index 9c7afb2..e698b20 100644
--- a/board/amcc/yucca/cmd_yucca.c
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -30,7 +30,7 @@
#include <asm/byteorder.h>
extern void print_evb440spe_info(void);
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
int flag, int argc, char *argv[]);
extern int cmd_get_data_size(char* arg, int default_size);
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
index c5a2e31..15b8a46 100644
--- a/board/amcc/yucca/flash.c
+++ b/board/amcc/yucca/flash.c
@@ -1004,7 +1004,7 @@
}
} /*else if (index == 0) {*/
/* if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
-/* index = 8;*//* sram below op code flash -> new index 8*/
+/* index = 8;*/ /* sram below op code flash -> new index 8*/
/* }*/
DEBUGF("\n");
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index a950eac..5a3dd0e 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -121,7 +121,7 @@
/**************************************************************************
* TLB table for revB
*
- * Notice: revB of the 440SPe chip is very strict about PLB real addressess
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
* and ranges to be mapped for config space: it seems to only work with
* d_nnnn_nnnn range (hangs the core upon config transaction attempts when
* set otherwise) while revA uses c_nnnn_nnnn.
diff --git a/board/atc/Makefile b/board/atc/Makefile
index 7a2014d..7573a0c 100644
--- a/board/atc/Makefile
+++ b/board/atc/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o ti113x.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/atc/ti113x.c b/board/atc/ti113x.c
new file mode 100644
index 0000000..d5e935c
--- /dev/null
+++ b/board/atc/ti113x.c
@@ -0,0 +1,637 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ *
+ * Lots of code copied from:
+ *
+ * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
+ * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
+ * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_I82365
+
+#include <command.h>
+#include <pci.h>
+#include <pcmcia.h>
+#include <asm/io.h>
+
+#include <pcmcia/ss.h>
+#include <pcmcia/i82365.h>
+#include <pcmcia/yenta.h>
+#include <pcmcia/ti113x.h>
+
+static struct pci_device_id supported[] = {
+ {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
+ {0, 0}
+};
+
+#define CYCLE_TIME 120
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev);
+#endif
+
+typedef struct socket_info_t {
+ pci_dev_t dev;
+ u_short bcr;
+ u_char pci_lat, cb_lat, sub_bus, cache;
+ u_int cb_phys;
+
+ socket_cap_t cap;
+ u_short type;
+ u_int flags;
+ ti113x_state_t state;
+} socket_info_t;
+
+static socket_info_t socket;
+static socket_state_t state;
+static struct pccard_mem_map mem;
+static struct pccard_io_map io;
+
+/*====================================================================*/
+
+/* Some PCI shortcuts */
+
+static int pci_readb (socket_info_t * s, int r, u_char * v)
+{
+ return pci_read_config_byte (s->dev, r, v);
+}
+static int pci_writeb (socket_info_t * s, int r, u_char v)
+{
+ return pci_write_config_byte (s->dev, r, v);
+}
+static int pci_readw (socket_info_t * s, int r, u_short * v)
+{
+ return pci_read_config_word (s->dev, r, v);
+}
+static int pci_writew (socket_info_t * s, int r, u_short v)
+{
+ return pci_write_config_word (s->dev, r, v);
+}
+static int pci_readl (socket_info_t * s, int r, u_int * v)
+{
+ return pci_read_config_dword (s->dev, r, v);
+}
+static int pci_writel (socket_info_t * s, int r, u_int v)
+{
+ return pci_write_config_dword (s->dev, r, v);
+}
+
+/*====================================================================*/
+
+#define cb_readb(s, r) readb((s)->cb_phys + (r))
+#define cb_readl(s, r) readl((s)->cb_phys + (r))
+#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
+#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
+
+static u_char i365_get (socket_info_t * s, u_short reg)
+{
+ return cb_readb (s, 0x0800 + reg);
+}
+
+static void i365_set (socket_info_t * s, u_short reg, u_char data)
+{
+ cb_writeb (s, 0x0800 + reg, data);
+}
+
+static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
+{
+ i365_set (s, reg, i365_get (s, reg) | mask);
+}
+
+static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
+{
+ i365_set (s, reg, i365_get (s, reg) & ~mask);
+}
+
+#if 0 /* not used */
+static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
+{
+ u_char d = i365_get (s, reg);
+
+ i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
+}
+
+static u_short i365_get_pair (socket_info_t * s, u_short reg)
+{
+ return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
+}
+#endif /* not used */
+
+static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
+{
+ i365_set (s, reg, data & 0xff);
+ i365_set (s, reg + 1, data >> 8);
+}
+
+/*======================================================================
+
+ Code to save and restore global state information for TI 1130 and
+ TI 1131 controllers, and to set and report global configuration
+ options.
+
+======================================================================*/
+
+static void ti113x_get_state (socket_info_t * s)
+{
+ ti113x_state_t *p = &s->state;
+
+ pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
+ pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
+ pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
+ pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
+ pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
+}
+
+static void ti113x_set_state (socket_info_t * s)
+{
+ ti113x_state_t *p = &s->state;
+
+ pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
+ pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
+ pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
+ pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
+ pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
+ pci_writel (s, TI12XX_IRQMUX, p->irqmux);
+ i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
+ i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
+}
+
+static u_int ti113x_set_opts (socket_info_t * s)
+{
+ ti113x_state_t *p = &s->state;
+ u_int mask = 0xffff;
+
+ p->cardctl &= ~TI113X_CCR_ZVENABLE;
+ p->cardctl |= TI113X_CCR_SPKROUTEN;
+
+ return mask;
+}
+
+/*======================================================================
+
+ Routines to handle common CardBus options
+
+======================================================================*/
+
+/* Default settings for PCI command configuration register */
+#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
+ PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
+
+static void cb_get_state (socket_info_t * s)
+{
+ pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
+ pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
+ pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
+ pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
+ pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
+ pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
+}
+
+static void cb_set_state (socket_info_t * s)
+{
+ pci_writel (s, CB_LEGACY_MODE_BASE, 0);
+ pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
+ pci_writew (s, PCI_COMMAND, CMD_DFLT);
+ pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
+ pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
+ pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
+ pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
+ pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
+ pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
+}
+
+static void cb_set_opts (socket_info_t * s)
+{
+ if (s->cache == 0)
+ s->cache = 8;
+ if (s->pci_lat == 0)
+ s->pci_lat = 0xa8;
+ if (s->cb_lat == 0)
+ s->cb_lat = 0xb0;
+}
+
+/*======================================================================
+
+ Power control for Cardbus controllers: used both for 16-bit and
+ Cardbus cards.
+
+======================================================================*/
+
+static int cb_set_power (socket_info_t * s, socket_state_t * state)
+{
+ u_int reg = 0;
+
+ /* restart card voltage detection if it seems appropriate */
+ if ((state->Vcc == 0) && (state->Vpp == 0) &&
+ !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
+ cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
+ switch (state->Vcc) {
+ case 0:
+ reg = 0;
+ break;
+ case 33:
+ reg = CB_SC_VCC_3V;
+ break;
+ case 50:
+ reg = CB_SC_VCC_5V;
+ break;
+ default:
+ return -1;
+ }
+ switch (state->Vpp) {
+ case 0:
+ break;
+ case 33:
+ reg |= CB_SC_VPP_3V;
+ break;
+ case 50:
+ reg |= CB_SC_VPP_5V;
+ break;
+ case 120:
+ reg |= CB_SC_VPP_12V;
+ break;
+ default:
+ return -1;
+ }
+ if (reg != cb_readl (s, CB_SOCKET_CONTROL))
+ cb_writel (s, CB_SOCKET_CONTROL, reg);
+
+ return 0;
+}
+
+/*======================================================================
+
+ Generic routines to get and set controller options
+
+======================================================================*/
+
+static void get_bridge_state (socket_info_t * s)
+{
+ ti113x_get_state (s);
+ cb_get_state (s);
+}
+
+static void set_bridge_state (socket_info_t * s)
+{
+ cb_set_state (s);
+ i365_set (s, I365_GBLCTL, 0x00);
+ i365_set (s, I365_GENCTL, 0x00);
+ ti113x_set_state (s);
+}
+
+static void set_bridge_opts (socket_info_t * s)
+{
+ ti113x_set_opts (s);
+ cb_set_opts (s);
+}
+
+/*====================================================================*/
+#define PD67_EXT_INDEX 0x2e /* Extension index */
+#define PD67_EXT_DATA 0x2f /* Extension data */
+#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
+
+#define pd67_ext_get(s, r) \
+ (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
+
+static int i365_get_status (socket_info_t * s, u_int * value)
+{
+ u_int status;
+
+ status = i365_get (s, I365_IDENT);
+ status = i365_get (s, I365_STATUS);
+ *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
+ if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
+ *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
+ } else {
+ *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
+ *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
+ }
+ *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
+ *value |= (status & I365_CS_READY) ? SS_READY : 0;
+ *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
+
+ status = cb_readl (s, CB_SOCKET_STATE);
+ *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
+ *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
+ *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
+ *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
+ /* For now, ignore cards with unsupported voltage keys */
+ if (*value & SS_XVCARD)
+ *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
+
+ return 0;
+} /* i365_get_status */
+
+static int i365_set_socket (socket_info_t * s, socket_state_t * state)
+{
+ u_char reg;
+
+ set_bridge_state (s);
+
+ /* IO card, RESET flag */
+ reg = 0;
+ reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
+ reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
+ i365_set (s, I365_INTCTL, reg);
+
+ reg = I365_PWR_NORESET;
+ if (state->flags & SS_PWR_AUTO)
+ reg |= I365_PWR_AUTO;
+ if (state->flags & SS_OUTPUT_ENA)
+ reg |= I365_PWR_OUT;
+
+ cb_set_power (s, state);
+ reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
+
+ if (reg != i365_get (s, I365_POWER))
+ i365_set (s, I365_POWER, reg);
+
+ return 0;
+} /* i365_set_socket */
+
+/*====================================================================*/
+
+static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
+{
+ u_short base, i;
+ u_char map;
+
+ debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
+ mem->map, mem->flags, mem->speed,
+ mem->sys_start, mem->sys_stop, mem->card_start);
+
+ map = mem->map;
+ if ((map > 4) ||
+ (mem->card_start > 0x3ffffff) ||
+ (mem->sys_start > mem->sys_stop) ||
+ (mem->speed > 1000)) {
+ return -1;
+ }
+
+ /* Turn off the window before changing anything */
+ if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
+ i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
+
+ /* Take care of high byte, for PCI controllers */
+ i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
+
+ base = I365_MEM (map);
+ i = (mem->sys_start >> 12) & 0x0fff;
+ if (mem->flags & MAP_16BIT)
+ i |= I365_MEM_16BIT;
+ if (mem->flags & MAP_0WS)
+ i |= I365_MEM_0WS;
+ i365_set_pair (s, base + I365_W_START, i);
+
+ i = (mem->sys_stop >> 12) & 0x0fff;
+ switch (mem->speed / CYCLE_TIME) {
+ case 0:
+ break;
+ case 1:
+ i |= I365_MEM_WS0;
+ break;
+ case 2:
+ i |= I365_MEM_WS1;
+ break;
+ default:
+ i |= I365_MEM_WS1 | I365_MEM_WS0;
+ break;
+ }
+ i365_set_pair (s, base + I365_W_STOP, i);
+
+ i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
+ if (mem->flags & MAP_WRPROT)
+ i |= I365_MEM_WRPROT;
+ if (mem->flags & MAP_ATTRIB)
+ i |= I365_MEM_REG;
+ i365_set_pair (s, base + I365_W_OFF, i);
+
+ /* Turn on the window if necessary */
+ if (mem->flags & MAP_ACTIVE)
+ i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
+ return 0;
+} /* i365_set_mem_map */
+
+static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
+{
+ u_char map, ioctl;
+
+ map = io->map;
+ /* comment out: comparison is always false due to limited range of data type */
+ if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
+ (io->stop < io->start))
+ return -1;
+ /* Turn off the window before changing anything */
+ if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
+ i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
+ i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
+ i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
+ ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
+ if (io->speed)
+ ioctl |= I365_IOCTL_WAIT (map);
+ if (io->flags & MAP_0WS)
+ ioctl |= I365_IOCTL_0WS (map);
+ if (io->flags & MAP_16BIT)
+ ioctl |= I365_IOCTL_16BIT (map);
+ if (io->flags & MAP_AUTOSZ)
+ ioctl |= I365_IOCTL_IOCS16 (map);
+ i365_set (s, I365_IOCTL, ioctl);
+ /* Turn on the window if necessary */
+ if (io->flags & MAP_ACTIVE)
+ i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
+ return 0;
+} /* i365_set_io_map */
+
+/*====================================================================*/
+
+int i82365_init (void)
+{
+ u_int val;
+ int i;
+
+ if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
+ /* Controller not found */
+ return 1;
+ }
+ debug ("i82365 Device Found!\n");
+
+ pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
+ socket.cb_phys &= ~0xf;
+
+ get_bridge_state (&socket);
+ set_bridge_opts (&socket);
+
+ i = i365_get_status (&socket, &val);
+
+ if (val & SS_DETECT) {
+ if (val & SS_3VCARD) {
+ state.Vcc = state.Vpp = 33;
+ puts (" 3.3V card found: ");
+ } else if (!(val & SS_XVCARD)) {
+ state.Vcc = state.Vpp = 50;
+ puts (" 5.0V card found: ");
+ } else {
+ puts ("i82365: unsupported voltage key\n");
+ state.Vcc = state.Vpp = 0;
+ }
+ } else {
+ /* No card inserted */
+ puts ("No card\n");
+ return 1;
+ }
+
+ state.flags = SS_IOCARD | SS_OUTPUT_ENA;
+ state.csc_mask = 0;
+ state.io_irq = 0;
+
+ i365_set_socket (&socket, &state);
+
+ for (i = 500; i; i--) {
+ if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
+ break;
+ udelay (1000);
+ }
+
+ if (i == 0) {
+ /* PC Card not ready for data transfer */
+ puts ("i82365 PC Card not ready for data transfer\n");
+ return 1;
+ }
+ debug (" PC Card ready for data transfer: ");
+
+ mem.map = 0;
+ mem.flags = MAP_ATTRIB | MAP_ACTIVE;
+ mem.speed = 300;
+ mem.sys_start = CFG_PCMCIA_MEM_ADDR;
+ mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
+ mem.card_start = 0;
+ i365_set_mem_map (&socket, &mem);
+
+ io.map = 0;
+ io.flags = MAP_AUTOSZ | MAP_ACTIVE;
+ io.speed = 0;
+ io.start = 0x0100;
+ io.stop = 0x010F;
+ i365_set_io_map (&socket, &io);
+
+#ifdef DEBUG
+ i82365_dump_regions (socket.dev);
+#endif
+
+ return 0;
+}
+
+void i82365_exit (void)
+{
+ io.map = 0;
+ io.flags = 0;
+ io.speed = 0;
+ io.start = 0;
+ io.stop = 0x1;
+
+ i365_set_io_map (&socket, &io);
+
+ mem.map = 0;
+ mem.flags = 0;
+ mem.speed = 0;
+ mem.sys_start = 0;
+ mem.sys_stop = 0x1000;
+ mem.card_start = 0;
+
+ i365_set_mem_map (&socket, &mem);
+
+ socket.state.sysctl &= 0xFFFF00FF;
+
+ state.Vcc = state.Vpp = 0;
+
+ i365_set_socket (&socket, &state);
+}
+
+int pcmcia_on (void)
+{
+ u_int rc;
+
+ debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ rc = i82365_init();
+ if (rc)
+ goto exit;
+
+ rc = check_ide_device(0);
+ if (rc == 0)
+ goto exit;
+
+ i82365_exit();
+
+exit:
+ return rc;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+ printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ i82365_exit();
+
+ return 0;
+}
+#endif
+
+/*======================================================================
+
+ Debug stuff
+
+======================================================================*/
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev)
+{
+ u_int tmp[2];
+ u_int *mem = (void *) socket.cb_phys;
+ u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
+ u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
+
+ pci_read_config_dword (dev, 0x00, tmp + 0);
+ pci_read_config_dword (dev, 0x80, tmp + 1);
+
+ printf ("PCI CONF: %08X ... %08X\n",
+ tmp[0], tmp[1]);
+ printf ("PCI MEM: ... %08X ... %08X\n",
+ mem[0x8 / 4], mem[0x800 / 4]);
+ printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
+ cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
+ cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
+ printf ("CIS CONF: %02X %02X %02X ...\n",
+ cis[0x200], cis[0x202], cis[0x204]);
+ printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
+ ide[0], ide[1], ide[2], ide[3],
+ ide[4], ide[5], ide[6], ide[7]);
+}
+#endif /* DEBUG */
+
+#endif /* CONFIG_I82365 */
diff --git a/board/c2mon/Makefile b/board/c2mon/Makefile
index 7a2014d..7b2b545 100644
--- a/board/c2mon/Makefile
+++ b/board/c2mon/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c
new file mode 100644
index 0000000..5e50c4d
--- /dev/null
+++ b/board/c2mon/pcmcia.c
@@ -0,0 +1,284 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "C2MON"
+
+static void cfg_ports (void)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ ushort sreg;
+
+ immap = (immap_t *)CFG_IMMR;
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /*
+ * Configure Port C for TPS2211 PC-Card Power-Interface Switch
+ *
+ * Switch off all voltages, assert shutdown
+ */
+ sreg = immap->im_ioport.iop_pcdat;
+ sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */
+ sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */
+ immap->im_ioport.iop_pcdat = sreg;
+
+ immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS);
+ immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS;
+
+ debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n",
+ immap->im_ioport.iop_pcpar,
+ immap->im_ioport.iop_pcdir,
+ immap->im_ioport.iop_pcdat);
+
+ /*
+ * Configure Port B for TPS2211 PC-Card Power-Interface Switch
+ *
+ * Over-Current Input only
+ */
+ cp->cp_pbpar &= ~(TPS2211_INPUTS);
+ cp->cp_pbdir &= ~(TPS2211_INPUTS);
+
+ debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
+ cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, pipr, mask;
+ ushort sreg;
+ int i;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+ cfg_ports ();
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ pipr = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ pipr,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+ sreg = immap->im_ioport.iop_pcdat;
+ if ((pipr & mask) == mask) {
+ sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
+ TPS2211_VCCD1); /* 5V on */
+ sreg &= ~(TPS2211_VCCD0); /* 3V off */
+ puts (" 5.0V card found: ");
+ } else {
+ sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
+ TPS2211_VCCD0); /* 3V on */
+ sreg &= ~(TPS2211_VCCD1); /* 5V off */
+ puts (" 3.3V card found: ");
+ }
+
+ debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n",
+ sreg,
+ ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off",
+ (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off"
+ );
+
+ immap->im_ioport.iop_pcdat = sreg;
+
+ /* Wait 500 ms; use this to check for over-current */
+ for (i=0; i<5000; ++i) {
+ if ((cp->cp_pbdat & TPS2211_OC) == 0) {
+ printf (" *** Overcurrent - Safety shutdown ***\n");
+ immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1);
+ return (1);
+ }
+ udelay (100);
+ }
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+ /* Configure PCMCIA General Control Register */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ /* ALl voltages off / Hi-Z */
+ immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 |
+ TPS2211_VCCD0 | TPS2211_VCCD1 );
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+ ushort sreg;
+
+ debug ("voltage_set: "
+ PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ immap = (immap_t *)CFG_IMMR;
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn all power pins to Hi-Z
+ */
+ debug ("PCMCIA power OFF\n");
+ cfg_ports (); /* Enables switch, but all in Hi-Z */
+
+ sreg = immap->im_ioport.iop_pcdat;
+ sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */
+
+ switch(vcc) {
+ case 0: break; /* Switch off */
+ case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */
+ sreg &= ~TPS2211_VCCD1;
+ break;
+ case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */
+ sreg |= TPS2211_VCCD1;
+ break;
+ default: goto done;
+ }
+
+ /* Checking supported voltages */
+
+ debug ("PIPR: 0x%x --> %s\n",
+ pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+ immap->im_ioport.iop_pcdat = sreg;
+
+#ifdef DEBUG
+{
+ char *s;
+
+ if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) {
+ s = "at 3.3V";
+ } else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) {
+ s = "at 5.0V";
+ } else {
+ s = "down";
+ }
+ printf ("PCMCIA powered %s\n", s);
+}
+#endif
+
+done:
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c
index c84fbae..6ca3e7b 100644
--- a/board/cpc45/pd67290.c
+++ b/board/cpc45/pd67290.c
@@ -1,4 +1,6 @@
-/* pd67290.c - system configuration module for SPD67290
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,51 +20,799 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
- * (C) 2004 DENX Software Engineering, Heiko Schocher <hs@denx.de>
+ ********************************************************************
+ *
+ * Lots of code copied from:
+ *
+ * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
+ * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
+ * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
*/
#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-/* imports */
-#include <mpc824x.h>
+#ifdef CONFIG_I82365
+
+#include <command.h>
+#include <pci.h>
+#include <pcmcia.h>
+#include <asm/io.h>
+
+#include <pcmcia/ss.h>
+#include <pcmcia/i82365.h>
+#include <pcmcia/yenta.h>
+#include <pcmcia/cirrus.h>
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
- {}
+ {0, 0}
};
-/***************************************************************************
-*
-* SPD67290Init -
-*
-* RETURNS: -1 on error, 0 if OK
-*/
+#define CYCLE_TIME 120
-int SPD67290Init (void)
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev);
+#endif
+
+typedef struct socket_info_t {
+ pci_dev_t dev;
+ u_short bcr;
+ u_char pci_lat, cb_lat, sub_bus, cache;
+ u_int cb_phys;
+
+ socket_cap_t cap;
+ u_short type;
+ u_int flags;
+ cirrus_state_t c_state;
+} socket_info_t;
+
+/* These definitions must match the pcic table! */
+typedef enum pcic_id {
+ IS_PD6710, IS_PD672X, IS_VT83C469
+} pcic_id;
+
+typedef struct pcic_t {
+ char *name;
+} pcic_t;
+
+static pcic_t pcic[] = {
+ {" Cirrus PD6710: "},
+ {" Cirrus PD672x: "},
+ {" VIA VT83C469: "},
+};
+
+static socket_info_t socket;
+static socket_state_t state;
+static struct pccard_mem_map mem;
+static struct pccard_io_map io;
+
+/*====================================================================*/
+
+/* Some PCI shortcuts */
+
+static int pci_readb (socket_info_t * s, int r, u_char * v)
{
- pci_dev_t devno;
- int idx = 0; /* general index */
- ulong membaseCsr; /* base address of device memory space */
+ return pci_read_config_byte (s->dev, r, v);
+}
+static int pci_writeb (socket_info_t * s, int r, u_char v)
+{
+ return pci_write_config_byte (s->dev, r, v);
+}
+static int pci_readw (socket_info_t * s, int r, u_short * v)
+{
+ return pci_read_config_word (s->dev, r, v);
+}
+static int pci_writew (socket_info_t * s, int r, u_short v)
+{
+ return pci_write_config_word (s->dev, r, v);
+}
- /* find PD67290 device */
- if ((devno = pci_find_devices (supported, idx++)) < 0) {
- printf ("No PD67290 device found !!\n");
+/*====================================================================*/
+
+#define cb_readb(s) readb((s)->cb_phys + 1)
+#define cb_writeb(s, v) writeb(v, (s)->cb_phys)
+#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
+#define cb_readl(s, r) readl((s)->cb_phys + (r))
+#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
+
+
+static u_char i365_get (socket_info_t * s, u_short reg)
+{
+ u_char val;
+#ifdef CONFIG_PCMCIA_SLOT_A
+ int slot = 0;
+#else
+ int slot = 1;
+#endif
+
+ val = I365_REG (slot, reg);
+
+ cb_writeb (s, val);
+ val = cb_readb (s);
+
+ debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
+ return val;
+}
+
+static void i365_set (socket_info_t * s, u_short reg, u_char data)
+{
+#ifdef CONFIG_PCMCIA_SLOT_A
+ int slot = 0;
+#else
+ int slot = 1;
+#endif
+ u_char val;
+
+ val = I365_REG (slot, reg);
+
+ cb_writeb (s, val);
+ cb_writeb2 (s, data);
+
+ debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
+}
+
+static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
+{
+ i365_set (s, reg, i365_get (s, reg) | mask);
+}
+
+static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
+{
+ i365_set (s, reg, i365_get (s, reg) & ~mask);
+}
+
+#if 0 /* not used */
+static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
+{
+ u_char d = i365_get (s, reg);
+
+ i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
+}
+
+static u_short i365_get_pair (socket_info_t * s, u_short reg)
+{
+ return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
+}
+#endif /* not used */
+
+static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
+{
+ i365_set (s, reg, data & 0xff);
+ i365_set (s, reg + 1, data >> 8);
+}
+
+/*======================================================================
+
+ Code to save and restore global state information for Cirrus
+ PD67xx controllers, and to set and report global configuration
+ options.
+
+======================================================================*/
+
+#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
+
+static void cirrus_get_state (socket_info_t * s)
+{
+ int i;
+ cirrus_state_t *p = &s->c_state;
+
+ p->misc1 = i365_get (s, PD67_MISC_CTL_1);
+ p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
+ p->misc2 = i365_get (s, PD67_MISC_CTL_2);
+ for (i = 0; i < 6; i++)
+ p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
+
+}
+
+static void cirrus_set_state (socket_info_t * s)
+{
+ int i;
+ u_char misc;
+ cirrus_state_t *p = &s->c_state;
+
+ misc = i365_get (s, PD67_MISC_CTL_2);
+ i365_set (s, PD67_MISC_CTL_2, p->misc2);
+ if (misc & PD67_MC2_SUSPEND)
+ udelay (50000);
+ misc = i365_get (s, PD67_MISC_CTL_1);
+ misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
+ i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
+ for (i = 0; i < 6; i++)
+ i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
+}
+
+static u_int cirrus_set_opts (socket_info_t * s)
+{
+ cirrus_state_t *p = &s->c_state;
+ u_int mask = 0xffff;
+#if DEBUG
+ char buf[200];
+
+ memset (buf, 0, 200);
+#endif
+
+ if (has_ring == -1)
+ has_ring = 1;
+ flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
+ flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
+#if DEBUG
+ if (p->misc2 & PD67_MC2_IRQ15_RI)
+ strcat (buf, " [ring]");
+ if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
+ strcat (buf, " [dyn mode]");
+ if (p->misc1 & PD67_MC1_INPACK_ENA)
+ strcat (buf, " [inpack]");
+#endif
+
+ if (p->misc2 & PD67_MC2_IRQ15_RI)
+ mask &= ~0x8000;
+ if (has_led > 0) {
+#if DEBUG
+ strcat (buf, " [led]");
+#endif
+ mask &= ~0x1000;
+ }
+ if (has_dma > 0) {
+#if DEBUG
+ strcat (buf, " [dma]");
+#endif
+ mask &= ~0x0600;
+ flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
+#if DEBUG
+ if (p->misc2 & PD67_MC2_FREQ_BYPASS)
+ strcat (buf, " [freq bypass]");
+#endif
+ }
+
+ if (setup_time >= 0)
+ p->timer[0] = p->timer[3] = setup_time;
+ if (cmd_time > 0) {
+ p->timer[1] = cmd_time;
+ p->timer[4] = cmd_time * 2 + 4;
+ }
+ if (p->timer[1] == 0) {
+ p->timer[1] = 6;
+ p->timer[4] = 16;
+ if (p->timer[0] == 0)
+ p->timer[0] = p->timer[3] = 1;
+ }
+ if (recov_time >= 0)
+ p->timer[2] = p->timer[5] = recov_time;
+
+ debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
+ buf,
+ p->timer[0], p->timer[1], p->timer[2],
+ p->timer[3], p->timer[4], p->timer[5]);
+
+ return mask;
+}
+
+/*======================================================================
+
+ Routines to handle common CardBus options
+
+======================================================================*/
+
+/* Default settings for PCI command configuration register */
+#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
+ PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
+
+static void cb_get_state (socket_info_t * s)
+{
+ pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
+ pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
+ pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
+ pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
+ pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
+ pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
+}
+
+static void cb_set_state (socket_info_t * s)
+{
+ pci_writew (s, PCI_COMMAND, CMD_DFLT);
+ pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
+ pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
+ pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
+ pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
+ pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
+ pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
+}
+
+static void cb_set_opts (socket_info_t * s)
+{
+}
+
+/*======================================================================
+
+ Power control for Cardbus controllers: used both for 16-bit and
+ Cardbus cards.
+
+======================================================================*/
+
+static int cb_set_power (socket_info_t * s, socket_state_t * state)
+{
+ u_int reg = 0;
+
+ reg = I365_PWR_NORESET;
+ if (state->flags & SS_PWR_AUTO)
+ reg |= I365_PWR_AUTO;
+ if (state->flags & SS_OUTPUT_ENA)
+ reg |= I365_PWR_OUT;
+ if (state->Vpp != 0) {
+ if (state->Vpp == 120) {
+ reg |= I365_VPP1_12V;
+ puts (" 12V card found: ");
+ } else if (state->Vpp == state->Vcc) {
+ reg |= I365_VPP1_5V;
+ } else {
+ puts (" power not found: ");
+ return -1;
+ }
+ }
+ if (state->Vcc != 0) {
+ reg |= I365_VCC_5V;
+ if (state->Vcc == 33) {
+ puts (" 3.3V card found: ");
+ i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+ } else if (state->Vcc == 50) {
+ puts (" 5V card found: ");
+ i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+ } else {
+ puts (" power not found: ");
+ return -1;
+ }
+ }
+
+ if (reg != i365_get (s, I365_POWER)) {
+ reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
+ i365_set (s, I365_POWER, reg);
+ }
+
+ return 0;
+}
+
+/*======================================================================
+
+ Generic routines to get and set controller options
+
+======================================================================*/
+
+static void get_bridge_state (socket_info_t * s)
+{
+ cirrus_get_state (s);
+ cb_get_state (s);
+}
+
+static void set_bridge_state (socket_info_t * s)
+{
+ cb_set_state (s);
+ i365_set (s, I365_GBLCTL, 0x00);
+ i365_set (s, I365_GENCTL, 0x00);
+ cirrus_set_state (s);
+}
+
+static void set_bridge_opts (socket_info_t * s)
+{
+ cirrus_set_opts (s);
+ cb_set_opts (s);
+}
+
+/*====================================================================*/
+#define PD67_EXT_INDEX 0x2e /* Extension index */
+#define PD67_EXT_DATA 0x2f /* Extension data */
+#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
+
+#define pd67_ext_get(s, r) \
+ (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
+
+static int i365_get_status (socket_info_t * s, u_int * value)
+{
+ u_int status;
+ u_char val;
+ u_char power, vcc, vpp;
+ u_int powerstate;
+
+ status = i365_get (s, I365_IDENT);
+ status = i365_get (s, I365_STATUS);
+ *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
+ if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
+ *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
+ } else {
+ *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
+ *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
+ }
+ *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
+ *value |= (status & I365_CS_READY) ? SS_READY : 0;
+ *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
+
+ /* Check for Cirrus CL-PD67xx chips */
+ i365_set (s, PD67_CHIP_INFO, 0);
+ val = i365_get (s, PD67_CHIP_INFO);
+ s->type = -1;
+ if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
+ val = i365_get (s, PD67_CHIP_INFO);
+ if ((val & PD67_INFO_CHIP_ID) == 0) {
+ s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
+ i365_set (s, PD67_EXT_INDEX, 0xe5);
+ if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
+ s->type = IS_VT83C469;
+ }
+ } else {
+ printf ("no Cirrus Chip found\n");
+ *value = 0;
return -1;
}
- /* - 0xfe000000 see MPC 8245 Users Manual Adress Map B */
- membaseCsr = PCMCIA_IO_BASE - 0xfe000000;
+
+ power = i365_get (s, I365_POWER);
+ state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
+ state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
+ vcc = power & I365_VCC_MASK;
+ vpp = power & I365_VPP1_MASK;
+ state.Vcc = state.Vpp = 0;
+ if((vcc== 0) || (vpp == 0)) {
+ /*
+ * On the Cirrus we get the info which card voltage
+ * we have in EXTERN DATA and write it to MISC_CTL1
+ */
+ powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
+ if (powerstate & PD67_EXD_VS1(0)) {
+ /* 5V Card */
+ i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+ } else {
+ /* 3.3V Card */
+ i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+ }
+ i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
+ power = i365_get (s, I365_POWER);
+ }
+ if (power & I365_VCC_5V) {
+ state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
+ }
+
+ if (power == I365_VPP1_12V)
+ state.Vpp = 120;
+
+ /* IO card, RESET flags, IO interrupt */
+ power = i365_get (s, I365_INTCTL);
+ state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
+ if (power & I365_PC_IOCARD)
+ state.flags |= SS_IOCARD;
+ state.io_irq = power & I365_IRQ_MASK;
+
+ /* Card status change mask */
+ power = i365_get (s, I365_CSCINT);
+ state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
+ if (state.flags & SS_IOCARD)
+ state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
+ else {
+ state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
+ state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
+ state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
+ }
+ debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
+ "io_irq %d, csc_mask %#2.2x\n", state.flags,
+ state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
+
+ return 0;
+} /* i365_get_status */
+
+static int i365_set_socket (socket_info_t * s, socket_state_t * state)
+{
+ u_char reg;
+
+ set_bridge_state (s);
+
+ /* IO card, RESET flag */
+ reg = 0;
+ reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
+ reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
+ i365_set (s, I365_INTCTL, reg);
+
+ cb_set_power (s, state);
+
+#if 0
+ /* Card status change interrupt mask */
+ reg = s->cs_irq << 4;
+ if (state->csc_mask & SS_DETECT)
+ reg |= I365_CSC_DETECT;
+ if (state->flags & SS_IOCARD) {
+ if (state->csc_mask & SS_STSCHG)
+ reg |= I365_CSC_STSCHG;
+ } else {
+ if (state->csc_mask & SS_BATDEAD)
+ reg |= I365_CSC_BVD1;
+ if (state->csc_mask & SS_BATWARN)
+ reg |= I365_CSC_BVD2;
+ if (state->csc_mask & SS_READY)
+ reg |= I365_CSC_READY;
+ }
+ i365_set (s, I365_CSCINT, reg);
+ i365_get (s, I365_CSC);
+#endif /* 0 */
+
+ return 0;
+} /* i365_set_socket */
+
+/*====================================================================*/
+
+static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
+{
+ u_short base, i;
+ u_char map;
+
+ debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
+ mem->map, mem->flags, mem->speed,
+ mem->sys_start, mem->sys_stop, mem->card_start);
+
+ map = mem->map;
+ if ((map > 4) ||
+ (mem->card_start > 0x3ffffff) ||
+ (mem->sys_start > mem->sys_stop) ||
+ (mem->speed > 1000)) {
+ return -1;
+ }
+
+ /* Turn off the window before changing anything */
+ if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
+ i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
+
+ /* Take care of high byte, for PCI controllers */
+ i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
+
+ base = I365_MEM (map);
+ i = (mem->sys_start >> 12) & 0x0fff;
+ if (mem->flags & MAP_16BIT)
+ i |= I365_MEM_16BIT;
+ if (mem->flags & MAP_0WS)
+ i |= I365_MEM_0WS;
+ i365_set_pair (s, base + I365_W_START, i);
+
+ i = (mem->sys_stop >> 12) & 0x0fff;
+ switch (mem->speed / CYCLE_TIME) {
+ case 0:
+ break;
+ case 1:
+ i |= I365_MEM_WS0;
+ break;
+ case 2:
+ i |= I365_MEM_WS1;
+ break;
+ default:
+ i |= I365_MEM_WS1 | I365_MEM_WS0;
+ break;
+ }
+ i365_set_pair (s, base + I365_W_STOP, i);
+
+ i = 0;
+ if (mem->flags & MAP_WRPROT)
+ i |= I365_MEM_WRPROT;
+ if (mem->flags & MAP_ATTRIB)
+ i |= I365_MEM_REG;
+ i365_set_pair (s, base + I365_W_OFF, i);
+
+ /* set System Memory map Upper Adress */
+ i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
+ i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
+
+ /* Turn on the window if necessary */
+ if (mem->flags & MAP_ACTIVE)
+ i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
+ return 0;
+} /* i365_set_mem_map */
+
+static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
+{
+ u_char map, ioctl;
+
+ map = io->map;
+ /* comment out: comparison is always false due to limited range of data type */
+ if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
+ (io->stop < io->start))
+ return -1;
+ /* Turn off the window before changing anything */
+ if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
+ i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
+ i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
+ i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
+ ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
+ if (io->speed)
+ ioctl |= I365_IOCTL_WAIT (map);
+ if (io->flags & MAP_0WS)
+ ioctl |= I365_IOCTL_0WS (map);
+ if (io->flags & MAP_16BIT)
+ ioctl |= I365_IOCTL_16BIT (map);
+ if (io->flags & MAP_AUTOSZ)
+ ioctl |= I365_IOCTL_IOCS16 (map);
+ i365_set (s, I365_IOCTL, ioctl);
+ /* Turn on the window if necessary */
+ if (io->flags & MAP_ACTIVE)
+ i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
+ return 0;
+} /* i365_set_io_map */
+
+/*====================================================================*/
+
+/*
+ * PCI_ADDR = (HOST_ADDR - 0xfe000000)
+ * see MPC 8245 Users Manual Adress Map B
+ */
+#define HOST_TO_PCI(addr) ((addr) - 0xfe000000)
+#define PCI_TO_HOST(addr) ((addr) + 0xfe000000)
+
+int i82365_init (void)
+{
+ u_int val;
+ int i;
+
+ if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
+ /* Controller not found */
+ printf ("No PD67290 device found !!\n");
+ return 1;
+ }
+ debug ("i82365 Device Found!\n");
+
+ socket.cb_phys = PCMCIA_IO_BASE;
/* set base address */
- pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, membaseCsr);
+ pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0,
+ HOST_TO_PCI(socket.cb_phys));
/* enable mapped memory and IO addresses */
- pci_write_config_dword (devno,
+ pci_write_config_dword (socket.dev,
PCI_COMMAND,
PCI_COMMAND_MEMORY |
PCI_COMMAND_IO | PCI_COMMAND_WAIT);
+
+ get_bridge_state (&socket);
+ set_bridge_opts (&socket);
+
+ i = i365_get_status (&socket, &val);
+
+ if (i > -1) {
+ puts (pcic[socket.type].name);
+ } else {
+ printf ("i82365: Controller not found.\n");
+ return 1;
+ }
+ if((val & SS_DETECT) != SS_DETECT){
+ puts ("No card\n");
+ return 1;
+ }
+
+ state.flags |= SS_OUTPUT_ENA;
+
+ i365_set_socket (&socket, &state);
+
+ for (i = 500; i; i--) {
+ if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
+ break;
+ udelay (1000);
+ }
+
+ if (i == 0) {
+ /* PC Card not ready for data transfer */
+ puts ("i82365 PC Card not ready for data transfer\n");
+ return 1;
+ }
+ debug (" PC Card ready for data transfer: ");
+
+ mem.map = 0;
+ mem.flags = MAP_ATTRIB | MAP_ACTIVE;
+ mem.speed = 300;
+ mem.sys_start = CFG_PCMCIA_MEM_ADDR;
+ mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
+ mem.card_start = 0;
+ i365_set_mem_map (&socket, &mem);
+
+ mem.map = 1;
+ mem.flags = MAP_ACTIVE;
+ mem.speed = 300;
+ mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE;
+ mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1;
+ mem.card_start = 0;
+ i365_set_mem_map (&socket, &mem);
+
+#ifdef DEBUG
+ i82365_dump_regions (socket.dev);
+#endif
+
return 0;
}
+
+void i82365_exit (void)
+{
+ io.map = 0;
+ io.flags = 0;
+ io.speed = 0;
+ io.start = 0;
+ io.stop = 0x1;
+
+ i365_set_io_map (&socket, &io);
+
+ mem.map = 0;
+ mem.flags = 0;
+ mem.speed = 0;
+ mem.sys_start = 0;
+ mem.sys_stop = 0x1000;
+ mem.card_start = 0;
+
+ i365_set_mem_map (&socket, &mem);
+
+ mem.map = 1;
+ mem.flags = 0;
+ mem.speed = 0;
+ mem.sys_start = 0;
+ mem.sys_stop = 0x1000;
+ mem.card_start = 0;
+
+ i365_set_mem_map (&socket, &mem);
+
+ state.Vcc = state.Vpp = 0;
+
+ i365_set_socket (&socket, &state);
+}
+
+int pcmcia_on (void)
+{
+ u_int rc;
+
+ debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ rc = i82365_init();
+ if (rc)
+ goto exit;
+
+ rc = check_ide_device(0);
+ if (rc == 0)
+ goto exit;
+
+ i82365_exit();
+
+exit:
+ return rc;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+ printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ i82365_exit();
+
+ return 0;
+}
+#endif
+
+/*======================================================================
+
+ Debug stuff
+
+======================================================================*/
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev)
+{
+ u_int tmp[2];
+ u_int *mem = (void *) socket.cb_phys;
+ u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
+ u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
+
+ pci_read_config_dword (dev, 0x00, tmp + 0);
+ pci_read_config_dword (dev, 0x80, tmp + 1);
+
+ printf ("PCI CONF: %08X ... %08X\n",
+ tmp[0], tmp[1]);
+ printf ("PCI MEM: ... %08X ... %08X\n",
+ mem[0x8 / 4], mem[0x800 / 4]);
+ printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
+ cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
+ cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
+ printf ("CIS CONF: %02X %02X %02X ...\n",
+ cis[0x200], cis[0x202], cis[0x204]);
+ printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
+ ide[0], ide[1], ide[2], ide[3],
+ ide[4], ide[5], ide[6], ide[7]);
+}
+#endif /* DEBUG */
+
+#endif /* CONFIG_I82365 */
diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
index 8363d86..e8c2614 100644
--- a/board/cpu87/cpu87.c
+++ b/board/cpu87/cpu87.c
@@ -197,7 +197,7 @@
*/
int checkboard (void)
{
- printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV);
+ printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
return 0;
}
@@ -280,7 +280,7 @@
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifndef CFG_RAMBOOT
- ulong size8, size9;
+ ulong size8, size9, size10;
#endif
long psize;
@@ -294,17 +294,25 @@
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
+
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
-
- if (size8 < size9) {
- psize = size9;
- printf ("(60x:9COL) ");
- } else {
+
+ size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
+ (uchar *) CFG_SDRAM_BASE);
+
+ psize = max(size8,max(size9,size10));
+
+ if (psize == size8) {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:8COL) ");
- }
+ } else if (psize == size9){
+ psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+ (uchar *) CFG_SDRAM_BASE);
+ printf ("(60x:9COL) ");
+ } else
+ printf ("(60x:10COL) ");
#endif /* CFG_RAMBOOT */
diff --git a/board/etin/kvme080/Makefile b/board/etin/kvme080/Makefile
new file mode 100644
index 0000000..303ccfa
--- /dev/null
+++ b/board/etin/kvme080/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o multiverse.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/etin/kvme080/config.mk b/board/etin/kvme080/config.mk
new file mode 100644
index 0000000..45abdc0
--- /dev/null
+++ b/board/etin/kvme080/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2005
+# Sangmoon, Etin Systems, dogoil@etinsys.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# KVME080 board
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c
new file mode 100644
index 0000000..de62fa0
--- /dev/null
+++ b/board/etin/kvme080/kvme080.c
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts ("Board: KVME080\n");
+ return 0;
+}
+
+unsigned long setdram(int m, int row, int col, int bank)
+{
+ int i;
+ unsigned long start, end;
+ uint32_t mccr1;
+ uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+ uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+ uint8_t mber = 0;
+
+ CONFIG_READ_WORD(MCCR1, mccr1);
+ mccr1 &= 0xffff0000;
+
+ start = CFG_SDRAM_BASE;
+ end = start + (1 << (col + row + 3) ) * bank - 1;
+
+ for (i = 0; i < m; i++) {
+ mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+ if (i < 4) {
+ msar1 |= ((start >> 20) & 0xff) << i * 8;
+ emsar1 |= ((start >> 28) & 0xff) << i * 8;
+ mear1 |= ((end >> 20) & 0xff) << i * 8;
+ emear1 |= ((end >> 28) & 0xff) << i * 8;
+ } else {
+ msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
+ emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+ mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
+ emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+ }
+ mber |= 1 << i;
+ start += (1 << (col + row + 3) ) * bank;
+ end += (1 << (col + row + 3) ) * bank;
+ }
+ for (; i < 8; i++) {
+ if (i < 4) {
+ msar1 |= 0xff << i * 8;
+ emsar1 |= 0x30 << i * 8;
+ mear1 |= 0xff << i * 8;
+ emear1 |= 0x30 << i * 8;
+ } else {
+ msar2 |= 0xff << (i-4) * 8;
+ emsar2 |= 0x30 << (i-4) * 8;
+ mear2 |= 0xff << (i-4) * 8;
+ emear2 |= 0x30 << (i-4) * 8;
+ }
+ }
+
+ CONFIG_WRITE_WORD(MCCR1, mccr1);
+ CONFIG_WRITE_WORD(MSAR1, msar1);
+ CONFIG_WRITE_WORD(EMSAR1, emsar1);
+ CONFIG_WRITE_WORD(MEAR1, mear1);
+ CONFIG_WRITE_WORD(EMEAR1, emear1);
+ CONFIG_WRITE_WORD(MSAR2, msar2);
+ CONFIG_WRITE_WORD(EMSAR2, emsar2);
+ CONFIG_WRITE_WORD(MEAR2, mear2);
+ CONFIG_WRITE_WORD(EMEAR2, emear2);
+ CONFIG_WRITE_BYTE(MBER, mber);
+
+ return (1 << (col + row + 3) ) * bank * m;
+}
+
+long int initdram(int board_type)
+{
+ unsigned int msr;
+ long int size = 0;
+
+ msr = mfmsr();
+ mtmsr(msr & ~(MSR_IR | MSR_DR));
+ mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
+ mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
+ mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
+ mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
+ mtmsr(msr);
+
+ if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
+ size = 0x20000000; /* 512MB */
+ else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+ size = 0x10000000; /* 256MB */
+ else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+ size = 0x10000000; /* 256MB */
+ else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+ size = 0x08000000; /* 128MB */
+ else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+ size = 0x08000000; /* 128MB */
+ else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
+ size = 0x04000000; /* 64MB */
+
+ msr = mfmsr();
+ mtmsr(msr & ~(MSR_IR | MSR_DR));
+ mtspr(IBAT2L, CFG_IBAT2L);
+ mtspr(IBAT2U, CFG_IBAT2U);
+ mtspr(DBAT2L, CFG_DBAT2L);
+ mtspr(DBAT2U, CFG_DBAT2U);
+ mtmsr(msr);
+
+ return size;
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+ pci_mpc824x_init(&hose);
+}
+
+int board_early_init_f(void)
+{
+ *(volatile unsigned char *)(0xff080120) = 0xfb;
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ unsigned int msr;
+
+ CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
+ CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
+ CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
+
+ msr = mfmsr();
+ mtmsr(msr & ~(MSR_IR | MSR_DR));
+ mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+ mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+ mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+ mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+ mtmsr(msr);
+
+ return 0;
+}
+
+extern int multiverse_init(void);
+
+int misc_init_r(void)
+{
+ multiverse_init();
+ return 0;
+}
+
+void *nvram_read(void *dest, const long src, size_t count)
+{
+ volatile uchar *d = (volatile uchar*) dest;
+ volatile uchar *s = (volatile uchar*) src;
+ while(count--) {
+ *d++ = *s++;
+ asm volatile("sync");
+ }
+ return dest;
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+ volatile uchar *d = (volatile uchar*)dest;
+ volatile uchar *s = (volatile uchar*)src;
+ while(count--) {
+ *d++ = *s++;
+ asm volatile("sync");
+ }
+}
diff --git a/board/etin/kvme080/multiverse.c b/board/etin/kvme080/multiverse.c
new file mode 100644
index 0000000..eb89581
--- /dev/null
+++ b/board/etin/kvme080/multiverse.c
@@ -0,0 +1,186 @@
+/*
+ * multiverse.c
+ *
+ * VME driver for Multiverse
+ *
+ * Author : Sangmoon Kim
+ * dogoil@etinsys.com
+ *
+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "multiverse.h"
+
+static unsigned long vme_asi_addr;
+static unsigned long vme_iack_addr;
+static unsigned long pci_reg_addr;
+static unsigned long vme_reg_addr;
+
+int multiv_reset(unsigned long base)
+{
+ writeb(0x09, base + VME_SLAVE32_AM);
+ writeb(0x39, base + VME_SLAVE24_AM);
+ writeb(0x29, base + VME_SLAVE16_AM);
+ writeb(0x2f, base + VME_SLAVE_REG_AM);
+ writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
+ writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
+ writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
+#ifdef A32_SLV_WINDOW
+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+ writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
+ base + VME_SLAVE32_MASK);
+ writeb(0x01, base + VME_SLAVE32_EN);
+ } else {
+ writeb(0xff, base + VME_SLAVE32_MASK);
+ writeb(0x00, base + VME_SLAVE32_EN);
+ }
+#else
+ writeb(0xff, base + VME_SLAVE32_MASK);
+ writeb(0x00, base + VME_SLAVE32_EN);
+#endif
+#ifdef A24_SLV_WINDOW
+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+ writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
+ base + VME_SLAVE24_MASK);
+ writeb(0x01, base + VME_SLAVE24_EN);
+ } else {
+ writeb(0xff, base + VME_SLAVE24_MASK);
+ writeb(0x00, base + VME_SLAVE24_EN);
+ }
+#else
+ writeb(0xff, base + VME_SLAVE24_MASK);
+ writeb(0x00, base + VME_SLAVE24_EN);
+#endif
+#ifdef A16_SLV_WINDOW
+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+ writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
+ base + VME_SLAVE16_MASK);
+ writeb(0x01, base + VME_SLAVE16_EN);
+ } else {
+ writeb(0xff, base + VME_SLAVE16_MASK);
+ writeb(0x00, base + VME_SLAVE16_EN);
+ }
+#else
+ writeb(0xff, base + VME_SLAVE16_MASK);
+ writeb(0x00, base + VME_SLAVE16_EN);
+#endif
+#ifdef REG_SLV_WINDOW
+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+ writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
+ base + VME_SLAVE_REG_MASK);
+ writeb(0x01, base + VME_SLAVE_REG_EN);
+ } else {
+ writeb(0xf8, base + VME_SLAVE_REG_MASK);
+ }
+#else
+ writeb(0xf8, base + VME_SLAVE_REG_MASK);
+#endif
+ writeb(0x09, base + VME_MASTER32_AM);
+ writeb(0x39, base + VME_MASTER24_AM);
+ writeb(0x29, base + VME_MASTER16_AM);
+ writeb(0x2f, base + VME_MASTER_REG_AM);
+ writel(0x00000000, base + VME_RMW_ADRS);
+ writeb(0x00, base + VME_IRQ);
+ writeb(0x00, base + VME_INT_EN);
+ writel(0x00000000, base + VME_IRQ1_REG);
+ writel(0x00000000, base + VME_IRQ2_REG);
+ writel(0x00000000, base + VME_IRQ3_REG);
+ writel(0x00000000, base + VME_IRQ4_REG);
+ writel(0x00000000, base + VME_IRQ5_REG);
+ writel(0x00000000, base + VME_IRQ6_REG);
+ writel(0x00000000, base + VME_IRQ7_REG);
+ return 0;
+}
+
+void multiv_auto_slot_id(unsigned long base)
+{
+ unsigned int vector;
+ int slot_id = 1;
+ if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
+ *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
+ writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
+ writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
+ base + VME_CTRL);
+ while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+ while (readb(base + VME_INT) & 0x04) {
+ vector = *(volatile unsigned int*)
+ (vme_iack_addr + VME_IACK2);
+ *(unsigned char*)(vme_asi_addr + 0x7ffff)
+ = (slot_id << 3) & 0xff;
+ slot_id ++;
+ if (slot_id > 31)
+ break;
+ }
+ }
+ }
+}
+
+int multiverse_init(void)
+{
+ int i;
+ pci_dev_t pdev;
+ unsigned int bar[6];
+
+ pdev = pci_find_device(0x1895, 0x0001, 0);
+
+ if (pdev == 0)
+ return -1;
+
+ for (i = 0; i < 6; i++)
+ pci_read_config_dword (pdev,
+ PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
+
+ pci_reg_addr = bar[0];
+ vme_reg_addr = bar[1] + 0x00F00000;
+ vme_iack_addr = bar[1] + 0x00200000;
+ vme_asi_addr = bar[3];
+
+ pci_write_config_dword (pdev, PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ writel(0xFF000000, pci_reg_addr + P_TA1);
+ writel(0x04, pci_reg_addr + P_IMG_CTRL1);
+ writel(0xf0000000, pci_reg_addr + P_TA2);
+ writel(0x04, pci_reg_addr + P_IMG_CTRL2);
+ writel(0xF1000000, pci_reg_addr + P_TA3);
+ writel(0x04, pci_reg_addr + P_IMG_CTRL3);
+ writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
+ writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
+ writel(0x04, pci_reg_addr + P_IMG_CTRL5);
+
+ writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
+ writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
+ writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
+ writel(0x04, pci_reg_addr + W_IMG_CTRL1);
+
+ writel(0xF0000000, pci_reg_addr + W_BA2);
+ writel(0xFF000000, pci_reg_addr + W_AM2);
+ writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
+ writel(0x04, pci_reg_addr + W_IMG_CTRL2);
+
+ writel(0xFF000000, pci_reg_addr + W_BA3);
+ writel(0xFF000000, pci_reg_addr + W_AM3);
+ writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
+ writel(0x04, pci_reg_addr + W_IMG_CTRL3);
+
+ writel(0x00000001, pci_reg_addr + W_ERR_CS);
+ writel(0x00000001, pci_reg_addr + P_ERR_CS);
+
+ multiv_reset(vme_reg_addr);
+ writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
+ vme_reg_addr + VME_CTRL);
+
+ multiv_auto_slot_id(vme_reg_addr);
+
+ return 0;
+}
diff --git a/board/etin/kvme080/multiverse.h b/board/etin/kvme080/multiverse.h
new file mode 100644
index 0000000..776162d
--- /dev/null
+++ b/board/etin/kvme080/multiverse.h
@@ -0,0 +1,176 @@
+/*
+ * multiverse.h
+ *
+ * VME driver for Multiverse
+ *
+ * Author : Sangmoon Kim
+ * dogoil@etinsys.com
+ *
+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MULTIVERSE_H__
+#define __MULTIVERSE_H__
+
+#define VME_A32_MSTR_BUS 0x90000000
+#define VME_A32_MSTR_SIZE 0x01000000
+
+#define VME_A32_SLV_SIZE 0x01000000
+
+#define VME_A32_SLV_BUS 0x90000000
+#define VME_A24_SLV_BUS 0x00000000
+#define VME_A16_SLV_BUS 0x00000000
+
+#define VME_A32_SLV_LOCAL 0x00000000
+#define VME_A24_SLV_LOCAL 0x00000000
+#define VME_A16_SLV_LOCAL 0x00000000
+
+#define A32_SLV_WINDOW
+#undef A24_SLV_WINDOW
+#undef A16_SLV_WINDOW
+#undef REG_SLV_WINDOW
+
+/* PCI Registers */
+
+#define P_IMG_CTRL0 0x100
+#define P_BA0 0x104
+#define P_AM0 0x108
+#define P_TA0 0x10C
+#define P_IMG_CTRL1 0x110
+#define P_BA1 0x114
+#define P_AM1 0x118
+#define P_TA1 0x11C
+#define P_IMG_CTRL2 0x120
+#define P_BA2 0x124
+#define P_AM2 0x128
+#define P_TA2 0x12C
+#define P_IMG_CTRL3 0x130
+#define P_BA3 0x134
+#define P_AM3 0x138
+#define P_TA3 0x13C
+#define P_IMG_CTRL4 0x140
+#define P_BA4 0x144
+#define P_AM4 0x148
+#define P_TA4 0x14C
+#define P_IMG_CTRL5 0x150
+#define P_BA5 0x154
+#define P_AM5 0x158
+#define P_TA5 0x15C
+#define P_ERR_CS 0x160
+#define P_ERR_ADDR 0x164
+#define P_ERR_DATA 0x168
+
+#define WB_CONF_SPC_BAR 0x180
+#define W_IMG_CTRL1 0x184
+#define W_BA1 0x188
+#define W_AM1 0x18C
+#define W_TA1 0x190
+#define W_IMG_CTRL2 0x194
+#define W_BA2 0x198
+#define W_AM2 0x19C
+#define W_TA2 0x1A0
+#define W_IMG_CTRL3 0x1A4
+#define W_BA3 0x1A8
+#define W_AM3 0x1AC
+#define W_TA3 0x1B0
+#define W_IMG_CTRL4 0x1B4
+#define W_BA4 0x1B8
+#define W_AM4 0x1BC
+#define W_TA4 0x1C0
+#define W_IMG_CTRL5 0x1C4
+#define W_BA5 0x1C8
+#define W_AM5 0x1CC
+#define W_TA5 0x1D0
+#define W_ERR_CS 0x1D4
+#define W_ERR_ADDR 0x1D8
+#define W_ERR_DATA 0x1DC
+#define CNF_ADDR 0x1E0
+#define CNF_DATA 0x1E4
+#define INT_ACK 0x1E8
+#define ICR 0x1EC
+#define ISR 0x1F0
+
+/* VME registers */
+
+#define VME_SLAVE32_AM 0x03
+#define VME_SLAVE24_AM 0x02
+#define VME_SLAVE16_AM 0x01
+#define VME_SLAVE_REG_AM 0x00
+#define VME_SLAVE32_A 0x07
+#define VME_SLAVE24_A 0x06
+#define VME_SLAVE16_A 0x05
+#define VME_SLAVE_REG_A 0x04
+#define VME_SLAVE32_MASK 0x0B
+#define VME_SLAVE24_MASK 0x0A
+#define VME_SLAVE16_MASK 0x09
+#define VME_SLAVE_REG_MASK 0x08
+#define VME_SLAVE32_EN 0x0F
+#define VME_SLAVE24_EN 0x0E
+#define VME_SLAVE16_EN 0x0D
+#define VME_SLAVE_REG_EN 0x0C
+#define VME_MASTER32_AM 0x13
+#define VME_MASTER24_AM 0x12
+#define VME_MASTER16_AM 0x11
+#define VME_MASTER_REG_AM 0x10
+#define VME_RMW_ADRS 0x14
+#define VME_MBOX 0x18
+#define VME_STATUS 0x1E
+#define VME_CTRL 0x1C
+#define VME_IRQ 0x20
+#define VME_INT_EN 0x21
+#define VME_INT 0x22
+#define VME_IRQ1_REG 0x24
+#define VME_IRQ2_REG 0x28
+#define VME_IRQ3_REG 0x2C
+#define VME_IRQ4_REG 0x30
+#define VME_IRQ5_REG 0x34
+#define VME_IRQ6_REG 0x38
+#define VME_IRQ7_REG 0x3C
+
+/* VME control register */
+
+#define VME_CTRL_BRDRST 0x01
+#define VME_CTRL_SYSRST 0x02
+#define VME_CTRL_RMW 0x04
+#define VME_CTRL_SHORT_D 0x08
+#define VME_CTRL_SYSFAIL 0x10
+#define VME_CTRL_VOWN 0x20
+#define VME_CTRL_A16_REG_MODE 0x40
+
+/* VME status register */
+
+#define VME_STATUS_SYSCON 0x01
+#define VME_STATUS_SYSFAIL 0x02
+#define VME_STATUS_ACFAIL 0x04
+#define VME_STATUS_SYSRST 0x08
+#define VME_STATUS_VOWN 0x10
+
+/* Interrupt types */
+
+#define LVL1 0x0002
+#define LVL2 0x0004
+#define LVL3 0x0008
+#define LVL4 0x0010
+#define LVL5 0x0020
+#define LVL6 0x0040
+#define LVL7 0x0080
+#define MULTIVERSE_INTI_INT 0x0100
+#define MULTIVERSE_WB_INT 0x0200
+#define MULTIVERSE_PCI_INT 0x0400
+
+/* interrupt acknowledge */
+
+#define VME_IACK1 0x04
+#define VME_IACK2 0x08
+#define VME_IACK3 0x0c
+#define VME_IACK4 0x10
+#define VME_IACK5 0x14
+#define VME_IACK6 0x18
+#define VME_IACK7 0x1c
+
+#endif /* __MULTIVERSE_H__ */
diff --git a/board/etin/kvme080/u-boot.lds b/board/etin/kvme080/u-boot.lds
new file mode 100644
index 0000000..dda3687
--- /dev/null
+++ b/board/etin/kvme080/u-boot.lds
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2001-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc824x/start.o (.text)
+ lib_ppc/board.o (.text)
+ lib_ppc/ppcstring.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/fads/Makefile b/board/fads/Makefile
index baa6c2e..7fc88ee 100644
--- a/board/fads/Makefile
+++ b/board/fads/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o lamp.o
+OBJS = $(BOARD).o flash.o lamp.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/fads/fads.h b/board/fads/fads.h
index e981be0..41f18b5 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -467,7 +467,9 @@
#define CONFIG_ISO_PARTITION 1
#undef CONFIG_ATAPI
+#if 0 /* does not make sense when CFG_CMD_IDE is not enabled, too */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+#endif
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c
new file mode 100644
index 0000000..978c16b
--- /dev/null
+++ b/board/fads/pcmcia.c
@@ -0,0 +1,84 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#ifdef CONFIG_ADS
+#define PCMCIA_BOARD_MSG "ADS"
+#else
+#define PCMCIA_BOARD_MSG "FADS"
+#endif
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ u_long reg = 0;
+
+ switch(vpp) {
+ case 0: reg = 0; break;
+ case 50: reg = 1; break;
+ case 120: reg = 2; break;
+ default: return 1;
+ }
+
+ switch(vcc) {
+ case 0: reg = 0; break;
+#ifdef CONFIG_ADS
+ case 50: reg = BCSR1_PCCVCCON; break;
+#endif
+#ifdef CONFIG_FADS
+ case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break;
+ case 50: reg = BCSR1_PCCVCC1; break;
+#endif
+ default: return 1;
+ }
+
+ /* first, turn off all power */
+
+#ifdef CONFIG_ADS
+ *((uint *)BCSR1) |= BCSR1_PCCVCCON;
+#endif
+#ifdef CONFIG_FADS
+ *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1);
+#endif
+ *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK;
+
+ /* enable new powersettings */
+
+#ifdef CONFIG_ADS
+ *((uint *)BCSR1) &= ~reg;
+#endif
+#ifdef CONFIG_FADS
+ *((uint *)BCSR1) |= reg;
+#endif
+
+ *((uint *)BCSR1) |= reg << 20;
+
+ return 0;
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+ *((uint *)BCSR1) &= ~BCSR1_PCCEN;
+ return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ *((uint *)BCSR1) &= ~BCSR1_PCCEN;
+ return 0;
+}
+#endif /* CFG_CMD_PCMCIA */
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/gth/Makefile b/board/gth/Makefile
index e14c12e..48f74cd 100644
--- a/board/gth/Makefile
+++ b/board/gth/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ee_access.o
+OBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/gth/pcmcia.c b/board/gth/pcmcia.c
new file mode 100644
index 0000000..fce5492
--- /dev/null
+++ b/board/gth/pcmcia.c
@@ -0,0 +1,93 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH"
+
+int pcmcia_voltage_set (int slot, int vcc, int vpp)
+{ /* Do nothing */
+ return 0;
+}
+
+int pcmcia_hardware_enable (int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ debug ("hardware_enable: GTH Slot %c\n", 'A' + slot);
+
+ immap = (immap_t *) CFG_IMMR;
+ sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX (_slot_) = reg;
+ udelay (500);
+
+ /*
+ * Make sure there is a card in the slot,
+ * then configure the interface.
+ */
+ udelay (10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__, __FUNCTION__,
+ &(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & 0x98000000) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
+ (reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX (_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX (_slot_) = reg;
+
+ udelay (250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return 0;
+}
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ return 0; /* No hardware to disable */
+}
+#endif
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/gth2/config.mk b/board/gth2/config.mk
index 6d21ba1..2bc1338 100644
--- a/board/gth2/config.mk
+++ b/board/gth2/config.mk
@@ -39,4 +39,3 @@
endif
endif
endif
-
diff --git a/board/gth2/ee_access.c b/board/gth2/ee_access.c
index e293139..d4798c4 100644
--- a/board/gth2/ee_access.c
+++ b/board/gth2/ee_access.c
@@ -8,7 +8,7 @@
For documentaion, see data sheet for DS2438, 2438.pdf
By Thomas.Lange@corelatus.com 001025
-
+
Copyright (C) 2000-2005 Corelatus AB */
/* This program is free software; you can redistribute it and/or
@@ -105,7 +105,7 @@
/* Compute a new checksum with new byte, using previous checksum as input
See DS app note 17, understanding and using cyclic redundancy checks...
Also see DS2438, page 11 */
- return( crc_lookup[Old_crc ^ New_value ]);
+ return( crc_lookup[Old_crc ^ New_value ]);
}
int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
@@ -119,16 +119,16 @@
Curr_byte++;
}
E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
-
+
if(Curr_crc == Crc){
- /* Good */
+ /* Good */
return(TRUE);
}
printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
return(FALSE);
}
-static void
+static void
set_idle(void){
/* Send idle and keep start time
Continous 1 is idle */
@@ -136,7 +136,7 @@
}
-static int
+static int
do_cpu_reset(void){
/* Release reset and verify that chip responds with presence pulse */
int Retries=0;
@@ -146,10 +146,10 @@
/* Send reset */
WRITE_PORT(0);
udelay(RESET_LOW_TIME);
-
+
/* Release reset */
WRITE_PORT(1);
-
+
/* Wait for EEPROM to drive output */
udelay(PRESENCE_TIMEOUT);
if(!READ_PORT){
@@ -166,17 +166,17 @@
}
printk(KERN_ERR"eeprom did not respond when releasing reset\n");
-
+
/* Make sure chip releases pin */
udelay(PRESENCE_LOW_TIME);
/* Set to idle again */
set_idle();
-
+
return(-EIO);
}
-static u8
+static u8
read_cpu_byte(void){
/* Read a single byte from EEPROM
Read LSb first */
@@ -186,36 +186,36 @@
u32 Flags;
E_DEBUG("Reading byte\n");
-
+
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
-#ifdef __KERNEL__
- /* Disable irq */
+#ifdef __KERNEL__
+ /* Disable irq */
save_flags(Flags);
cli();
-#endif
+#endif
/* Pull down pin short time to start read
See page 26 in data sheet */
-
+
WRITE_PORT(0);
udelay(READ_LOW);
WRITE_PORT(1);
-
+
/* Wait for chip to drive pin */
udelay(READ_TIMEOUT);
-
+
Value = READ_PORT;
if(Value)
Value=1;
#ifdef __KERNEL__
- /* Enable irq */
+ /* Enable irq */
restore_flags(Flags);
#endif
-
+
/* Wait for chip to release pin */
udelay(TOTAL_READ_LOW-READ_TIMEOUT);
@@ -230,30 +230,30 @@
return(Result);
}
-static void
+static void
write_cpu_byte(u8 Byte){
/* Write a single byte to EEPROM
Write LSb first */
int i;
int Value;
u32 Flags;
-
+
E_DEBUG("Writing byte 0x%x\n",Byte);
-
+
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
Value = Byte&1;
-
+
#ifdef __KERNEL__
- /* Disable irq */
+ /* Disable irq */
save_flags(Flags);
cli();
-#endif
+#endif
/* Pull down pin short time for a 1, long time for a 0
See page 26 in data sheet */
-
+
WRITE_PORT(0);
if(Value){
/* Write a 1 */
@@ -267,54 +267,54 @@
WRITE_PORT(1);
#ifdef __KERNEL__
- /* Enable irq */
+ /* Enable irq */
restore_flags(Flags);
#endif
if(Value)
/* Wait for chip to read the 1 */
udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
-
+
/* E_DEBUG("Wrote %d\n",Value); */
Byte>>=1;
}
}
int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
- /* Execute this command string, including
+ /* Execute this command string, including
giving reset and setting to idle after command
- if Rx_len is set, we read out data from EEPROM */
+ if Rx_len is set, we read out data from EEPROM */
int i;
E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
-
+
if(do_cpu_reset()){
/* Failed! */
return(-EIO);
}
if(Send_skip)
- /* Always send SKIP_ROM first to tell chip we are sending a command,
+ /* Always send SKIP_ROM first to tell chip we are sending a command,
except when we read out rom data for chip */
write_cpu_byte(SKIP_ROM);
-
+
/* Always have Tx data */
for(i=0;i<Tx_len;i++){
write_cpu_byte(Tx[i]);
}
-
+
if(Rx_len){
for(i=0;i<Rx_len;i++){
Rx[i]=read_cpu_byte();
}
}
-
+
set_idle();
E_DEBUG("Command done\n");
return(0);
-}
+}
int ee_init_cpu_data(void){
int i;
@@ -323,7 +323,7 @@
/* Leave it floting since altera is driving the same pin */
set_idle();
- /* Copy all User EEPROM data to scratchpad */
+ /* Copy all User EEPROM data to scratchpad */
for(i=0;i<USER_PAGES;i++){
Tx[0]=RECALL_MEMORY;
Tx[1]=EE_USER_PAGE_0+i;
@@ -332,16 +332,16 @@
/* Make sure chip doesnt store measurements in NVRAM */
Tx[0]=WRITE_SCRATCHPAD;
- Tx[1]=0; /* Page */
+ Tx[1]=0; /* Page */
Tx[2]=9;
if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
Tx[0]=COPY_SCRATCHPAD;
if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
-
+
for(i=0;i<10;i++){
udelay(1000);
}
-
+
return(0);
}
diff --git a/board/gth2/ee_access.h b/board/gth2/ee_access.h
index c21730e..926199d 100644
--- a/board/gth2/ee_access.h
+++ b/board/gth2/ee_access.h
@@ -21,7 +21,7 @@
#define EE_BUSY 0x40000000
#define EE_ERROR 0x20000000
-/* Commands */
+/* Commands */
#define EE_CMD_NOP 0
#define EE_CMD_INIT_RES 1
#define EE_CMD_WR_BYTE 2
diff --git a/board/gth2/ee_dev.h b/board/gth2/ee_dev.h
index acc3418..89ef2f8 100644
--- a/board/gth2/ee_dev.h
+++ b/board/gth2/ee_dev.h
@@ -21,7 +21,7 @@
#ifndef INCeedevh
#define INCeedevh
-#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
+#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
/* MIPS */
#define WRITE_PORT(Value) write_gpio_data(Value)
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index 77fc5b4..ffeaf58 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -61,13 +61,13 @@
u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
/* Copy buffer from last run */
- memcpy(serial_log_buffer + 4096,
- serial_log_buffer,
+ memcpy(serial_log_buffer + 4096,
+ serial_log_buffer,
4096);
memset(serial_log_buffer, 0, 4096);
- *serial_log_offsetp = 4;
+ *serial_log_offsetp = 4;
}
@@ -118,7 +118,7 @@
udelay(1);
*sys_outputclr = GPIO_LEDCLK;
udelay(1);
-
+
value<<=1;
}
/* Data is enable output */
@@ -228,7 +228,7 @@
printf ("Invalid boot count %u, setting 1\n", Count);
Count = 1;
}
-
+
printf ("Boot attempt %d\n", Count);
data = (System << 8) | Count;
@@ -241,9 +241,9 @@
}
static int random_system(void){
- /* EEPROM read failed. Just try to choose one
+ /* EEPROM read failed. Just try to choose one
system release and hope it works */
-
+
/* FIXME */
return(SYSTEM_BOOT);
}
@@ -320,8 +320,8 @@
data = *addr;
system = data >> 8;
count = data & 0xFF;
- if ((system != SYSTEM_BOOT) &
- (system != SYSTEM2_BOOT) &
+ if ((system != SYSTEM_BOOT) &
+ (system != SYSTEM2_BOOT) &
(system != FAILSAFE_BOOT)) {
printf ("*** Wrong system %d\n", system);
system = FAILSAFE_BOOT;
diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S
index 62e3657..983ff70 100644
--- a/board/gth2/lowlevel_init.S
+++ b/board/gth2/lowlevel_init.S
@@ -197,11 +197,11 @@
/* RCE2 CP Altera */
li t0, MEM_STCFG2
- li t1, 0x00000280 /* BE, EW */
+ li t1, 0x00000280 /* BE, EW */
sw t1, 0(t0)
li t0, MEM_STTIME2
- li t1, 0x0303000c
+ li t1, 0x0303000c
sw t1, 0(t0)
li t0, MEM_STADDR2
@@ -210,11 +210,11 @@
/* RCE3 DP Altera */
li t0, MEM_STCFG3
- li t1, 0x00000280 /* BE, EW */
+ li t1, 0x00000280 /* BE, EW */
sw t1, 0(t0)
li t0, MEM_STTIME3
- li t1, 0x0303000c
+ li t1, 0x0303000c
sw t1, 0(t0)
li t0, MEM_STADDR3
@@ -428,14 +428,14 @@
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
mt1: lw t2, 0(t0)
- bne t0, t2, memhang
+ bne t0, t2, memhang
add t1, -1
add t0, 4
bne t1, zero, mt1
nop
nop
.globl clearmem
-clearmem:
+clearmem:
/* Clear memory */
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
@@ -445,10 +445,10 @@
bne t1, zero, mtc
nop
nop
-memtestend:
+memtestend:
j ra
nop
-
-memhang:
+
+memhang:
b memhang
nop
diff --git a/board/icu862/Makefile b/board/icu862/Makefile
index 7a2014d..7b2b545 100644
--- a/board/icu862/Makefile
+++ b/board/icu862/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c
new file mode 100644
index 0000000..20f653b
--- /dev/null
+++ b/board/icu862/pcmcia.c
@@ -0,0 +1,268 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "ICU862"
+
+static void cfg_port_B (void)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ uint reg;
+
+ immap = (immap_t *)CFG_IMMR;
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /*
+ * Configure Port B for TPS2205 PC-Card Power-Interface Switch
+ *
+ * Switch off all voltages, assert shutdown
+ */
+ reg = cp->cp_pbdat;
+ reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
+ TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */
+ TPS2205_SHDN); /* enable switch */
+ cp->cp_pbdat = reg;
+
+ cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS);
+
+ reg = cp->cp_pbdir & ~(TPS2205_INPUTS);
+ cp->cp_pbdir = reg | TPS2205_OUTPUTS;
+
+ debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
+ cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, pipr, mask;
+ int i;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */
+ cfg_port_B ();
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ pipr = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ pipr,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+ reg = cp->cp_pbdat;
+ if ((pipr & mask) == mask) {
+ reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
+ TPS2205_VCC3); /* 3V off */
+ reg &= ~(TPS2205_VCC5); /* 5V on */
+ puts (" 5.0V card found: ");
+ } else {
+ reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
+ TPS2205_VCC5); /* 5V off */
+ reg &= ~(TPS2205_VCC3); /* 3V on */
+ puts (" 3.3V card found: ");
+ }
+
+ debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n",
+ reg,
+ (reg & TPS2205_VCC3) ? "off" : "on",
+ (reg & TPS2205_VCC5) ? "off" : "on",
+ (reg & TPS2205_VPP_PGM) ? "off" : "on",
+ (reg & TPS2205_VPP_VCC) ? "off" : "on" );
+
+ cp->cp_pbdat = reg;
+
+ /* Wait 500 ms; use this to check for over-current */
+ for (i=0; i<5000; ++i) {
+ if ((cp->cp_pbdat & TPS2205_OC) == 0) {
+ printf (" *** Overcurrent - Safety shutdown ***\n");
+ cp->cp_pbdat &= ~(TPS2205_SHDN);
+ return (1);
+ }
+ udelay (100);
+ }
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+ /* Shut down */
+ cp->cp_pbdat &= ~(TPS2205_SHDN);
+
+ /* Configure PCMCIA General Control Register */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("voltage_set: "
+ PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ immap = (immap_t *)CFG_IMMR;
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn all power pins to Hi-Z
+ */
+ debug ("PCMCIA power OFF\n");
+ cfg_port_B (); /* Enables switch, but all in Hi-Z */
+
+ reg = cp->cp_pbdat;
+
+ switch(vcc) {
+ case 0: break; /* Switch off */
+ case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */
+ case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */
+ default: goto done;
+ }
+
+ /* Checking supported voltages */
+
+ debug ("PIPR: 0x%x --> %s\n",
+ pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+ cp->cp_pbdat = reg;
+
+#ifdef DEBUG
+{
+ char *s;
+
+ if ((reg & TPS2205_VCC3) == 0) {
+ s = "at 3.3V";
+ } else if ((reg & TPS2205_VCC5) == 0) {
+ s = "at 5.0V";
+ } else {
+ s = "down";
+ }
+ printf ("PCMCIA powered %s\n", s);
+}
+#endif
+
+done:
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c
new file mode 100644
index 0000000..1f61a0e
--- /dev/null
+++ b/board/kup/common/pcmcia.c
@@ -0,0 +1,225 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "KUP"
+
+#define KUP4K_PCMCIA_B_3V3 (0x00020000)
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(slot);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(2500);
+
+ /*
+ * Configure Port B pins for
+ * 3 Volts enable
+ */
+ if (slot) { /* Slot A is built-in */
+ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
+ cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
+ /* remove all power */
+ cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
+ }
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot);
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+ if ((reg & mask) == mask) {
+ puts (" 5.0V card found: NOT SUPPORTED !!!\n");
+ } else {
+ if(slot)
+ cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
+ puts (" 3.3V card found: ");
+ }
+#if 0
+ /* VCC switch error flag, PCMCIA slot INPACK_ pin */
+ cp->cp_pbdir &= ~(0x0020 | 0x0010);
+ cp->cp_pbpar &= ~(0x0020 | 0x0010);
+ udelay(500000);
+#endif
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(slot) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /* remove all power */
+ if (slot)
+ cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
+
+ /* Configure PCMCIA General Control Register */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(slot) = reg;
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("voltage_set: " \
+ PCMCIA_BOARD_MSG \
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ if (!slot) /* Slot A is not configurable */
+ return 0;
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(500);
+
+ debug ("PCMCIA power OFF\n");
+ /*
+ * Configure Port B pins for
+ * 3 Volts enable
+ */
+ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
+ cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
+ /* remove all power */
+ cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
+
+ switch(vcc) {
+ case 0: break;
+ case 33:
+ cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
+ debug ("PCMCIA powered at 3.3V\n");
+ break;
+ case 50:
+ debug ("PCMCIA: 5Volt vcc not supported\n");
+ break;
+ default:
+ puts("PCMCIA: vcc not supported");
+ break;
+ }
+ udelay(10000);
+ /* Checking supported voltages */
+
+ debug ("PIPR: 0x%x --> %s\n",
+ pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
+ ? "only 5 V --> NOT SUPPORTED"
+ : "can do 3.3V");
+
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile
index 62d289b..4a3954c 100644
--- a/board/kup/kup4k/Makefile
+++ b/board/kup/kup4k/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o
+OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile
index 62d289b..4a3954c 100644
--- a/board/kup/kup4x/Makefile
+++ b/board/kup/kup4x/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o
+OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile
index 7a2014d..7b2b545 100644
--- a/board/lwmon/Makefile
+++ b/board/lwmon/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c
new file mode 100644
index 0000000..2349286
--- /dev/null
+++ b/board/lwmon/pcmcia.c
@@ -0,0 +1,240 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+#include <i2c.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "LWMON"
+
+/* #define's for MAX1604 Power Switch */
+#define MAX1604_OP_SUS 0x80
+#define MAX1604_VCCBON 0x40
+#define MAX1604_VCC_35 0x20
+#define MAX1604_VCCBHIZ 0x10
+#define MAX1604_VPPBON 0x08
+#define MAX1604_VPPBPBPGM 0x04
+#define MAX1604_VPPBHIZ 0x02
+/* reserved 0x01 */
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+ uchar val;
+
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ /* Switch on PCMCIA port in PIC register 0x60 */
+ reg = pic_read (0x60);
+ debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
+ reg &= ~0x10;
+ /* reg |= 0x08; Vpp not needed */
+ pic_write (0x60, reg);
+#ifdef DEBUG
+ reg = pic_read (0x60);
+ printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
+#endif
+ udelay(10000);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+ if ((reg & mask) == mask) {
+ val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */
+ puts (" 5.0V card found: ");
+ } else {
+ val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */
+ puts (" 3.3V card found: ");
+ }
+
+ /* switch VCC on */
+ val |= MAX1604_OP_SUS | MAX1604_VCCBON;
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+
+ udelay(500000);
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+ uchar val;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+ /* remove all power, put output in high impedance state */
+ val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+
+ /* Configure PCMCIA General Control Register */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ /* Switch off PCMCIA port in PIC register 0x60 */
+ reg = pic_read (0x60);
+ debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
+ reg |= 0x10;
+ reg &= ~0x08;
+ pic_write (0x60, reg);
+#ifdef DEBUG
+ reg = pic_read (0x60);
+ printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
+#endif
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+ uchar val;
+
+ debug ("voltage_set: "
+ PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Turn off all power (switch to high impedance)
+ */
+ debug ("PCMCIA power OFF\n");
+ val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+
+ val = 0;
+ switch(vcc) {
+ case 0: break;
+ case 33: val = MAX1604_VCC_35; break;
+ case 50: break;
+ default: goto done;
+ }
+
+ /* Checking supported voltages */
+
+ debug ("PIPR: 0x%x --> %s\n",
+ pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+ i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+ if (val) {
+ debug ("PCMCIA powered at %sV\n",
+ (val & MAX1604_VCC_35) ? "3.3" : "5.0");
+ } else {
+ debug ("PCMCIA powered down\n");
+ }
+
+done:
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile
index 3e8376c..e4d1099 100644
--- a/board/mbx8xx/Makefile
+++ b/board/mbx8xx/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o vpd.o
+OBJS = $(BOARD).o flash.o vpd.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c
new file mode 100644
index 0000000..132a688
--- /dev/null
+++ b/board/mbx8xx/pcmcia.c
@@ -0,0 +1,166 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#include "csr.h"
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+/* A lot of this has been taken from the RPX code in this file it works from me.
+ I have added the voltage selection for the MBX board. */
+
+/* MBX voltage bit in control register #2 */
+#define CR2_VPP12 ((uchar)0x10)
+#define CR2_VPPVDD ((uchar)0x20)
+#define CR2_VDD5 ((uchar)0x40)
+#define CR2_VDD3 ((uchar)0x80)
+
+#define PCMCIA_BOARD_MSG "MBX860"
+
+int pcmcia_voltage_set (int slot, int vcc, int vpp)
+{
+ uchar reg = 0;
+
+ debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10);
+
+ switch (vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= CR2_VDD3;
+ break;
+ case 50:
+ reg |= CR2_VDD5;
+ break;
+ default:
+ return 1;
+ }
+
+ switch (vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if (vcc == vpp) {
+ reg |= CR2_VPPVDD;
+ } else {
+ return 1;
+ }
+ break;
+ case 120:
+ reg |= CR2_VPP12;
+ break;
+ default:
+ return 1;
+ }
+
+ /* first, turn off all power */
+ MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL);
+
+ /* enable new powersettings */
+ MBX_CSR2 |= reg;
+ debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2);
+
+ return (0);
+}
+
+int pcmcia_hardware_enable (int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n",
+ 'A' + slot);
+
+ udelay (10000);
+
+ immap = (immap_t *) CFG_IMMR;
+ sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX (_slot_) = reg;
+ udelay (500);
+
+ /* remove all power */
+ pcmcia_voltage_set (slot, 0, 0);
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+#ifndef CONFIG_HMI10
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+#else
+ if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
+#endif /* CONFIG_HMI10 */
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
+ (reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
+ (reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
+
+ if ((reg & mask) == mask) {
+ pcmcia_voltage_set (_slot_, 50, 0);
+ printf (" 5.0V card found: ");
+ } else {
+ pcmcia_voltage_set (_slot_, 33, 0);
+ printf (" 3.3V card found: ");
+ }
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX (_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX (_slot_) = reg;
+
+ udelay (250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+ }
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable (int slot)
+{
+ return 0; /* No hardware to disable */
+}
+#endif /* CFG_CMD_PCMCIA */
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk
index fa55673..a822559 100644
--- a/board/mcc200/config.mk
+++ b/board/mcc200/config.mk
@@ -26,16 +26,18 @@
#
# Valid values for TEXT_BASE are:
#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFE000000 boot low
+# 0xFC000000 boot low (standard configuration)
+# 0xFFF00000 boot high
# 0x00100000 boot from RAM (for testing only)
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
+## Standard: boot low
+TEXT_BASE = 0xFC000000
+## Boot high
+# TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
# TEXT_BASE = 0x00100000
endif
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index b9b9a71..167dc0f 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -32,7 +32,12 @@
/* #include "mt48lc8m32b2-6-7.h" */
/* One MT48LC16M32S2 for 64 MB */
-#include "mt48lc16m32s2-75.h"
+/* #include "mt48lc16m32s2-75.h" */
+#if defined (CONFIG_MCC200_SDRAM)
+#include "mt48lc16m16a2-75.h"
+#else
+#include "mt46v16m16-75.h"
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -249,7 +254,7 @@
*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
flash_protect (FLAG_PROTECT_CLEAR,
flash_info[0].start[0] + flash_info[0].size / 2,
- (flash_info[0].start[0] + flash_info[0].size) / 2 - 1,
+ (flash_info[0].start[0] - 1) + flash_info[0].size,
&flash_info[0]);
*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
}
diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S
index 6ca4d11..a74abf9 100644
--- a/board/netstar/crcek.S
+++ b/board/netstar/crcek.S
@@ -13,6 +13,7 @@
* u32 - crc32
*/
+#include <config.h>
#include "crcek.h"
/**
@@ -39,7 +40,7 @@
.macro crcuj, offset, size
mov r0, #0
ldr r1, \offset
- ldr r2, [r1]
+ ldr r2, [r1], #4
cmp r2, r0 @ no data, no problem
beq 2f
tst r2, #3 @ unaligned size
@@ -47,7 +48,6 @@
ldr r3, \size
cmp r2, r3 @ bogus size
bhi 2f
- add r1, r1, #4
do_crc32
ldr r1, [r1]
2:
@@ -55,16 +55,71 @@
.endm
.macro wait, reg
- mov \reg, #0x1000
+ mov \reg, #0x100000
3:
subs \reg, \reg, #0x1
bne 3b
-
.endm
+
.text
.globl crcek
crcek:
- b crc2_bad
+ /* Enable I-cache */
+ mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
+ mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
+ mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
+ orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
+ mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
+ mov r1, #0x00
+ mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
+ nop
+ nop
+ nop
+ nop
+
+ /* Setup clocking mode */
+ ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
+ ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
+ bic r1, r1, #(7 << 11) @ clear clock select
+ orr r1, r1, #(2 << 11) @ set synchronous scalable
+ mov r2, #0
+loop:
+ cmp r2, #1 @ this loop will wait for at least 100 cycles
+ streqh r1, [r0, #0x18] @ before issuing next request from MPU
+ add r2, r2, #1 @ on the 1st run code is loaded into I-cache
+ cmp r2, #16 @ and second run will set clocking mode
+ bne loop
+ nop
+
+ /* Setup clock dividers */
+ ldr r1, CKCTL_VAL
+ orr r1, r1, #0x2000 @ enable DSP clock
+ strh r1, [r0] @ setup clock divisors
+
+ /* Setup DPLL to generate requested freq */
+ ldr r0, DPLL1_BASE @ base of DPLL1 register
+ mov r1, #0x0010 @ set PLL_ENABLE
+ orr r1, r1, #0x2000 @ set IOB to new locking
+ orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+ orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+ strh r1, [r0] @ write
+
+locking:
+ ldrh r1, [r0] @ get DPLL value
+ tst r1, #0x01
+ beq locking @ while LOCK not set
+
+ /* Enable clock */
+ ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
+ mov r1, #(1 << 10) @ disable idle mode do not check
+ @ nWAKEUP pin, other remain active
+ strh r1, [r0, #0x04]
+ ldr r1, EN_CLK_VAL
+ strh r1, [r0, #0x08]
+ mov r1, #0x003f @ FLASH.RP not enabled in idle and
+ strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
+
+
mov r6, #0
crcuj _LOADER1_OFFSET, _LOADER_SIZE
bne crc1_bad
@@ -76,9 +131,8 @@
crc2_bad:
ldr r3, _LOADER1_OFFSET
ldr r4, _LOADER2_OFFSET
- b boot_2nd
- tst r6, #3
- beq one_is_bad @ one of them (or both) has bad crc
+ teq r6, #3
+ bne one_is_bad @ one of them (or both) has bad crc
ldr r1, [r3, #4]
ldr r2, [r4, #4]
cmp r1, r2 @ boot 2nd loader if versions differ
@@ -90,6 +144,7 @@
tst r6, #2
bne boot_2nd
@ We are doomed, so let user know.
+hell:
ldr r0, GPIO_BASE @ configure GPIO pins
ldr r1, GPIO_DIRECTION
strh r1, [r0, #0x08]
@@ -171,6 +226,15 @@
GPIO_BASE:
.word 0xfffce000
+MPU_CLKM_BASE:
+ .word 0xfffece00
+DPLL1_BASE:
+ .word 0xfffecf00
+
+CKCTL_VAL:
+ .word OMAP5910_ARM_CKCTL
+EN_CLK_VAL:
+ .word OMAP5910_ARM_EN_CLK
GPIO_DIRECTION:
.word 0x0000ffe7
diff --git a/board/netstar/crcit b/board/netstar/crcit
index 98ae42e..203645d 100755
--- a/board/netstar/crcit
+++ b/board/netstar/crcit
Binary files differ
diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c
index f6d3066..ce98e20 100644
--- a/board/netstar/crcit.c
+++ b/board/netstar/crcit.c
@@ -77,7 +77,7 @@
} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
char *endptr, *nptr = argv[2];
unsigned ver = strtoul(nptr, &endptr, 0);
- if (nptr != '\0' && endptr == '\0')
+ if (*nptr != '\0' && *endptr == '\0')
return doit(argv[3], ver);
}
fprintf(stderr, "Usage: crcit [-v version] <image>\n");
diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c
index 4b7eba1..d6b620c 100644
--- a/board/netstar/netstar.c
+++ b/board/netstar/netstar.c
@@ -27,7 +27,6 @@
int board_init(void)
{
/* arch number of NetStar board */
- /* TODO: use define from asm/mach-types.h */
gd->bd->bi_arch_number = 692;
/* adress of boot parameters */
@@ -51,15 +50,11 @@
return 0;
}
-extern void partition_flash(void);
-
int misc_init_r(void)
{
return 0;
}
-extern void nand_init(void);
-
int board_late_init(void)
{
return 0;
diff --git a/board/netstar/setup.S b/board/netstar/setup.S
index f67786d..5dacc9c 100644
--- a/board/netstar/setup.S
+++ b/board/netstar/setup.S
@@ -145,25 +145,23 @@
nop
/* Setup clocking mode */
- ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
- ldrh r1, [r0, #0x18] @ get reset status
+ ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
+ ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable
- mov r2, #0 @ set wait counter to 100 clock cycles
-
-icache_loop:
- cmp r2, #0x01
- streqh r1, [r0, #0x18]
- add r2, r2, #0x01
- cmp r2, #0x10
- bne icache_loop
+ mov r2, #0
+loop:
+ cmp r2, #1 @ this loop will wait for at least 100 cycles
+ streqh r1, [r0, #0x18] @ before issuing next request from MPU
+ add r2, r2, #1 @ on the 1st run code is loaded into I-cache
+ cmp r2, #16 @ and second run will set clocking mode
+ bne loop
nop
- /* Setup clock divisors */
- ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
+ /* Setup clock dividers */
ldr r1, _OMAP5910_ARM_CKCTL
orr r1, r1, #0x2000 @ enable DSP clock
- strh r1, [r0, #0x00] @ setup clock divisors
+ strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */
ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
@@ -186,8 +184,7 @@
ldr r1, _OMAP5910_ARM_EN_CLK
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
- @ max delayed ( 32 x CLKIN )
- strh r1, [r0, #0x0c]
+ strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
/* Configure 5910 pins functions to match our board. */
ldr r0, MUX_CONFIG_BASE
diff --git a/board/netta/Makefile b/board/netta/Makefile
index 68e2402..ee200c2 100644
--- a/board/netta/Makefile
+++ b/board/netta/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o dsp.o codec.o
+OBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c
new file mode 100644
index 0000000..a3709f7
--- /dev/null
+++ b/board/netta/pcmcia.c
@@ -0,0 +1,370 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+/* some sane bit macros */
+#define _BD(_b) (1U << (31-(_b)))
+#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b) (1U << (15-(_b)))
+#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b) (1U << (7-(_b)))
+#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b) _BD(_b)
+#define _BR(_l, _h) _BDR(_l, _h)
+
+#define PCMCIA_BOARD_MSG "NETTA"
+
+static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
+
+static void cfg_vppd(int no)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ unsigned short mask;
+
+ if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
+ return;
+
+ mask = vppd_masks[no];
+
+ immap->im_ioport.iop_papar &= ~mask;
+ immap->im_ioport.iop_paodr &= ~mask;
+ immap->im_ioport.iop_padir |= mask;
+}
+
+static void set_vppd(int no, int what)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ unsigned short mask;
+
+ if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
+ return;
+
+ mask = vppd_masks[no];
+
+ if (what)
+ immap->im_ioport.iop_padat |= mask;
+ else
+ immap->im_ioport.iop_padat &= ~mask;
+}
+
+static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
+
+static void cfg_vccd(int no)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ unsigned short mask;
+
+ if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
+ return;
+
+ mask = vccd_masks[no];
+
+ immap->im_ioport.iop_papar &= ~mask;
+ immap->im_ioport.iop_paodr &= ~mask;
+ immap->im_ioport.iop_padir |= mask;
+}
+
+static void set_vccd(int no, int what)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ unsigned short mask;
+
+ if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
+ return;
+
+ mask = vccd_masks[no];
+
+ if (what)
+ immap->im_ioport.iop_padat |= mask;
+ else
+ immap->im_ioport.iop_padat &= ~mask;
+}
+
+static const unsigned short oc_mask = _BW(8);
+
+static void cfg_oc(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ unsigned short mask = oc_mask;
+
+ immap->im_ioport.iop_pcdir &= ~mask;
+ immap->im_ioport.iop_pcso &= ~mask;
+ immap->im_ioport.iop_pcint &= ~mask;
+ immap->im_ioport.iop_pcpar &= ~mask;
+}
+
+static int get_oc(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ unsigned short mask = oc_mask;
+ int what;
+
+ what = !!(immap->im_ioport.iop_pcdat & mask);;
+ return what;
+}
+
+static const unsigned short shdn_mask = _BW(12);
+
+static void cfg_shdn(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ unsigned short mask;
+
+ mask = shdn_mask;
+
+ immap->im_ioport.iop_papar &= ~mask;
+ immap->im_ioport.iop_paodr &= ~mask;
+ immap->im_ioport.iop_padir |= mask;
+}
+
+static void set_shdn(int what)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ unsigned short mask;
+
+ mask = shdn_mask;
+
+ if (what)
+ immap->im_ioport.iop_padat |= mask;
+ else
+ immap->im_ioport.iop_padat &= ~mask;
+}
+
+static void cfg_ports (void)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+
+ immap = (immap_t *)CFG_IMMR;
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+
+ cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */
+ cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */
+ cfg_shdn();
+ cfg_oc();
+
+ /*
+ * Configure Port A for TPS2211 PC-Card Power-Interface Switch
+ *
+ * Switch off all voltages, assert shutdown
+ */
+ set_vppd(0, 1); set_vppd(1, 1);
+ set_vccd(0, 0); set_vccd(1, 0);
+ set_shdn(1);
+
+ udelay(100000);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, pipr, mask;
+ int i;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+ cfg_ports ();
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(500);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ pipr = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ pipr,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+ if ((pipr & mask) == mask) {
+ set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
+ set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */
+ puts (" 5.0V card found: ");
+ } else {
+ set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
+ set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */
+ puts (" 3.3V card found: ");
+ }
+
+ /* Wait 500 ms; use this to check for over-current */
+ for (i=0; i<5000; ++i) {
+ if (!get_oc()) {
+ printf (" *** Overcurrent - Safety shutdown ***\n");
+ set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */
+ return (1);
+ }
+ udelay (100);
+ }
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+ /* Configure PCMCIA General Control Register */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ /* All voltages off / Hi-Z */
+ set_vppd(0, 1); set_vppd(1, 1);
+ set_vccd(0, 1); set_vccd(1, 1);
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+ ushort sreg;
+
+ debug ("voltage_set: "
+ PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ immap = (immap_t *)CFG_IMMR;
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn all power pins to Hi-Z
+ */
+ debug ("PCMCIA power OFF\n");
+ cfg_ports (); /* Enables switch, but all in Hi-Z */
+
+ sreg = immap->im_ioport.iop_pcdat;
+ set_vppd(0, 1); set_vppd(1, 1);
+
+ switch(vcc) {
+ case 0:
+ break; /* Switch off */
+
+ case 33:
+ set_vccd(0, 1); set_vccd(1, 0);
+ break;
+
+ case 50:
+ set_vccd(0, 0); set_vccd(1, 1);
+ break;
+
+ default:
+ goto done;
+ }
+
+ /* Checking supported voltages */
+
+ debug ("PIPR: 0x%x --> %s\n",
+ pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+done:
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/ppmc7xx/config.mk b/board/ppmc7xx/config.mk
index bcb6c81..b5b46dc 100644
--- a/board/ppmc7xx/config.mk
+++ b/board/ppmc7xx/config.mk
@@ -1,6 +1,6 @@
#
# (C) Copyright 2005
-# Richard Danter, Wind River Systems
+# Richard Danter, Wind River Systems
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -22,11 +22,6 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
-#
-
-#
-#
-#
TEXT_BASE = 0xFFF00000
TEXT_END = 0xFFF40000
diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c
index 1cbcadc..4be6f13 100644
--- a/board/ppmc7xx/flash.c
+++ b/board/ppmc7xx/flash.c
@@ -1,10 +1,10 @@
/*
* flash.c
* -------
- *
+ *
* Flash programming routines for the Wind River PPMC 74xx/7xx
* based on flash.c from the TQM8260 board.
- *
+ *
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
@@ -27,13 +27,13 @@
{
unsigned long msr;
DWORD cmd_reset = 0x00F000F000F000F0LL;
-
+
if (flash_info[0].flash_id != FLASH_UNKNOWN) {
msr = get_msr ();
set_msr (msr | MSR_FP);
write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
-
+
set_msr (msr);
}
}
@@ -50,16 +50,16 @@
/* Enable FPU */
msr = get_msr ();
- set_msr (msr | MSR_FP);
-
+ set_msr (msr | MSR_FP);
+
/* Write auto-select command sequence */
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
-
+
/* Restore FPU */
set_msr (msr);
-
+
/* Read manufacturer ID */
flashtest = *(volatile DWORD*)baseaddr;
switch ((int)flashtest) {
@@ -70,7 +70,7 @@
info->flash_id = FLASH_MAN_FUJ;
break;
default:
- /* No, faulty or unknown flash */
+ /* No, faulty or unknown flash */
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
@@ -291,7 +291,7 @@
DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x0080008000800080LL, 0x00AA00AA00AA00AALL,
0x0055005500550055LL, 0x0030003000300030LL };
-
+
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
@@ -319,7 +319,7 @@
/* Enable FPU */
msr = get_msr();
set_msr ( msr | MSR_FP );
-
+
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -344,7 +344,7 @@
/* Restore FPU */
set_msr (msr);
-
+
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
@@ -373,7 +373,7 @@
DONE:
/* reset to read mode */
flash_reset ();
-
+
printf (" done\n");
return 0;
}
@@ -446,7 +446,7 @@
DWORD data;
DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x00A000A000A000A0LL };
-
+
for (data = 0, i = 0; i < 8; i++)
data = (data << 8) + *pdata++;
@@ -454,11 +454,11 @@
if ((*(DWORD*)dest & data) != data) {
return (2);
}
-
+
/* Enable FPU */
msr = get_msr();
set_msr( msr | MSR_FP );
-
+
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -473,7 +473,7 @@
/* Restore FPU */
set_msr(msr);
-
+
/* data polling for D7 */
start = get_timer (0);
while (*(volatile DWORD*)dest != data ) {
diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S
index e4ed7a6..99a818a 100644
--- a/board/ppmc7xx/init.S
+++ b/board/ppmc7xx/init.S
@@ -21,314 +21,314 @@
ori r4,r4,0x0000
lis r5,0xFEE0
ori r5,r5,0x0000
- lis r3,0x8000 # ADDR_00
+ lis r3,0x8000 # ADDR_00
ori r3,r3,0x0000
stwbrx r3,0,r4
- li r3,0x1057 # VENDOR
+ li r3,0x1057 # VENDOR
li r8, 0x0
sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_02
+ lis r3,0x8000 # ADDR_02
ori r3,r3,0x0002
stwbrx r3,0,r4
- li r3,0x0004 # ID
+ li r3,0x0004 # ID
li r8, 0x2
sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_04
+ lis r3,0x8000 # ADDR_04
ori r3,r3,0x0004
stwbrx r3,0,r4
- li r3,0x0006 # PCICMD
+ li r3,0x0006 # PCICMD
li r8, 0x0
sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_06
+ lis r3,0x8000 # ADDR_06
ori r3,r3,0x0006
stwbrx r3,0,r4
- li r3,0x00A0 # PCISTAT
+ li r3,0x00A0 # PCISTAT
li r8, 0x2
sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_08
+ lis r3,0x8000 # ADDR_08
ori r3,r3,0x0008
stwbrx r3,0,r4
- li r3,0x10 # REVID
+ li r3,0x10 # REVID
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_09
+ lis r3,0x8000 # ADDR_09
ori r3,r3,0x0009
stwbrx r3,0,r4
- li r3,0x00 # PROGIR
+ li r3,0x00 # PROGIR
stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_0A
+ lis r3,0x8000 # ADDR_0A
ori r3,r3,0x000A
stwbrx r3,0,r4
- li r3,0x00 # SUBCCODE
+ li r3,0x00 # SUBCCODE
stb r3,0x2(r5)
- lis r3,0x8000 # ADDR_0B
+ lis r3,0x8000 # ADDR_0B
ori r3,r3,0x000B
stwbrx r3,0,r4
- li r3,0x06 # PBCCR
+ li r3,0x06 # PBCCR
stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_0C
+ lis r3,0x8000 # ADDR_0C
ori r3,r3,0x000C
stwbrx r3,0,r4
- li r3,0x08 # PCLSR
+ li r3,0x08 # PCLSR
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_0D
+ lis r3,0x8000 # ADDR_0D
ori r3,r3,0x000D
stwbrx r3,0,r4
- li r3,0x00 # PLTR
+ li r3,0x00 # PLTR
stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_0E
+ lis r3,0x8000 # ADDR_0E
ori r3,r3,0x000E
stwbrx r3,0,r4
- li r3,0x00 # HEADTYPE
+ li r3,0x00 # HEADTYPE
stb r3,0x2(r5)
- lis r3,0x8000 # ADDR_0F
+ lis r3,0x8000 # ADDR_0F
ori r3,r3,0x000F
stwbrx r3,0,r4
- li r3,0x00 # BISTCTRL
+ li r3,0x00 # BISTCTRL
stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_10
+ lis r3,0x8000 # ADDR_10
ori r3,r3,0x0010
stwbrx r3,0,r4
- lis r3,0x0000 # LMBAR
+ lis r3,0x0000 # LMBAR
ori r3,r3,0x0008
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_14
+ lis r3,0x8000 # ADDR_14
ori r3,r3,0x0014
stwbrx r3,0,r4
- lis r3,0xF000 # PCSRBAR
+ lis r3,0xF000 # PCSRBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_3C
+ lis r3,0x8000 # ADDR_3C
ori r3,r3,0x003C
stwbrx r3,0,r4
- li r3,0x00 # ILR
+ li r3,0x00 # ILR
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_3D
+ lis r3,0x8000 # ADDR_3D
ori r3,r3,0x003D
stwbrx r3,0,r4
- li r3,0x01 # INTPIN
+ li r3,0x01 # INTPIN
stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_3E
+ lis r3,0x8000 # ADDR_3E
ori r3,r3,0x003E
stwbrx r3,0,r4
- li r3,0x00 # MIN_GNT
+ li r3,0x00 # MIN_GNT
stb r3,0x2(r5)
- lis r3,0x8000 # ADDR_3F
+ lis r3,0x8000 # ADDR_3F
ori r3,r3,0x003F
stwbrx r3,0,r4
- li r3,0x00 # MAX_LAT
+ li r3,0x00 # MAX_LAT
stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_40
+ lis r3,0x8000 # ADDR_40
ori r3,r3,0x0040
stwbrx r3,0,r4
- li r3,0x00 # BUSNB
+ li r3,0x00 # BUSNB
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_41
+ lis r3,0x8000 # ADDR_41
ori r3,r3,0x0041
stwbrx r3,0,r4
- li r3,0x00 # SBUSNB
+ li r3,0x00 # SBUSNB
stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_46
+ lis r3,0x8000 # ADDR_46
ori r3,r3,0x0046
stwbrx r3,0,r4
-# li r3,0xE080 # PCIARB
- li r3,-0x1F80 # PCIARB
+# li r3,0xE080 # PCIARB
+ li r3,-0x1F80 # PCIARB
li r8, 0x2
sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_70
+ lis r3,0x8000 # ADDR_70
ori r3,r3,0x0070
stwbrx r3,0,r4
- li r3,0x0000 # PMCR1
+ li r3,0x0000 # PMCR1
li r8, 0x0
sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_72
+ lis r3,0x8000 # ADDR_72
ori r3,r3,0x0072
stwbrx r3,0,r4
- li r3,0xC0 # PMCR2
+ li r3,0xC0 # PMCR2
stb r3,0x2(r5)
- lis r3,0x8000 # ADDR_73
+ lis r3,0x8000 # ADDR_73
ori r3,r3,0x0073
stwbrx r3,0,r4
- li r3,0xEF # ODCR
+ li r3,0xEF # ODCR
stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_74
+ lis r3,0x8000 # ADDR_74
ori r3,r3,0x0074
stwbrx r3,0,r4
- li r3,0x7D00 # CLKDCR
+ li r3,0x7D00 # CLKDCR
li r8, 0x0
sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_76
+ lis r3,0x8000 # ADDR_76
ori r3,r3,0x0076
stwbrx r3,0,r4
- li r3,0x00 # MDCR
+ li r3,0x00 # MDCR
stb r3,0x2(r5)
lis r6,0xFCE0
ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
- lis r3,0x8000 # ADDR_78
+ lis r3,0x8000 # ADDR_78
ori r3,r3,0x0078
stwbrx r3,0,r4
- lis r3,0xFCE0 # EUMBBAR
+ lis r3,0xFCE0 # EUMBBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_80
+ lis r3,0x8000 # ADDR_80
ori r3,r3,0x0080
stwbrx r3,0,r4
- lis r3,0xFFFF # MSADDR1
+ lis r3,0xFFFF # MSADDR1
ori r3,r3,0x4000
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_84
+ lis r3,0x8000 # ADDR_84
ori r3,r3,0x0084
stwbrx r3,0,r4
- lis r3,0xFFFF # MSADDR2
+ lis r3,0xFFFF # MSADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_88
+ lis r3,0x8000 # ADDR_88
ori r3,r3,0x0088
stwbrx r3,0,r4
- lis r3,0x0303 # EMSADDR1
+ lis r3,0x0303 # EMSADDR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_8C
+ lis r3,0x8000 # ADDR_8C
ori r3,r3,0x008C
stwbrx r3,0,r4
- lis r3,0x0303 # EMSADDR2
+ lis r3,0x0303 # EMSADDR2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_90
+ lis r3,0x8000 # ADDR_90
ori r3,r3,0x0090
stwbrx r3,0,r4
- lis r3,0xFFFF # EMEADDR1
+ lis r3,0xFFFF # EMEADDR1
ori r3,r3,0x7F3F
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_94
+ lis r3,0x8000 # ADDR_94
ori r3,r3,0x0094
stwbrx r3,0,r4
- lis r3,0xFFFF # EMEADDR2
+ lis r3,0xFFFF # EMEADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_98
+ lis r3,0x8000 # ADDR_98
ori r3,r3,0x0098
stwbrx r3,0,r4
- lis r3,0x0303 # EXTEMEM1
+ lis r3,0x0303 # EXTEMEM1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_9C
+ lis r3,0x8000 # ADDR_9C
ori r3,r3,0x009C
stwbrx r3,0,r4
- lis r3,0x0303 # EXTEMEM2
+ lis r3,0x0303 # EXTEMEM2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_A0
+ lis r3,0x8000 # ADDR_A0
ori r3,r3,0x00A0
stwbrx r3,0,r4
- li r3,0x03 # MEMBNKEN
+ li r3,0x03 # MEMBNKEN
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_A3
+ lis r3,0x8000 # ADDR_A3
ori r3,r3,0x00A3
stwbrx r3,0,r4
- li r3,0x00 # MEMPMODE
+ li r3,0x00 # MEMPMODE
stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_B8
+ lis r3,0x8000 # ADDR_B8
ori r3,r3,0x00B8
stwbrx r3,0,r4
- li r3,0x00 # ECCCNT
+ li r3,0x00 # ECCCNT
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_B9
+ lis r3,0x8000 # ADDR_B9
ori r3,r3,0x00B9
stwbrx r3,0,r4
- li r3,0x00 # ECCTRG
+ li r3,0x00 # ECCTRG
stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_C0
+ lis r3,0x8000 # ADDR_C0
ori r3,r3,0x00C0
stwbrx r3,0,r4
- li r3,0xFF # ERRENR1
+ li r3,0xFF # ERRENR1
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_C1
+ lis r3,0x8000 # ADDR_C1
ori r3,r3,0x00C1
stwbrx r3,0,r4
- li r3,0x00 # ERRDR1
+ li r3,0x00 # ERRDR1
stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_C3
+ lis r3,0x8000 # ADDR_C3
ori r3,r3,0x00C3
stwbrx r3,0,r4
- li r3,0x50 # IPBESR
+ li r3,0x50 # IPBESR
stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_C4
+ lis r3,0x8000 # ADDR_C4
ori r3,r3,0x00C4
stwbrx r3,0,r4
- li r3,0xBF # ERRENR2
+ li r3,0xBF # ERRENR2
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_C5
+ lis r3,0x8000 # ADDR_C5
ori r3,r3,0x00C5
stwbrx r3,0,r4
- li r3,0x00 # ERRDR2
+ li r3,0x00 # ERRDR2
stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_C7
+ lis r3,0x8000 # ADDR_C7
ori r3,r3,0x00C7
stwbrx r3,0,r4
- li r3,0x00 # PCIBESR
+ li r3,0x00 # PCIBESR
stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_C8
+ lis r3,0x8000 # ADDR_C8
ori r3,r3,0x00C8
stwbrx r3,0,r4
- lis r3,0x0000 # BERRADDR
+ lis r3,0x0000 # BERRADDR
ori r3,r3,0xE0FE
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_E0
+ lis r3,0x8000 # ADDR_E0
ori r3,r3,0x00E0
stwbrx r3,0,r4
- li r3,0xC0 # AMBOR
+ li r3,0xC0 # AMBOR
stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_F4
+ lis r3,0x8000 # ADDR_F4
ori r3,r3,0x00F4
stwbrx r3,0,r4
- lis r3,0x0000 # MCCR2
+ lis r3,0x0000 # MCCR2
ori r3,r3,0x020C
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_F8
+ lis r3,0x8000 # ADDR_F8
ori r3,r3,0x00F8
stwbrx r3,0,r4
- lis r3,0x0230 # MCCR3
+ lis r3,0x0230 # MCCR3
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_FC
+ lis r3,0x8000 # ADDR_FC
ori r3,r3,0x00FC
stwbrx r3,0,r4
- lis r3,0x2532 # MCCR4
+ lis r3,0x2532 # MCCR4
ori r3,r3,0x2220
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_F0
+ lis r3,0x8000 # ADDR_F0
ori r3,r3,0x00F0
stwbrx r3,0,r4
- lis r3,0xFFC8 # MCCR1
+ lis r3,0xFFC8 # MCCR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_A8
+ lis r3,0x8000 # ADDR_A8
ori r3,r3,0x00A8
stwbrx r3,0,r4
- lis r3,0xFF14 # PICR1
+ lis r3,0xFF14 # PICR1
ori r3,r3,0x1CC8
li r8, 0x0
stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_AC
+ lis r3,0x8000 # ADDR_AC
ori r3,r3,0x00AC
stwbrx r3,0,r4
- lis r3,0x0000 # PICR2
+ lis r3,0x0000 # PICR2
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c
index 0597c72..402ac5e 100644
--- a/board/ppmc7xx/ppmc7xx.c
+++ b/board/ppmc7xx/ppmc7xx.c
@@ -1,9 +1,9 @@
/*
* ppmc7xx.c
* ---------
- *
+ *
* Main board-specific routines for Wind River PPMC 7xx/74xx board.
- *
+ *
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
@@ -24,7 +24,7 @@
/*
* initdram()
- *
+ *
* This function normally initialises the (S)DRAM of the system. For this board
* the SDRAM was already initialised by board_asm_init (see init.S) so we just
* return the size of RAM.
@@ -37,12 +37,12 @@
/*
* after_reloc()
- *
+ *
* This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
* us an opportunity to do some additional setup before the rest of the system
* is initialised. We don't need to do anything, so we just call board_init_r()
* which should never return.
- */
+ */
void after_reloc( ulong dest_addr, gd_t* gd )
{
/* Jump to the main U-Boot board init code */
@@ -52,7 +52,7 @@
/*
* checkboard()
- *
+ *
* We could do some board level checks here, such as working out what version
* it is, but for this board we simply display it's name (on the console).
*/
@@ -65,7 +65,7 @@
/*
* misc_init_r
- *
+ *
* Used for other setup which needs to be done late in the bring-up phase.
*/
int misc_init_r( void )
@@ -78,27 +78,27 @@
/* Enable the I-Cache */
icache_enable();
-
+
return 0;
}
/*
* do_reset()
- *
+ *
* Shell command to reset the board.
*/
void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
{
printf( "Resetting...\n" );
-
+
/* Disabe and invalidate cache */
icache_disable();
dcache_disable();
/* Jump to warm start (in RAM) */
_start_warm();
-
+
/* Should never get here */
while(1);
}
diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile
index 13ce9fc..1a7e7a6 100644
--- a/board/r360mpi/Makefile
+++ b/board/r360mpi/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c
new file mode 100644
index 0000000..7d34ac8
--- /dev/null
+++ b/board/r360mpi/pcmcia.c
@@ -0,0 +1,236 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "R360MPI"
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Configure Ports A, B & C pins for
+ * 5 Volts Enable and 3 Volts enable
+ */
+ immap->im_ioport.iop_pcpar &= ~(0x0400);
+ immap->im_ioport.iop_pcso &= ~(0x0400);/*
+ immap->im_ioport.iop_pcdir |= 0x0400;*/
+
+ immap->im_ioport.iop_papar &= ~(0x0200);/*
+ immap->im_ioport.iop_padir |= 0x0200;*/
+#if 0
+ immap->im_ioport.iop_pbpar &= ~(0xC000);
+ immap->im_ioport.iop_pbdir &= ~(0xC000);
+#endif
+ /* remove all power */
+
+ immap->im_ioport.iop_pcdat |= 0x0400;
+ immap->im_ioport.iop_padat |= 0x0200;
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+ if ((reg & mask) == mask) {
+ immap->im_ioport.iop_pcdat &= ~(0x4000);
+ puts (" 5.0V card found: ");
+ } else {
+ immap->im_ioport.iop_padat &= ~(0x0002);
+ puts (" 3.3V card found: ");
+ }
+ immap->im_ioport.iop_pcdir |= 0x0400;
+ immap->im_ioport.iop_padir |= 0x0200;
+#if 0
+ /* VCC switch error flag, PCMCIA slot INPACK_ pin */
+ cp->cp_pbdir &= ~(0x0020 | 0x0010);
+ cp->cp_pbpar &= ~(0x0020 | 0x0010);
+ udelay(500000);
+#endif
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+ /* remove all power */
+ immap->im_ioport.iop_pcdat |= 0x0400;
+ immap->im_ioport.iop_padat |= 0x0200;
+
+ /* Configure PCMCIA General Control Register */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("voltage_set: "
+ PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Configure Ports A & C pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn off all power
+ */
+ debug ("PCMCIA power OFF\n");
+ immap->im_ioport.iop_pcpar &= ~(0x0400);
+ immap->im_ioport.iop_pcso &= ~(0x0400);/*
+ immap->im_ioport.iop_pcdir |= 0x0400;*/
+
+ immap->im_ioport.iop_papar &= ~(0x0200);/*
+ immap->im_ioport.iop_padir |= 0x0200;*/
+
+ immap->im_ioport.iop_pcdat |= 0x0400;
+ immap->im_ioport.iop_padat |= 0x0200;
+
+ reg = 0;
+ switch(vcc) {
+ case 0: break;
+ case 33: reg |= 0x0200; break;
+ case 50: reg |= 0x0400; break;
+ default: goto done;
+ }
+
+ /* Checking supported voltages */
+
+ debug ("PIPR: 0x%x --> %s\n",
+ pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+ if (reg & 0x0200)
+ immap->im_ioport.iop_pcdat &= !reg;
+ if (reg & 0x0400)
+ immap->im_ioport.iop_padat &= !reg;
+ immap->im_ioport.iop_pcdir |= 0x0200;
+ immap->im_ioport.iop_padir |= 0x0400;
+ if (reg) {
+ debug ("PCMCIA powered at %sV\n",
+ (reg&0x0400) ? "5.0" : "3.3");
+ } else {
+ debug ("PCMCIA powered down\n");
+ }
+
+done:
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* CCONFIG_PCMCIA */
diff --git a/board/sbc2410x/Makefile b/board/sbc2410x/Makefile
new file mode 100644
index 0000000..ae8665e
--- /dev/null
+++ b/board/sbc2410x/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := sbc2410x.o flash.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sbc2410x/config.mk b/board/sbc2410x/config.mk
new file mode 100644
index 0000000..f244e64
--- /dev/null
+++ b/board/sbc2410x/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SMDK2410 has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3400'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3300'0000
+
+TEXT_BASE = 0x33F80000
diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c
new file mode 100644
index 0000000..f2718f2
--- /dev/null
+++ b/board/sbc2410x/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush (void);
+
+#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#define CMD_READ_ARRAY 0x000000F0
+#define CMD_UNLOCK1 0x000000AA
+#define CMD_UNLOCK2 0x00000055
+#define CMD_ERASE_SETUP 0x00000080
+#define CMD_ERASE_CONFIRM 0x00000030
+#define CMD_PROGRAM 0x000000A0
+#define CMD_UNLOCK_BYPASS 0x00000020
+
+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE 0x00000080
+#define BIT_RDY_MASK 0x00000080
+#define BIT_PROGRAM_ERROR 0x00000020
+#define BIT_TIMEOUT 0x80000000 /* our flag */
+
+#define READY 1
+#define ERR 2
+#define TMO 4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ ulong flashbase = 0;
+
+ flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+ (AMD_MANUFACT & FLASH_VENDMASK) |
+ (AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+ (AMD_MANUFACT & FLASH_VENDMASK) |
+ (AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ if (i == 0)
+ flashbase = PHYS_FLASH_1;
+ else
+ panic ("configured too many flash banks!\n");
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ if (j <= 3) {
+ /* 1st one is 16 KB */
+ if (j == 0) {
+ flash_info[i].start[j] =
+ flashbase + 0;
+ }
+
+ /* 2nd and 3rd are both 8 KB */
+ if ((j == 1) || (j == 2)) {
+ flash_info[i].start[j] =
+ flashbase + 0x4000 + (j -
+ 1) *
+ 0x2000;
+ }
+
+ /* 4th 32 KB */
+ if (j == 3) {
+ flash_info[i].start[j] =
+ flashbase + 0x8000;
+ }
+ } else {
+ flash_info[i].start[j] =
+ flashbase + (j - 3) * MAIN_SECT_SIZE;
+ }
+ }
+ size += flash_info[i].size;
+ }
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (AMD_MANUFACT & FLASH_VENDMASK):
+ printf ("AMD: ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case (AMD_ID_LV400B & FLASH_TYPEMASK):
+ printf ("1x Amd29LV400BB (4Mbit)\n");
+ break;
+ case (AMD_ID_LV800B & FLASH_TYPEMASK):
+ printf ("1x Amd29LV800BB (8Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ goto Done;
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 5) == 0) {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+
+ Done:;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ ushort result;
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+ int chip;
+
+ /* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+ (AMD_MANUFACT & FLASH_VENDMASK)) {
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot)
+ return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_short *addr = (vu_short *) (info->start[sect]);
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ *addr = CMD_ERASE_CONFIRM;
+
+ /* wait until flash is ready */
+ chip = 0;
+
+ do {
+ result = *addr;
+
+ /* check timeout */
+ if (get_timer_masked () >
+ CFG_FLASH_ERASE_TOUT) {
+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+ chip = TMO;
+ break;
+ }
+
+ if (!chip
+ && (result & 0xFFFF) & BIT_ERASE_DONE)
+ chip = READY;
+
+ if (!chip
+ && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+ chip = ERR;
+
+ } while (!chip);
+
+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+ if (chip == ERR) {
+ rc = ERR_PROG_ERROR;
+ goto outahere;
+ }
+ if (chip == TMO) {
+ rc = ERR_TIMOUT;
+ goto outahere;
+ }
+
+ printf ("ok.\n");
+ } else { /* it was protected */
+
+ printf ("protected!\n");
+ }
+ }
+
+ if (ctrlc ())
+ printf ("User Interrupt!\n");
+
+ outahere:
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked (10000);
+
+ if (iflag)
+ enable_interrupts ();
+
+ if (cflag)
+ icache_enable ();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+{
+ vu_short *addr = (vu_short *) dest;
+ ushort result;
+ int rc = ERR_OK;
+ int cflag, iflag;
+ int chip;
+
+ /*
+ * Check if Flash is (sufficiently) erased
+ */
+ result = *addr;
+ if ((result & data) != data)
+ return ERR_NOT_ERASED;
+
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+ *addr = CMD_PROGRAM;
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait until flash is ready */
+ chip = 0;
+ do {
+ result = *addr;
+
+ /* check timeout */
+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ chip = ERR | TMO;
+ break;
+ }
+ if (!chip && ((result & 0x80) == (data & 0x80)))
+ chip = READY;
+
+ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+ result = *addr;
+
+ if ((result & 0x80) == (data & 0x80))
+ chip = READY;
+ else
+ chip = ERR;
+ }
+
+ } while (!chip);
+
+ *addr = CMD_READ_ARRAY;
+
+ if (chip == ERR || *addr != data)
+ rc = ERR_PROG_ERROR;
+
+ if (iflag)
+ enable_interrupts ();
+
+ if (cflag)
+ icache_enable ();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ int l;
+ int i, rc;
+ ushort data;
+
+ wp = (addr & ~1); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+ for (; i < 2 && cnt > 0; ++i) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+
+ if ((rc = write_hword (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 2;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 2) {
+ data = *((vu_short *) src);
+ if ((rc = write_hword (info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 2;
+ wp += 2;
+ cnt -= 2;
+ }
+
+ if (cnt == 0) {
+ return ERR_OK;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ }
+ for (; i < 2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+
+ return write_hword (info, wp, data);
+}
diff --git a/board/sbc2410x/lowlevel_init.S b/board/sbc2410x/lowlevel_init.S
new file mode 100644
index 0000000..3df63cd
--- /dev/null
+++ b/board/sbc2410x/lowlevel_init.S
@@ -0,0 +1,163 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * Modified for the friendly-arm SBC-2410X by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/*
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
+ */
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW16)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+#define B0_Tacs 0x0
+#define B0_Tcos 0x0
+#define B0_Tacc 0x7
+#define B0_Tcoh 0x0
+#define B0_Tah 0x0
+#define B0_Tacp 0x0
+#define B0_PMC 0x0
+
+#define B1_Tacs 0x0
+#define B1_Tcos 0x0
+#define B1_Tacc 0x7
+#define B1_Tcoh 0x0
+#define B1_Tah 0x0
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0xc
+#define B3_Tcos 0x7
+#define B3_Tacc 0xf
+#define B3_Tcoh 0x1
+#define B3_Tah 0x0
+#define B3_Tacp 0x0
+#define B3_PMC 0x0
+
+#define B4_Tacs 0x0
+#define B4_Tcos 0x0
+#define B4_Tacc 0x7
+#define B4_Tcoh 0x0
+#define B4_Tah 0x0
+#define B4_Tacp 0x0
+#define B4_PMC 0x0
+
+#define B5_Tacs 0xc
+#define B5_Tcos 0x7
+#define B5_Tacc 0xf
+#define B5_Tcoh 0x1
+#define B5_Tah 0x0
+#define B5_Tacp 0x0
+#define B5_PMC 0x0
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1
+#define B6_SCAN 0x1 /* 9bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+#define REFCNT 0x0459
+/**************************************/
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #13*4
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0xb2
+ .word 0x30
+ .word 0x30
diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c
new file mode 100644
index 0000000..7030985
--- /dev/null
+++ b/board/sbc2410x/sbc2410x.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2410.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV 0xC3
+#define M_PDIV 0x4
+#define M_SDIV 0x1
+#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
+#define M_MDIV 0x5c
+#define M_PDIV 0x4
+#define M_SDIV 0x0
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV 0xA1
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV 0x48
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x2
+#endif
+
+static inline void delay (unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->LOCKTIME = 0xFFFFFF;
+
+ /* configure MPLL */
+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (4000);
+
+ /* configure UPLL */
+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (8000);
+
+ /* set up the I/O ports */
+ gpio->GPACON = 0x007FFFFF;
+ gpio->GPBCON = 0x00044556;
+ gpio->GPBUP = 0x000007FF;
+ gpio->GPCCON = 0xAAAAAAAA;
+ gpio->GPCUP = 0x0000FFFF;
+ gpio->GPDCON = 0xAAAAAAAA;
+ gpio->GPDUP = 0x0000FFFF;
+ gpio->GPECON = 0xAAAAAAAA;
+ gpio->GPEUP = 0x0000FFFF;
+ gpio->GPFCON = 0x000055AA;
+ gpio->GPFUP = 0x000000FF;
+ gpio->GPGCON = 0xFF95FF3A;
+ gpio->GPGUP = 0x0000FFFF;
+ gpio->GPHCON = 0x0016FAAA;
+ gpio->GPHUP = 0x000007FF;
+
+ gpio->EXTINT0=0x22222222;
+ gpio->EXTINT1=0x22222222;
+ gpio->EXTINT2=0x22222222;
+
+ /* arch number of SMDK2410-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
+
+ icache_enable();
+ dcache_enable();
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong nand_probe(ulong physadr);
+
+static inline void NF_Reset(void)
+{
+ int i;
+
+ NF_SetCE(NFCE_LOW);
+ NF_Cmd(0xFF); /* reset command */
+ for(i = 0; i < 10; i++); /* tWB = 100ns. */
+ NF_WaitRB(); /* wait 200~500us; */
+ NF_SetCE(NFCE_HIGH);
+}
+
+static inline void NF_Init(void)
+{
+#if 1
+#define TACLS 0
+#define TWRPH0 3
+#define TWRPH1 0
+#else
+#define TACLS 0
+#define TWRPH0 4
+#define TWRPH1 2
+#endif
+
+ NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
+ /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
+ /* 1 1 1 1, 1 xxx, r xxx, r xxx */
+ /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
+
+ NF_Reset();
+}
+
+void nand_init(void)
+{
+ S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+ NF_Init();
+#ifdef DEBUG
+ printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
+#endif
+ printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
diff --git a/board/sbc2410x/u-boot.lds b/board/sbc2410x/u-boot.lds
new file mode 100644
index 0000000..76df6b2
--- /dev/null
+++ b/board/sbc2410x/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile
new file mode 100644
index 0000000..47afef7
--- /dev/null
+++ b/board/spc1920/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/spc1920/config.mk b/board/spc1920/config.mk
new file mode 100644
index 0000000..e361694
--- /dev/null
+++ b/board/spc1920/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
+# MPC885ADS boards
+#
+
+#TEXT_BASE = 0xFE000000
+TEXT_BASE = 0xFFF00000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/spc1920
+HOST_CFLAGS += -I$(TOPDIR)/board/spc1920
+HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/spc1920
diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h
new file mode 100644
index 0000000..3254f82
--- /dev/null
+++ b/board/spc1920/pld.h
@@ -0,0 +1,14 @@
+#ifndef __PLD_H__
+#define __PLD_H__
+
+typedef struct spc1920_pld {
+ uchar com1_en;
+ uchar dsp_reset;
+ uchar dsp_hpi_on;
+ uchar codec_dsp_power_en;
+ uchar clk2_en;
+ uchar clk3_select;
+ uchar clk4_select;
+} spc1920_pld_t;
+
+#endif /* __PLD_H__ */
diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c
new file mode 100644
index 0000000..028f4c6
--- /dev/null
+++ b/board/spc1920/spc1920.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mpc8xx.h>
+#include "pld.h"
+
+#define _NOT_USED_ 0xFFFFFFFF
+/* #define debug(fmt,args...) printf (fmt ,##args) */
+
+static long int dram_size (long int, long int *, long int);
+
+const uint sdram_table[] = {
+ /*
+ * Single Read. (Offset 0 in UPMB RAM)
+ */
+ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+ 0x1FF77C47, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPMB RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPMB RAM)
+ */
+ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPMB RAM)
+ */
+ 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPMB RAM)
+ */
+ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+ 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPMB RAM)
+ */
+ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPMB RAM)
+ */
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; */
+
+ long int size_b0;
+ long int size8, size9;
+ int i;
+
+ /*
+ * Configure UPMB for SDRAM
+ */
+ upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ udelay(100);
+
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ /* burst length=4, burst type=sequential, CAS latency=2 */
+ memctl->memc_mar = CFG_MAR;
+
+ /*
+ * Map controller bank 1 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ /* initialize memory address register */
+ memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
+
+ /* mode initialization (offset 5) */
+ udelay (200); /* 0x80006105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);
+
+ /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+ udelay (1); /* 0x80006130 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
+ udelay (1); /* 0x80006130 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
+ udelay (1); /* 0x80006106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);
+
+ memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
+
+ udelay (200);
+
+ /* Need at least 10 DRAM accesses to stabilize */
+ for (i = 0; i < 10; ++i) {
+ volatile unsigned long *addr =
+ (volatile unsigned long *) CFG_SDRAM_BASE;
+ unsigned long val;
+
+ val = *(addr + i);
+ *(addr + i) = val;
+ }
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CFG_MBMR_8COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
+
+ udelay (1000);
+
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MBMR_9COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size_b0 = size9;
+ memctl->memc_mbmr = CFG_MBMR_9COL | MBMR_PTBE;
+ udelay (500);
+ } else { /* back to 8 columns */
+ size_b0 = size8;
+ memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+ udelay (500);
+ }
+
+ /*
+ * Final mapping:
+ */
+
+ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
+ OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
+ memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
+ udelay (1000);
+
+
+ /* PLD Setup */
+ memctl->memc_or5 = CFG_OR5_PRELIM;
+ memctl->memc_br5 = CFG_BR5_PRELIM;
+ udelay(1000);
+
+ return (size_b0);
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int mbmr_value, long int *base,
+ long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ memctl->memc_mbmr = mbmr_value;
+
+ return (get_ram_size (base, maxsize));
+}
+
+
+/************* other stuff ******************/
+
+
+int board_early_init_f(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+
+ /* Turn on LED PD9 */
+ immap->im_ioport.iop_pdpar &= ~(0x0040);
+ immap->im_ioport.iop_pddir |= 0x0040;
+ immap->im_ioport.iop_pddat |= 0x0040;
+
+ /* Enable PD10 (COM2_EN) */
+ immap->im_ioport.iop_pdpar &= ~0x0020;
+ immap->im_ioport.iop_pddir &= ~0x4000;
+ immap->im_ioport.iop_pddir |= 0x0020;
+ immap->im_ioport.iop_pddat |= 0x0020;
+
+
+#ifdef CFG_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
+ immap->im_cpm.cp_simode |= 0x7000;
+ immap->im_cpm.cp_simode &= ~(0x8000);
+#endif
+
+ return 0;
+}
+
+
+int checkboard (void)
+{
+ puts("Board: SPC1920\n");
+ return 0;
+}
diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds
new file mode 100644
index 0000000..d526d1d
--- /dev/null
+++ b/board/spc1920/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ cpu/mpc8xx/traps.o (.text)
+ common/dlmalloc.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/time.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.ppcenv)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile
index ab0ff1a..9a1ea48 100644
--- a/board/tqm5200/Makefile
+++ b/board/tqm5200/Makefile
@@ -25,7 +25,7 @@
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o cmd_stk52xx.o
+OBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c
index 8b9057f..c37d4c6 100755
--- a/board/tqm5200/cmd_stk52xx.c
+++ b/board/tqm5200/cmd_stk52xx.c
@@ -22,7 +22,7 @@
*/
/*
- * SKT52XX specific functions
+ * STK52XX specific functions
*/
/*#define DEBUG*/
@@ -30,6 +30,7 @@
#include <command.h>
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#if defined (CONFIG_STK52XX)
#define DEFAULT_VOL 45
#define DEFAULT_FREQ 500
@@ -60,7 +61,6 @@
static void pcm1772_write_reg(unsigned char addr, unsigned char data);
static void set_attenuation(unsigned char attenuation);
-#ifdef CONFIG_STK52XX
static void spi_init(void)
{
struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
@@ -1209,7 +1209,7 @@
fkt , 4, 1, cmd_fkt,
"fkt - Function test routines\n",
"led number on/off\n"
- " - 'number's like printed on SKT52XX board\n"
+ " - 'number's like printed on STK52XX board\n"
"fkt can\n"
" - loopback plug for X83 required\n"
"fkt rs232 number\n"
diff --git a/board/tqm5200/cmd_tb5200.c b/board/tqm5200/cmd_tb5200.c
new file mode 100644
index 0000000..8784b1f
--- /dev/null
+++ b/board/tqm5200/cmd_tb5200.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2005 - 2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TB5200 specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#if defined (CONFIG_TB5200)
+
+#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
+
+static void led_init(void)
+{
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ /* configure timer 4 for simple GPIO output */
+ gpt->gpt4.emsr |= 0x00000024;
+}
+
+int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ led_init();
+
+ if (strcmp (argv[1], "on") == 0) {
+ debug ("switch status LED on\n");
+ gpt->gpt4.emsr |= (1 << 4);
+ } else if (strcmp (argv[1], "off") == 0) {
+ debug ("switch status LED off\n");
+ gpt->gpt4.emsr &= ~(1 << 4);
+ } else {
+ printf ("Usage:\nled on/off\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static void sm501_backlight (unsigned int state)
+{
+ if (state == 1) {
+ *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+ (1 << 26) | (1 << 27);
+ } else if (state == 0)
+ *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+ ~((1 << 26) | (1 << 27));
+}
+
+int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (strcmp (argv[1], "on") == 0) {
+ debug ("switch backlight on\n");
+ sm501_backlight (1);
+ } else if (strcmp (argv[1], "off") == 0) {
+ debug ("switch backlight off\n");
+ sm501_backlight (0);
+ } else {
+ printf ("Usage:\nbacklight on/off\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ led , 2, 1, cmd_led,
+ "led - switch status LED on or off\n",
+ "on/off\n"
+);
+
+U_BOOT_CMD(
+ backlight , 2, 1, cmd_backlight,
+ "backlight - switch backlight on or off\n",
+ "on/off\n"
+ );
+
+#endif /* CONFIG_STK52XX */
+#endif /* CFG_CMD_BSP */
diff --git a/board/tqm5200/config.mk b/board/tqm5200/config.mk
index 585a99a..84ddee8 100644
--- a/board/tqm5200/config.mk
+++ b/board/tqm5200/config.mk
@@ -28,12 +28,17 @@
#
# 0xFC000000 boot low (standard configuration with room for max 64 MByte
# Flash ROM)
+# 0xFFF00000 boot high (for a backup copy of U-Boot)
# 0x00100000 boot from RAM (for testing only)
#
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
ifndef TEXT_BASE
## Standard: boot low
TEXT_BASE = 0xFC000000
+## For a backup copy of U-Boot at the end of flash: boot high
+# TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
# TEXT_BASE = 0x00100000
endif
diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c
index 310abd2..d6f7737 100644
--- a/board/tqm5200/tqm5200.c
+++ b/board/tqm5200/tqm5200.c
@@ -1,11 +1,11 @@
/*
- * (C) Copyright 2003-2004
+ * (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
- * (C) Copyright 2004-2005
+ * (C) Copyright 2004-2006
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
@@ -30,6 +30,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <asm/processor.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
@@ -101,6 +102,8 @@
{
ulong dramsize = 0;
ulong dramsize2 = 0;
+ uint svr, pvr;
+
#ifndef CFG_RAMBOOT
ulong test1, test2;
@@ -190,11 +193,31 @@
} else {
dramsize2 = 0;
}
-
#endif /* CFG_RAMBOOT */
-/* return dramsize + dramsize2; */
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
+#if defined(CONFIG_TQM5200_B)
+ return dramsize + dramsize2;
+#else
return dramsize;
+#endif /* CONFIG_TQM5200_B */
}
#elif defined(CONFIG_MGT5100)
@@ -250,20 +273,36 @@
int checkboard (void)
{
-#if defined (CONFIG_AEVFIFO)
+#if defined(CONFIG_AEVFIFO)
puts ("Board: AEVFIFO\n");
return 0;
#endif
-#if defined (CONFIG_TQM5200)
- puts ("Board: TQM5200 (TQ-Components GmbH)\n");
+
+#if defined(CONFIG_TQM5200S)
+# define MODULE_NAME "TQM5200S"
+#else
+# define MODULE_NAME "TQM5200"
#endif
-#if defined (CONFIG_STK52XX)
- puts (" on a STK52XX baseboard\n");
+
+#if defined(CONFIG_STK52XX)
+# define CARRIER_NAME "STK52xx"
+#elif defined(CONFIG_TB5200)
+# define CARRIER_NAME "TB5200"
+#elif defined(CONFIG_CAM5200)
+# define CARRIER_NAME "Cam5200"
+#else
+# error "Unknown carrier board"
#endif
+ puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
+ " on a " CARRIER_NAME " carrier board\n");
+
return 0;
}
+#undef MODULE_NAME
+#undef CARRIER_NAME
+
void flash_preinit(void)
{
/*
@@ -405,7 +444,6 @@
#endif
#endif /* CONFIG_PS2MULT */
-#if defined(CONFIG_CS_AUTOCONF)
int last_stage_init (void)
{
/*
@@ -500,7 +538,6 @@
return 0;
}
-#endif /* CONFIG_CS_AUTOCONF */
#ifdef CONFIG_VIDEO_SM501
@@ -567,9 +604,14 @@
{
if (line_number == 1) {
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_STK52XX)
+#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200)
} else if (line_number == 2) {
- strcpy (info, " on a STK52XX baseboard");
+#if defined (CONFIG_STK52XX)
+ strcpy (info, " on a STK52xx carrier board");
+#endif
+#if defined (CONFIG_TB5200)
+ strcpy (info, " on a TB5200 carrier board");
+#endif
#endif
}
else {
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index d992aec..41b34cc 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -424,10 +424,12 @@
* which has to be written with a certain value defined by
* errata sheet.
*/
+ u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
+
#if defined(DDR_CASLAT_20)
- *((u8 *)im + 0x2f00) = 0x201c0000;
+ *reserved_p = 0x201c0000;
#else
- *((u8 *)im + 0x2f00) = 0x202c0000;
+ *reserved_p = 0x202c0000;
#endif
}
}
diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c
index befe8b7..b4ef5af 100644
--- a/board/tqm85xx/tqm85xx.c
+++ b/board/tqm85xx/tqm85xx.c
@@ -27,10 +27,6 @@
* MA 02111-1307 USA
*/
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init(void);
-#endif
-
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
@@ -47,6 +43,10 @@
long int fixed_sdram (void);
ulong flash_get_size (ulong base, int banknum);
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
+
#ifdef CONFIG_CPM2
/*
* I/O Port configuration table
@@ -423,4 +423,3 @@
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
-
diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c
index ab57ee5..db0a7e5 100644
--- a/board/tqm8xx/flash.c
+++ b/board/tqm8xx/flash.c
@@ -33,12 +33,13 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+ && !defined(CONFIG_TQM885D)
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_2_CLK | OR_EHTR | OR_BI)
# endif
-#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
#ifndef CFG_ENV_ADDR
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index b292231..6b206f8 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -119,6 +119,10 @@
gd->board_type = 'M';
}
+ if ((*(s + 6) == 'D')) { /* a TQM885D type */
+ gd->board_type = 'D';
+ }
+
for (; *s; ++s) {
if (*s == ' ')
break;
@@ -178,7 +182,8 @@
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
- (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
}
@@ -197,7 +202,8 @@
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
- (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
udelay (1);
memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
@@ -214,8 +220,7 @@
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
udelay (1000);
@@ -223,8 +228,7 @@
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
udelay(1000);
@@ -233,8 +237,7 @@
/*
* try 10 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
#else
size10 = 0;
@@ -255,7 +258,8 @@
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
- (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
/*
* Check Bank 1 Memory Size
* use current column settings
diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c
index 442c555..d2c8d44 100644
--- a/board/trab/auto_update.c
+++ b/board/trab/auto_update.c
@@ -57,9 +57,9 @@
* valid then run it.
* 2) if preinst.img is found load it into memory. If it is
* valid then run it. Update the EEPROM.
- * 3) if firmware.img is found load it into memory. If it is valid,
+ * 3) if firmw_01.img is found load it into memory. If it is valid,
* burn it into FLASH and update the EEPROM.
- * 4) if kernel.img is found load it into memory. If it is valid,
+ * 4) if kernl_01.img is found load it into memory. If it is valid,
* burn it into FLASH and update the EEPROM.
* 5) if app.img is found load it into memory. If it is valid,
* burn it into FLASH and update the EEPROM.
@@ -81,8 +81,8 @@
/* possible names of files on the USB stick. */
#define AU_PREPARE "prepare.img"
#define AU_PREINST "preinst.img"
-#define AU_FIRMWARE "firmware.img"
-#define AU_KERNEL "kernel.img"
+#define AU_FIRMWARE "firmw_01.img"
+#define AU_KERNEL "kernl_01.img"
#define AU_APP "app.img"
#define AU_DISK "disk.img"
#define AU_POSTINST "postinst.img"
diff --git a/board/trab/flash.c b/board/trab/flash.c
index 8cdd824..3e8f105 100644
--- a/board/trab/flash.c
+++ b/board/trab/flash.c
@@ -281,10 +281,12 @@
if (chip1 == ERR || chip2 == ERR) {
rc = ERR_PROG_ERROR;
+ printf ("Flash erase error\n");
goto outahere;
}
if (chip1 == TMO) {
rc = ERR_TIMOUT;
+ printf ("Flash erase timeout error\n");
goto outahere;
}
}
@@ -340,7 +342,9 @@
#endif
iflag = disable_interrupts ();
- *addr = CMD_PROGRAM;
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
@@ -352,7 +356,7 @@
result = *addr;
/* check timeout */
- if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
chip1 = ERR | TMO;
break;
}
@@ -384,8 +388,13 @@
*addr = CMD_READ_ARRAY;
- if (chip1 == ERR || chip2 == ERR || *addr != data)
+ if (chip1 == ERR || chip2 == ERR || *addr != data) {
rc = ERR_PROG_ERROR;
+ printf ("Flash program error\n");
+ debug ("chip1: %#x, chip2: %#x, addr: %#lx *addr: %#lx, "
+ "data: %#lx\n",
+ chip1, chip2, addr, *addr, data);
+ }
if (iflag)
enable_interrupts ();
@@ -408,10 +417,6 @@
int l;
int i, rc;
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
-
wp = (addr & ~3); /* get lower word aligned address */
/*
@@ -479,9 +484,6 @@
Done:
- MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1;
- MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2;
-
return (rc);
}
@@ -515,7 +517,7 @@
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
- addr[0] = 0x00FF00FF; /* restore read mode */
+ addr[0] = CMD_READ_ARRAY; /* restore read mode */
debug ("## flash_init: unknown manufacturer\n");
return (0); /* no or unknown flash */
}
@@ -530,7 +532,7 @@
info->sector_count = 71;
info->size = 0x00800000;
- addr[0] = 0x00FF00FF; /* restore read mode */
+ addr[0] = CMD_READ_ARRAY; /* restore read mode */
break; /* => 8 MB */
case AMD_ID_LV640U:
@@ -538,7 +540,7 @@
info->sector_count = 128;
info->size = 0x01000000;
- addr[0] = 0x00F000F0; /* restore read mode */
+ addr[0] = CMD_READ_ARRAY; /* restore read mode */
break; /* => 16 MB */
case MX_ID_LV320B:
@@ -546,13 +548,13 @@
info->sector_count = 71;
info->size = 0x00800000;
- addr[0] = 0x00FF00FF; /* restore read mode */
+ addr[0] = CMD_READ_ARRAY; /* restore read mode */
break; /* => 8 MB */
default:
debug ("## flash_init: unknown flash chip\n");
info->flash_id = FLASH_UNKNOWN;
- addr[0] = 0x00FF00FF; /* restore read mode */
+ addr[0] = CMD_READ_ARRAY; /* restore read mode */
return (0); /* => no or unknown flash */
}
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 26e52d2..d8a726b 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -175,9 +175,11 @@
#endif /* CONFIG_VERSION_VARIABLE */
#ifdef CONFIG_AUTO_UPDATE
- extern int do_auto_update(void);
- /* this has priority over all else */
- do_auto_update();
+ {
+ extern int do_auto_update(void);
+ /* this has priority over all else */
+ do_auto_update();
+ }
#endif
for (i = 0; i < KEYBD_KEY_NUM; ++i) {
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index 2f1e7d7..b6798fd 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -251,19 +251,17 @@
unsigned long adr = gd->fb_base;
unsigned int bit_nr = 0;
- if (vfd_table[x][y][color][display][entry]) {
+ pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs;
+ /*
+ * wrap arround if offset
+ * (see manual S3C2400)
+ */
+ if (pixel>=FRAME_BUF_SIZE*8)
+ pixel = pixel-(FRAME_BUF_SIZE*8);
+ adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8);
+ bit_nr = pixel%8;
+ bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
- pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs;
- /*
- * wrap arround if offset
- * (see manual S3C2400)
- */
- if (pixel>=FRAME_BUF_SIZE*8)
- pixel = pixel-(FRAME_BUF_SIZE*8);
- adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8);
- bit_nr = pixel%8;
- bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
- }
adr_vfd_table[x][y][color][display][entry] = adr;
bit_vfd_table[x][y][color][display][entry] = bit_nr;
}
diff --git a/board/uc100/Makefile b/board/uc100/Makefile
index eb81625..2d2cc23 100644
--- a/board/uc100/Makefile
+++ b/board/uc100/Makefile
@@ -25,8 +25,8 @@
LIB = lib$(BOARD).a
-#OBJS = $(BOARD).o flash.o
-OBJS = $(BOARD).o
+#OBJS = $(BOARD).o flash.o pcmcia.o
+OBJS = $(BOARD).o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/uc100/pcmcia.c b/board/uc100/pcmcia.c
new file mode 100644
index 0000000..6e4b6d6
--- /dev/null
+++ b/board/uc100/pcmcia.c
@@ -0,0 +1,198 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "UC100"
+
+/*
+ * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board.
+ * This leads to board-hangup! (sr, 8 Dez. 2004)
+ */
+static void cfg_ports (void)
+{
+ volatile immap_t *immap;
+
+ immap = (immap_t *)CFG_IMMR;
+
+ /*
+ * Configure Port A for MAX1602 PC-Card Power-Interface Switch
+ */
+ immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */
+ immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */
+
+ debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n",
+ immap->im_ioport.iop_papar, immap->im_ioport.iop_padir,
+ immap->im_ioport.iop_padat);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+ cfg_ports ();
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+ if ((reg & mask) == mask) {
+ puts (" 5.0V card found: ");
+ } else {
+ puts (" 3.3V card found: ");
+ }
+
+ /* switch VCC on */
+ immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
+
+ udelay(10000);
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+ /* switch VCC off */
+ immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
+
+ /* Configure PCMCIA General Control Register */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("voltage_set: "
+ PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ immap = (immap_t *)CFG_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn all power pins to Hi-Z
+ */
+ debug ("PCMCIA power OFF\n");
+ cfg_ports (); /* Enables switch, but all in Hi-Z */
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA */
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 0f4f9b7..d0fae6b 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -707,7 +707,7 @@
#if defined(CFG_MEMTEST_SCRATCH)
vu_long *dummy = (vu_long*)CFG_MEMTEST_SCRATCH;
#else
- vu_long *dummy = NULL;
+ vu_long *dummy = 0; /* yes, this is address 0x0, not NULL */
#endif
int j;
int iterations = 1;
diff --git a/common/cmd_mii.c b/common/cmd_mii.c
index 48a4e77..ee5e43e 100644
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -57,6 +57,11 @@
int rcode = 0;
char *devname;
+ if (argc < 2) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
mii_init ();
#endif
diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c
index 8e3e84b..2eb5b26 100644
--- a/common/cmd_pcmcia.c
+++ b/common/cmd_pcmcia.c
@@ -57,75 +57,14 @@
#include <command.h>
#include <config.h>
#include <pcmcia.h>
-#if defined(CONFIG_8xx)
-#include <mpc8xx.h>
-#endif
-#if defined(CONFIG_LWMON)
-#include <i2c.h>
-#endif
-#ifdef CONFIG_PXA_PCMCIA
-#include <asm/arch/pxa-regs.h>
-#endif
-
#include <asm/io.h>
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \
- ((CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD))
-
-int pcmcia_on (void);
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int pcmcia_off (void);
-#endif
-
-#ifdef CONFIG_I82365
-
-extern int i82365_init (void);
-extern void i82365_exit (void);
-
-#else /* ! CONFIG_I82365 */
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot);
-#endif
-static int hardware_enable (int slot);
-static int voltage_set(int slot, int vcc, int vpp);
-
-#if (! defined(CONFIG_I82365)) && (! defined(CONFIG_PXA_PCMCIA))
-static u_int m8xx_get_graycode(u_int size);
-#endif /* !CONFIG_I82365, !CONFIG_PXA_PCMCIA */
-#if 0
-static u_int m8xx_get_speed(u_int ns, u_int is_io);
-#endif
-
/* -------------------------------------------------------------------- */
-#ifndef CONFIG_PXA_PCMCIA
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-/* look up table for pgcrx registers */
-
-static u_int *pcmcia_pgcrx[2] = {
- &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra,
- &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb,
-};
-#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
-
-#endif /* CONFIG_PXA_PCMCIA */
-
-#endif /* CONFIG_I82365 */
-
-#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
-static void print_funcid (int func);
-static void print_fixed (volatile uchar *p);
-static int identify (volatile uchar *p);
-static int check_ide_device (int slot);
-#endif /* CONFIG_IDE_8xx_PCCARD, CONFIG_PXA_PCMCIA */
-
-const char *indent = "\t ";
-
-/* -------------------------------------------------------------------- */
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+extern int pcmcia_on (void);
+extern int pcmcia_off (void);
int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
@@ -136,7 +75,7 @@
return 1;
}
if (strcmp(argv[1],"on") == 0) {
- rcode = pcmcia_on ();
+ rcode = pcmcia_on ();
} else if (strcmp(argv[1],"off") == 0) {
rcode = pcmcia_off ();
} else {
@@ -146,322 +85,188 @@
return rcode;
}
-#endif /* CFG_CMD_PCMCIA */
+
+U_BOOT_CMD(
+ pinit, 2, 1, do_pinit,
+ "pinit - PCMCIA sub-system\n",
+ "on - power on PCMCIA socket\n"
+ "pinit off - power off PCMCIA socket\n"
+ );
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_PCMCIA */
/* -------------------------------------------------------------------- */
-#ifdef CONFIG_I82365
-int pcmcia_on (void)
-{
- u_int rc;
+#undef CHECK_IDE_DEVICE
- debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- rc = i82365_init();
-
- if (rc == 0) {
- rc = check_ide_device(0);
- }
-
- return (rc);
-}
-#else
-
-#ifndef CONFIG_PXA_PCMCIA
-
-#ifdef CONFIG_HMI10
-# define HMI10_FRAM_TIMING (PCMCIA_SHT(2) | PCMCIA_SST(2) | PCMCIA_SL(4))
-#endif
-#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
-# define CFG_PCMCIA_TIMING (PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12))
-#else
-# define CFG_PCMCIA_TIMING (PCMCIA_SHT(2) | PCMCIA_SST(4) | PCMCIA_SL(9))
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CHECK_IDE_DEVICE
#endif
-int pcmcia_on (void)
-{
- int i;
- u_long reg, base;
- pcmcia_win_t *win;
- u_int slotbit;
- u_int rc, slot;
-
- debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- /* intialize the fixed memory windows */
- win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0);
- base = CFG_PCMCIA_MEM_ADDR;
-
- if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) {
- printf ("Cannot set window size to 0x%08x\n",
- CFG_PCMCIA_MEM_SIZE);
- return (1);
- }
-
- slotbit = PCMCIA_SLOT_x;
- for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
- win->br = base;
-
-#if (PCMCIA_SOCKETS_NO == 2)
- if (i == 4) /* Another slot starting from win 4 */
- slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
-#endif
- switch (i) {
-#ifdef CONFIG_IDE_8xx_PCCARD
- case 4:
-#ifdef CONFIG_HMI10
- { /* map FRAM area */
- win->or = ( PCMCIA_BSIZE_256K
- | PCMCIA_PPS_8
- | PCMCIA_PRS_ATTR
- | slotbit
- | PCMCIA_PV
- | HMI10_FRAM_TIMING );
- break;
- }
-#endif
- case 0: { /* map attribute memory */
- win->or = ( PCMCIA_BSIZE_64M
- | PCMCIA_PPS_8
- | PCMCIA_PRS_ATTR
- | slotbit
- | PCMCIA_PV
- | CFG_PCMCIA_TIMING );
- break;
- }
- case 5:
- case 1: { /* map I/O window for data reg */
- win->or = ( PCMCIA_BSIZE_1K
- | PCMCIA_PPS_16
- | PCMCIA_PRS_IO
- | slotbit
- | PCMCIA_PV
- | CFG_PCMCIA_TIMING );
- break;
- }
- case 6:
- case 2: { /* map I/O window for cmd/ctrl reg block */
- win->or = ( PCMCIA_BSIZE_1K
- | PCMCIA_PPS_8
- | PCMCIA_PRS_IO
- | slotbit
- | PCMCIA_PV
- | CFG_PCMCIA_TIMING );
- break;
- }
-#endif /* CONFIG_IDE_8xx_PCCARD */
-#ifdef CONFIG_HMI10
- case 3: { /* map I/O window for 4xUART data/ctrl */
- win->br += 0x40000;
- win->or = ( PCMCIA_BSIZE_256K
- | PCMCIA_PPS_8
- | PCMCIA_PRS_IO
- | slotbit
- | PCMCIA_PV
- | CFG_PCMCIA_TIMING );
- break;
- }
-#endif /* CONFIG_HMI10 */
- default: /* set to not valid */
- win->or = 0;
- break;
- }
-
- debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",
- i, win->br, win->or);
- base += CFG_PCMCIA_MEM_SIZE;
- ++win;
- }
-
- for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
- /* turn off voltage */
- if ((rc = voltage_set(slot, 0, 0)))
- continue;
-
- /* Enable external hardware */
- if ((rc = hardware_enable(slot)))
- continue;
-
-#ifdef CONFIG_IDE_8xx_PCCARD
- if ((rc = check_ide_device(i)))
- continue;
-#endif
- }
- return (rc);
-}
-
-#endif /* CONFIG_PXA_PCMCIA */
-
-#endif /* CONFIG_I82365 */
-
-#ifdef CONFIG_PXA_PCMCIA
-
-static int hardware_enable (int slot)
-{
- return 0; /* No hardware to enable */
-}
-
-static int hardware_disable(int slot)
-{
- return 0; /* No hardware to disable */
-}
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- return 0;
-}
-
-void msWait(unsigned msVal)
-{
- udelay(msVal*1000);
-}
-
-int pcmcia_on (void)
-{
- unsigned int reg_arr[] = {
- 0x48000028, CFG_MCMEM0_VAL,
- 0x4800002c, CFG_MCMEM1_VAL,
- 0x48000030, CFG_MCATT0_VAL,
- 0x48000034, CFG_MCATT1_VAL,
- 0x48000038, CFG_MCIO0_VAL,
- 0x4800003c, CFG_MCIO1_VAL,
-
- 0, 0
- };
- int i, rc;
-
-#ifdef CONFIG_EXADRON1
- int cardDetect;
- volatile unsigned int *v_pBCRReg =
- (volatile unsigned int *) 0x08000000;
+#if defined(CONFIG_PXA_PCMCIA)
+#define CHECK_IDE_DEVICE
#endif
- debug ("%s\n", __FUNCTION__);
+#ifdef CHECK_IDE_DEVICE
- i = 0;
- while (reg_arr[i])
- *((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++];
- udelay (1000);
-
- debug ("%s: programmed mem controller \n", __FUNCTION__);
-
-#ifdef CONFIG_EXADRON1
-
-/*define useful BCR masks */
-#define BCR_CF_INIT_VAL 0x00007230
-#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231
-#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233
-#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213
-#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211
-
- /* we see from the GPIO bit if the card is present */
- cardDetect = !(GPLR0 & GPIO_bit (14));
-
- if (cardDetect) {
- printf ("No PCMCIA card found!\n");
- }
-
- /* reset the card via the BCR line */
- *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL;
- msWait (500);
-
- *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL;
- msWait (500);
-
- *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL;
- msWait (500);
-
- *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL;
- msWait (500);
-
- *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL;
- msWait (1500);
-
- /* enable address bus */
- GPCR1 = 0x01;
- /* and the first CF slot */
- MECR = 0x00000002;
-
-#endif /* EXADRON 1 */
-
- rc = check_ide_device (0); /* use just slot 0 */
-
- return rc;
-}
-
-#endif /* CONFIG_PXA_PCMCIA */
-
-/* -------------------------------------------------------------------- */
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-
-#ifdef CONFIG_I82365
-static int pcmcia_off (void)
-{
- printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- i82365_exit();
-
- return 0;
-}
-#else
-
-#ifndef CONFIG_PXA_PCMCIA
-
-static int pcmcia_off (void)
-{
- int i;
- pcmcia_win_t *win;
-
- printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- /* clear interrupt state, and disable interrupts */
- ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);
- ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /* turn off interrupt and disable CxOE */
- PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
-
- /* turn off memory windows */
- win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0);
-
- for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
- /* disable memory window */
- win->or = 0;
- ++win;
- }
-
- /* turn off voltage */
- voltage_set(_slot_, 0, 0);
-
- /* disable external hardware */
- printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
- hardware_disable(_slot_);
- return 0;
-}
-
-#endif /* CONFIG_PXA_PCMCIA */
-
-#endif /* CONFIG_I82365 */
-
-#ifdef CONFIG_PXA_PCMCIA
-static int pcmcia_off (void)
-{
- return 0;
-}
-#endif
-
-#endif /* CFG_CMD_PCMCIA */
-
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
+int ide_devices_found;
+static uchar *known_cards[] = {
+ (uchar *)"ARGOSY PnPIDE D5",
+ NULL
+};
#define MAX_TUPEL_SZ 512
#define MAX_FEATURES 4
-int ide_devices_found;
-static int check_ide_device (int slot)
+#define MAX_IDENT_CHARS 64
+#define MAX_IDENT_FIELDS 4
+
+#define indent "\t "
+
+static void print_funcid (int func)
+{
+ puts (indent);
+ switch (func) {
+ case CISTPL_FUNCID_MULTI:
+ puts (" Multi-Function");
+ break;
+ case CISTPL_FUNCID_MEMORY:
+ puts (" Memory");
+ break;
+ case CISTPL_FUNCID_SERIAL:
+ puts (" Serial Port");
+ break;
+ case CISTPL_FUNCID_PARALLEL:
+ puts (" Parallel Port");
+ break;
+ case CISTPL_FUNCID_FIXED:
+ puts (" Fixed Disk");
+ break;
+ case CISTPL_FUNCID_VIDEO:
+ puts (" Video Adapter");
+ break;
+ case CISTPL_FUNCID_NETWORK:
+ puts (" Network Adapter");
+ break;
+ case CISTPL_FUNCID_AIMS:
+ puts (" AIMS Card");
+ break;
+ case CISTPL_FUNCID_SCSI:
+ puts (" SCSI Adapter");
+ break;
+ default:
+ puts (" Unknown");
+ break;
+ }
+ puts (" Card\n");
+}
+
+static void print_fixed (volatile uchar *p)
+{
+ if (p == NULL)
+ return;
+
+ puts(indent);
+
+ switch (*p) {
+ case CISTPL_FUNCE_IDE_IFACE:
+ { uchar iface = *(p+2);
+
+ puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
+ puts (" interface ");
+ break;
+ }
+ case CISTPL_FUNCE_IDE_MASTER:
+ case CISTPL_FUNCE_IDE_SLAVE:
+ { uchar f1 = *(p+2);
+ uchar f2 = *(p+4);
+
+ puts ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
+
+ if (f1 & CISTPL_IDE_UNIQUE)
+ puts (" [unique]");
+
+ puts ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
+
+ if (f2 & CISTPL_IDE_HAS_SLEEP)
+ puts (" [sleep]");
+
+ if (f2 & CISTPL_IDE_HAS_STANDBY)
+ puts (" [standby]");
+
+ if (f2 & CISTPL_IDE_HAS_IDLE)
+ puts (" [idle]");
+
+ if (f2 & CISTPL_IDE_LOW_POWER)
+ puts (" [low power]");
+
+ if (f2 & CISTPL_IDE_REG_INHIBIT)
+ puts (" [reg inhibit]");
+
+ if (f2 & CISTPL_IDE_HAS_INDEX)
+ puts (" [index]");
+
+ if (f2 & CISTPL_IDE_IOIS16)
+ puts (" [IOis16]");
+
+ break;
+ }
+ }
+ putc ('\n');
+}
+
+static int identify (volatile uchar *p)
+{
+ uchar id_str[MAX_IDENT_CHARS];
+ uchar data;
+ uchar *t;
+ uchar **card;
+ int i, done;
+
+ if (p == NULL)
+ return (0); /* Don't know */
+
+ t = id_str;
+ done =0;
+
+ for (i=0; i<=4 && !done; ++i, p+=2) {
+ while ((data = *p) != '\0') {
+ if (data == 0xFF) {
+ done = 1;
+ break;
+ }
+ *t++ = data;
+ if (t == &id_str[MAX_IDENT_CHARS-1]) {
+ done = 1;
+ break;
+ }
+ p += 2;
+ }
+ if (!done)
+ *t++ = ' ';
+ }
+ *t = '\0';
+ while (--t > id_str) {
+ if (*t == ' ')
+ *t = '\0';
+ else
+ break;
+ }
+ puts ((char *)id_str);
+ putc ('\n');
+
+ for (card=known_cards; *card; ++card) {
+ debug ("## Compare against \"%s\"\n", *card);
+ if (strcmp((char *)*card, (char *)id_str) == 0) { /* found! */
+ debug ("## CARD FOUND ##\n");
+ return (1);
+ }
+ }
+
+ return (0); /* don't know */
+}
+
+int check_ide_device (int slot)
{
volatile uchar *ident = NULL;
volatile uchar *feature_p[MAX_FEATURES];
@@ -556,2933 +361,5 @@
#endif
return (0);
}
-#endif /* CONFIG_IDE_8xx_PCCARD */
-/* -------------------------------------------------------------------- */
-
-
-/* -------------------------------------------------------------------- */
-/* board specific stuff: */
-/* voltage_set(), hardware_enable() and hardware_disable() */
-/* -------------------------------------------------------------------- */
-
-/* -------------------------------------------------------------------- */
-/* RPX Boards from Embedded Planet */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
-
-/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
- * SYPCR is write once only, therefore must the slowest memory be faster
- * than the bus monitor or we will get a machine check due to the bus timeout.
- */
-
-#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
-
-#undef PCMCIA_BMT_LIMIT
-#define PCMCIA_BMT_LIMIT (6*8)
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- u_long reg = 0;
-
- switch(vcc) {
- case 0: break;
- case 33: reg |= BCSR1_PCVCTL4; break;
- case 50: reg |= BCSR1_PCVCTL5; break;
- default: return 1;
- }
-
- switch(vpp) {
- case 0: break;
- case 33:
- case 50:
- if(vcc == vpp)
- reg |= BCSR1_PCVCTL6;
- else
- return 1;
- break;
- case 120:
- reg |= BCSR1_PCVCTL7;
- default: return 1;
- }
-
- if(vcc == 120)
- return 1;
-
- /* first, turn off all power */
-
- *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5
- | BCSR1_PCVCTL6 | BCSR1_PCVCTL7);
-
- /* enable new powersettings */
-
- *((uint *)RPX_CSR_ADDR) |= reg;
-
- return 0;
-}
-
-#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
-static int hardware_enable (int slot)
-{
- return 0; /* No hardware to enable */
-}
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- return 0; /* No hardware to disable */
-}
-#endif /* CFG_CMD_PCMCIA */
-#endif /* CONFIG_RPXCLASSIC */
-
-/* -------------------------------------------------------------------- */
-/* (F)ADS Boards from Motorola */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_ADS) || defined(CONFIG_FADS)
-
-#ifdef CONFIG_ADS
-#define PCMCIA_BOARD_MSG "ADS"
-#define PCMCIA_GLITCHY_CD /* My ADS board needs this */
-#else
-#define PCMCIA_BOARD_MSG "FADS"
-#endif
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- u_long reg = 0;
-
- switch(vpp) {
- case 0: reg = 0; break;
- case 50: reg = 1; break;
- case 120: reg = 2; break;
- default: return 1;
- }
-
- switch(vcc) {
- case 0: reg = 0; break;
-#ifdef CONFIG_ADS
- case 50: reg = BCSR1_PCCVCCON; break;
-#endif
-#ifdef CONFIG_FADS
- case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break;
- case 50: reg = BCSR1_PCCVCC1; break;
-#endif
- default: return 1;
- }
-
- /* first, turn off all power */
-
-#ifdef CONFIG_ADS
- *((uint *)BCSR1) |= BCSR1_PCCVCCON;
-#endif
-#ifdef CONFIG_FADS
- *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1);
-#endif
- *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK;
-
- /* enable new powersettings */
-
-#ifdef CONFIG_ADS
- *((uint *)BCSR1) &= ~reg;
-#endif
-#ifdef CONFIG_FADS
- *((uint *)BCSR1) |= reg;
-#endif
-
- *((uint *)BCSR1) |= reg << 20;
-
- return 0;
-}
-
-#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
-
-static int hardware_enable(int slot)
-{
- *((uint *)BCSR1) &= ~BCSR1_PCCEN;
- return 0;
-}
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- *((uint *)BCSR1) &= ~BCSR1_PCCEN;
- return 0;
-}
-#endif /* CFG_CMD_PCMCIA */
-
-#endif /* (F)ADS */
-
-/* -------------------------------------------------------------------- */
-/* TQM8xxL Boards by TQ Components */
-/* SC8xx Boards by SinoVee Microsystems */
-/* -------------------------------------------------------------------- */
-
-#if (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)) \
- && !defined(CONFIG_VIRTLAB2)
-
-#if defined(CONFIG_TQM8xxL)
-#define PCMCIA_BOARD_MSG "TQM8xxL"
-#endif
-#if defined(CONFIG_SVM_SC8xx)
-#define PCMCIA_BOARD_MSG "SC8xx"
-#endif
-
-static int hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CFG_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(slot);
- pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
-#ifndef NSCU_OE_INV
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
-#endif
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
-#ifndef CONFIG_HMI10
-#ifndef CONFIG_NSCU
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable
- */
- immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004);
- immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004);
- /* remove all power */
-
- immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
-#endif
-#else /* CONFIG_HMI10 */
- /*
- * Configure Port B pins for
- * 5 Volts Enable and 3 Volts enable
- */
- immap->im_cpm.cp_pbpar &= ~(0x00000300);
-
- /* remove all power */
- immap->im_cpm.cp_pbdat |= 0x00000300;
-#endif /* CONFIG_HMI10 */
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-#ifndef CONFIG_HMI10
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
-#else
- if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
-#endif /* CONFIG_HMI10 */
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-#ifndef CONFIG_NSCU
- if ((reg & mask) == mask) {
-#ifndef CONFIG_HMI10
- immap->im_ioport.iop_pcdat |= 0x0004;
-#else
- immap->im_cpm.cp_pbdat &= ~(0x0000100);
-#endif /* CONFIG_HMI10 */
- puts (" 5.0V card found: ");
- } else {
-#ifndef CONFIG_HMI10
- immap->im_ioport.iop_pcdat |= 0x0002;
-#else
- immap->im_cpm.cp_pbdat &= ~(0x0000200);
-#endif /* CONFIG_HMI10 */
- puts (" 3.3V card found: ");
- }
-#ifndef CONFIG_HMI10
- immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
-#else
- immap->im_cpm.cp_pbdir |= 0x00000300;
-#endif /* CONFIG_HMI10 */
-#else
- if ((reg & mask) == mask) {
- puts (" 5.0V card found: ");
- } else {
- puts (" 3.3V card found: ");
- }
-#endif
-#if 0
- /* VCC switch error flag, PCMCIA slot INPACK_ pin */
- cp->cp_pbdir &= ~(0x0020 | 0x0010);
- cp->cp_pbpar &= ~(0x0020 | 0x0010);
- udelay(500000);
-#endif
- udelay(1000);
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
-#ifndef NSCU_OE_INV
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
-#else
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
-#endif
- PCMCIA_PGCRX(slot) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-
-#ifndef CONFIG_HMI10
-#ifndef CONFIG_NSCU
- /* remove all power */
- immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
-#endif
-#else /* CONFIG_HMI10 */
- immap->im_cpm.cp_pbdat |= 0x00000300;
-#endif /* CONFIG_HMI10 */
-
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
-#ifndef NSCU_OE_INV
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
-#endif
- PCMCIA_PGCRX(slot) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif /* CFG_CMD_PCMCIA */
-
-#ifdef CONFIG_NSCU
-static int voltage_set(int slot, int vcc, int vpp)
-{
- return 0;
-}
-#else
-static int voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
-#ifndef NSCU_OE_INV
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
-#else
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
-#endif
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
-#ifndef CONFIG_HMI10
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn off all power
- */
- debug ("PCMCIA power OFF\n");
- immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004);
- immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004);
- immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
-
- reg = 0;
- switch(vcc) {
- case 0: break;
- case 33: reg |= 0x0002; break;
- case 50: reg |= 0x0004; break;
- default: goto done;
- }
-#else /* CONFIG_HMI10 */
- /*
- * Configure Port B pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn off all power
- */
- debug ("PCMCIA power OFF\n");
- immap->im_cpm.cp_pbpar &= ~(0x00000300);
- /* remove all power */
-
- immap->im_cpm.cp_pbdat |= 0x00000300;
-
- reg = 0;
- switch(vcc) {
- case 0: break;
- case 33: reg |= 0x00000200; break;
- case 50: reg |= 0x00000100; break;
- default: goto done;
-}
-#endif /* CONFIG_HMI10 */
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
-#ifndef CONFIG_HMI10
- immap->im_ioport.iop_pcdat |= reg;
- immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
-#else
- immap->im_cpm.cp_pbdat &= !reg;
- immap->im_cpm.cp_pbdir |= 0x00000300;
-#endif /* CONFIG_HMI10 */
- if (reg) {
-#ifndef CONFIG_HMI10
- debug ("PCMCIA powered at %sV\n",
- (reg&0x0004) ? "5.0" : "3.3");
-#else
- debug ("PCMCIA powered at %sV\n",
- (reg&0x00000200) ? "5.0" : "3.3");
-#endif /* CONFIG_HMI10 */
- } else {
- debug ("PCMCIA powered down\n");
- }
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
-#ifndef NSCU_OE_INV
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
-#else
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
-#endif
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-#endif
-
-#endif /* TQM8xxL */
-
-/* -------------------------------------------------------------------- */
-/* Virtlab2 Board by TQ Components */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_VIRTLAB2)
-#define PCMCIA_BOARD_MSG "Virtlab2"
-
-static int hardware_enable(int slot)
-{
- volatile pcmconf8xx_t *pcmp =
- (pcmconf8xx_t *)&(((immap_t *)CFG_IMMR)->im_pcmcia);
- volatile unsigned char *powerctl =
- (volatile unsigned char *)PCMCIA_CTRL;
- volatile sysconf8xx_t *sysp =
- (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- unsigned int reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(slot);
- pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
-
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
- /* remove all power */
- *powerctl = 0;
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- if ((reg & mask) == mask) {
- *powerctl = 2; /* Enable 5V Vccout */
- puts (" 5.0V card found: ");
- } else {
- *powerctl = 1; /* Enable 3.3 V Vccout */
- puts (" 3.3V card found: ");
- }
-
- udelay(1000);
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
-
- PCMCIA_PGCRX(slot) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile unsigned char *powerctl =
- (volatile unsigned char *)PCMCIA_CTRL;
- unsigned long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- /* remove all power */
- *powerctl = 0;
-
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
-
- PCMCIA_PGCRX(slot) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
-#ifdef DEBUG
- volatile pcmconf8xx_t *pcmp =
- (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-#endif
- volatile unsigned char *powerctl =
- (volatile unsigned char *)PCMCIA_CTRL;
- unsigned long reg;
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
-
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
- /*
- * Configure pins for 5 Volts Enable and 3 Volts enable,
- * Turn off all power.
- */
- debug ("PCMCIA power OFF\n");
- reg = 0;
- switch(vcc) {
- case 0: break;
- case 33: reg = 0x0001; break;
- case 50: reg = 0x0002; break;
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n", pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- *powerctl = reg;
-
- if (reg) {
- debug ("PCMCIA powered at %sV\n", (reg&0x0004) ? "5.0" : "3.3");
- } else {
- debug ("PCMCIA powered down\n");
- }
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
-
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
- return (0);
-}
-#endif /* CONFIG_VIRTLAB2 */
-
-/* -------------------------------------------------------------------- */
-/* LWMON Board */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_LWMON)
-
-#define PCMCIA_BOARD_MSG "LWMON"
-
-/* #define's for MAX1604 Power Switch */
-#define MAX1604_OP_SUS 0x80
-#define MAX1604_VCCBON 0x40
-#define MAX1604_VCC_35 0x20
-#define MAX1604_VCCBHIZ 0x10
-#define MAX1604_VPPBON 0x08
-#define MAX1604_VPPBPBPGM 0x04
-#define MAX1604_VPPBHIZ 0x02
-/* reserved 0x01 */
-
-static int hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
- uchar val;
-
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- /* Switch on PCMCIA port in PIC register 0x60 */
- reg = pic_read (0x60);
- debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
- reg &= ~0x10;
- /* reg |= 0x08; Vpp not needed */
- pic_write (0x60, reg);
-#ifdef DEBUG
- reg = pic_read (0x60);
- printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
-#endif
- udelay(10000);
-
- immap = (immap_t *)CFG_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
- if ((reg & mask) == mask) {
- val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */
- puts (" 5.0V card found: ");
- } else {
- val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */
- puts (" 3.3V card found: ");
- }
-
- /* switch VCC on */
- val |= MAX1604_OP_SUS | MAX1604_VCCBON;
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
- i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
-
- udelay(500000);
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
- uchar val;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-
- /* remove all power, put output in high impedance state */
- val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
- i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- /* Switch off PCMCIA port in PIC register 0x60 */
- reg = pic_read (0x60);
- debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
- reg |= 0x10;
- reg &= ~0x08;
- pic_write (0x60, reg);
-#ifdef DEBUG
- reg = pic_read (0x60);
- printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
-#endif
- udelay(10000);
-
- return (0);
-}
-#endif /* CFG_CMD_PCMCIA */
-
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
- uchar val;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Turn off all power (switch to high impedance)
- */
- debug ("PCMCIA power OFF\n");
- val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
- i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
-
- val = 0;
- switch(vcc) {
- case 0: break;
- case 33: val = MAX1604_VCC_35; break;
- case 50: break;
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
- if (val) {
- debug ("PCMCIA powered at %sV\n",
- (val & MAX1604_VCC_35) ? "3.3" : "5.0");
- } else {
- debug ("PCMCIA powered down\n");
- }
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* LWMON */
-
-/* -------------------------------------------------------------------- */
-/* GTH board by Corelatus AB */
-/* -------------------------------------------------------------------- */
-#if defined(CONFIG_GTH)
-
-#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH"
-
-static int voltage_set (int slot, int vcc, int vpp)
-{ /* Do nothing */
- return 0;
-}
-
-static int hardware_enable (int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: GTH Slot %c\n", 'A' + slot);
-
- immap = (immap_t *) CFG_IMMR;
- sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX (_slot_) = reg;
- udelay (500);
-
- /*
- * Make sure there is a card in the slot,
- * then configure the interface.
- */
- udelay (10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__, __FUNCTION__,
- &(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & 0x98000000) {
- printf (" No Card found\n");
- return (1);
- }
-
- mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
- (reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX (_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX (_slot_) = reg;
-
- udelay (250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return 0;
-}
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- return 0; /* No hardware to disable */
-}
-#endif /* CFG_CMD_PCMCIA */
-#endif /* CONFIG_GTH */
-
-/* -------------------------------------------------------------------- */
-/* ICU862 Boards by Cambridge Broadband Ltd. */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_ICU862)
-
-#define PCMCIA_BOARD_MSG "ICU862"
-
-static void cfg_port_B (void);
-
-static int hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, pipr, mask;
- int i;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CFG_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */
- cfg_port_B ();
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- pipr = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- pipr,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- reg = cp->cp_pbdat;
- if ((pipr & mask) == mask) {
- reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
- TPS2205_VCC3); /* 3V off */
- reg &= ~(TPS2205_VCC5); /* 5V on */
- puts (" 5.0V card found: ");
- } else {
- reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
- TPS2205_VCC5); /* 5V off */
- reg &= ~(TPS2205_VCC3); /* 3V on */
- puts (" 3.3V card found: ");
- }
-
- debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n",
- reg,
- (reg & TPS2205_VCC3) ? "off" : "on",
- (reg & TPS2205_VCC5) ? "off" : "on",
- (reg & TPS2205_VPP_PGM) ? "off" : "on",
- (reg & TPS2205_VPP_VCC) ? "off" : "on" );
-
- cp->cp_pbdat = reg;
-
- /* Wait 500 ms; use this to check for over-current */
- for (i=0; i<5000; ++i) {
- if ((cp->cp_pbdat & TPS2205_OC) == 0) {
- printf (" *** Overcurrent - Safety shutdown ***\n");
- cp->cp_pbdat &= ~(TPS2205_SHDN);
- return (1);
- }
- udelay (100);
- }
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CFG_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-
- /* Shut down */
- cp->cp_pbdat &= ~(TPS2205_SHDN);
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif /* CFG_CMD_PCMCIA */
-
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CFG_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_port_B (); /* Enables switch, but all in Hi-Z */
-
- reg = cp->cp_pbdat;
-
- switch(vcc) {
- case 0: break; /* Switch off */
- case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */
- case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- cp->cp_pbdat = reg;
-
-#ifdef DEBUG
- {
- char *s;
-
- if ((reg & TPS2205_VCC3) == 0) {
- s = "at 3.3V";
- } else if ((reg & TPS2205_VCC5) == 0) {
- s = "at 5.0V";
- } else {
- s = "down";
- }
- printf ("PCMCIA powered %s\n", s);
- }
-#endif
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-static void cfg_port_B (void)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- uint reg;
-
- immap = (immap_t *)CFG_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /*
- * Configure Port B for TPS2205 PC-Card Power-Interface Switch
- *
- * Switch off all voltages, assert shutdown
- */
- reg = cp->cp_pbdat;
- reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
- TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */
- TPS2205_SHDN); /* enable switch */
- cp->cp_pbdat = reg;
-
- cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS);
-
- reg = cp->cp_pbdir & ~(TPS2205_INPUTS);
- cp->cp_pbdir = reg | TPS2205_OUTPUTS;
-
- debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
- cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
-}
-
-#endif /* ICU862 */
-
-
-/* -------------------------------------------------------------------- */
-/* C2MON Boards by TTTech Computertechnik AG */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_C2MON)
-
-#define PCMCIA_BOARD_MSG "C2MON"
-
-static void cfg_ports (void);
-
-static int hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, pipr, mask;
- ushort sreg;
- int i;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CFG_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
- cfg_ports ();
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- pipr = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- pipr,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- sreg = immap->im_ioport.iop_pcdat;
- if ((pipr & mask) == mask) {
- sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
- TPS2211_VCCD1); /* 5V on */
- sreg &= ~(TPS2211_VCCD0); /* 3V off */
- puts (" 5.0V card found: ");
- } else {
- sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
- TPS2211_VCCD0); /* 3V on */
- sreg &= ~(TPS2211_VCCD1); /* 5V off */
- puts (" 3.3V card found: ");
- }
-
- debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n",
- sreg,
- ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off",
- (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off"
- );
-
- immap->im_ioport.iop_pcdat = sreg;
-
- /* Wait 500 ms; use this to check for over-current */
- for (i=0; i<5000; ++i) {
- if ((cp->cp_pbdat & TPS2211_OC) == 0) {
- printf (" *** Overcurrent - Safety shutdown ***\n");
- immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1);
- return (1);
- }
- udelay (100);
- }
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- /* ALl voltages off / Hi-Z */
- immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 |
- TPS2211_VCCD0 | TPS2211_VCCD1 );
-
- udelay(10000);
-
- return (0);
-}
-#endif /* CFG_CMD_PCMCIA */
-
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
- ushort sreg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CFG_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_ports (); /* Enables switch, but all in Hi-Z */
-
- sreg = immap->im_ioport.iop_pcdat;
- sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */
-
- switch(vcc) {
- case 0: break; /* Switch off */
- case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */
- sreg &= ~TPS2211_VCCD1;
- break;
- case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */
- sreg |= TPS2211_VCCD1;
- break;
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- immap->im_ioport.iop_pcdat = sreg;
-
-#ifdef DEBUG
- {
- char *s;
-
- if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) {
- s = "at 3.3V";
- } else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) {
- s = "at 5.0V";
- } else {
- s = "down";
- }
- printf ("PCMCIA powered %s\n", s);
- }
-#endif
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-static void cfg_ports (void)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- ushort sreg;
-
- immap = (immap_t *)CFG_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /*
- * Configure Port C for TPS2211 PC-Card Power-Interface Switch
- *
- * Switch off all voltages, assert shutdown
- */
- sreg = immap->im_ioport.iop_pcdat;
- sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */
- sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */
- immap->im_ioport.iop_pcdat = sreg;
-
- immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS);
- immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS;
-
- debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n",
- immap->im_ioport.iop_pcpar,
- immap->im_ioport.iop_pcdir,
- immap->im_ioport.iop_pcdat);
-
- /*
- * Configure Port B for TPS2211 PC-Card Power-Interface Switch
- *
- * Over-Current Input only
- */
- cp->cp_pbpar &= ~(TPS2211_INPUTS);
- cp->cp_pbdir &= ~(TPS2211_INPUTS);
-
- debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
- cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
-}
-
-#endif /* C2MON */
-
-/* -------------------------------------------------------------------- */
-/* MBX board from Morotola */
-/* -------------------------------------------------------------------- */
-
-#if defined( CONFIG_MBX )
-#include <../board/mbx8xx/csr.h>
-
-/* A lot of this has been taken from the RPX code in this file it works from me.
- I have added the voltage selection for the MBX board. */
-
-/* MBX voltage bit in control register #2 */
-#define CR2_VPP12 ((uchar)0x10)
-#define CR2_VPPVDD ((uchar)0x20)
-#define CR2_VDD5 ((uchar)0x40)
-#define CR2_VDD3 ((uchar)0x80)
-
-#define PCMCIA_BOARD_MSG "MBX860"
-
-static int voltage_set (int slot, int vcc, int vpp)
-{
- uchar reg = 0;
-
- debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10);
-
- switch (vcc) {
- case 0:
- break;
- case 33:
- reg |= CR2_VDD3;
- break;
- case 50:
- reg |= CR2_VDD5;
- break;
- default:
- return 1;
- }
-
- switch (vpp) {
- case 0:
- break;
- case 33:
- case 50:
- if (vcc == vpp) {
- reg |= CR2_VPPVDD;
- } else {
- return 1;
- }
- break;
- case 120:
- reg |= CR2_VPP12;
- break;
- default:
- return 1;
- }
-
- /* first, turn off all power */
- MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL);
-
- /* enable new powersettings */
- MBX_CSR2 |= reg;
- debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2);
-
- return (0);
-}
-
-static int hardware_enable (int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n",
- 'A' + slot);
-
- udelay (10000);
-
- immap = (immap_t *) CFG_IMMR;
- sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX (_slot_) = reg;
- udelay (500);
-
- /* remove all power */
- voltage_set (slot, 0, 0);
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-#ifndef CONFIG_HMI10
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
-#else
- if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
-#endif /* CONFIG_HMI10 */
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
- (reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
- (reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
-
- if ((reg & mask) == mask) {
- voltage_set (_slot_, 50, 0);
- printf (" 5.0V card found: ");
- } else {
- voltage_set (_slot_, 33, 0);
- printf (" 3.3V card found: ");
- }
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX (_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX (_slot_) = reg;
-
- udelay (250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable (int slot)
-{
- return 0; /* No hardware to disable */
-}
-#endif /* CFG_CMD_PCMCIA */
-#endif /* CONFIG_MBX */
-/* -------------------------------------------------------------------- */
-/* R360MPI Board */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_R360MPI)
-
-#define PCMCIA_BOARD_MSG "R360MPI"
-
-
-static int hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CFG_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Ports A, B & C pins for
- * 5 Volts Enable and 3 Volts enable
- */
- immap->im_ioport.iop_pcpar &= ~(0x0400);
- immap->im_ioport.iop_pcso &= ~(0x0400);/*
- immap->im_ioport.iop_pcdir |= 0x0400;*/
-
- immap->im_ioport.iop_papar &= ~(0x0200);/*
- immap->im_ioport.iop_padir |= 0x0200;*/
-#if 0
- immap->im_ioport.iop_pbpar &= ~(0xC000);
- immap->im_ioport.iop_pbdir &= ~(0xC000);
-#endif
- /* remove all power */
-
- immap->im_ioport.iop_pcdat |= 0x0400;
- immap->im_ioport.iop_padat |= 0x0200;
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
- if ((reg & mask) == mask) {
- immap->im_ioport.iop_pcdat &= ~(0x4000);
- puts (" 5.0V card found: ");
- } else {
- immap->im_ioport.iop_padat &= ~(0x0002);
- puts (" 3.3V card found: ");
- }
- immap->im_ioport.iop_pcdir |= 0x0400;
- immap->im_ioport.iop_padir |= 0x0200;
-#if 0
- /* VCC switch error flag, PCMCIA slot INPACK_ pin */
- cp->cp_pbdir &= ~(0x0020 | 0x0010);
- cp->cp_pbpar &= ~(0x0020 | 0x0010);
- udelay(500000);
-#endif
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-
- /* remove all power */
- immap->im_ioport.iop_pcdat |= 0x0400;
- immap->im_ioport.iop_padat |= 0x0200;
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif /* CFG_CMD_PCMCIA */
-
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Ports A & C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn off all power
- */
- debug ("PCMCIA power OFF\n");
- immap->im_ioport.iop_pcpar &= ~(0x0400);
- immap->im_ioport.iop_pcso &= ~(0x0400);/*
- immap->im_ioport.iop_pcdir |= 0x0400;*/
-
- immap->im_ioport.iop_papar &= ~(0x0200);/*
- immap->im_ioport.iop_padir |= 0x0200;*/
-
- immap->im_ioport.iop_pcdat |= 0x0400;
- immap->im_ioport.iop_padat |= 0x0200;
-
- reg = 0;
- switch(vcc) {
- case 0: break;
- case 33: reg |= 0x0200; break;
- case 50: reg |= 0x0400; break;
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- if (reg & 0x0200)
- immap->im_ioport.iop_pcdat &= !reg;
- if (reg & 0x0400)
- immap->im_ioport.iop_padat &= !reg;
- immap->im_ioport.iop_pcdir |= 0x0200;
- immap->im_ioport.iop_padir |= 0x0400;
- if (reg) {
- debug ("PCMCIA powered at %sV\n",
- (reg&0x0400) ? "5.0" : "3.3");
- } else {
- debug ("PCMCIA powered down\n");
- }
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* R360MPI */
-
-/* -------------------------------------------------------------------- */
-/* KUP4K and KUP4X Boards */
-/* -------------------------------------------------------------------- */
-#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
-
-#define PCMCIA_BOARD_MSG "KUP"
-
-#define KUP4K_PCMCIA_B_3V3 (0x00020000)
-
-static int hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CFG_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(slot);
- pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
- udelay(2500);
-
- /*
- * Configure Port B pins for
- * 3 Volts enable
- */
- if (slot) { /* Slot A is built-in */
- cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
- cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
- /* remove all power */
- cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
- }
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot);
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
- if ((reg & mask) == mask) {
- puts (" 5.0V card found: NOT SUPPORTED !!!\n");
- } else {
- if(slot)
- cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
- puts (" 3.3V card found: ");
- }
-#if 0
- /* VCC switch error flag, PCMCIA slot INPACK_ pin */
- cp->cp_pbdir &= ~(0x0020 | 0x0010);
- cp->cp_pbpar &= ~(0x0020 | 0x0010);
- udelay(500000);
-#endif
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /* remove all power */
- if (slot)
- cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif /* CFG_CMD_PCMCIA */
-
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: " \
- PCMCIA_BOARD_MSG \
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- if (!slot) /* Slot A is not configurable */
- return 0;
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
- debug ("PCMCIA power OFF\n");
- /*
- * Configure Port B pins for
- * 3 Volts enable
- */
- cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
- cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
- /* remove all power */
- cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
-
- switch(vcc) {
- case 0: break;
- case 33:
- cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
- debug ("PCMCIA powered at 3.3V\n");
- break;
- case 50:
- debug ("PCMCIA: 5Volt vcc not supported\n");
- break;
- default:
- puts("PCMCIA: vcc not supported");
- break;
- }
- udelay(10000);
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
- ? "only 5 V --> NOT SUPPORTED"
- : "can do 3.3V");
-
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* KUP4K || KUP4X */
-
-
-/* -------------------------------------------------------------------- */
-/* End of Board Specific Stuff */
-/* -------------------------------------------------------------------- */
-
-
-/* -------------------------------------------------------------------- */
-/* MPC8xx Specific Stuff - should go to MPC8xx directory */
-/* -------------------------------------------------------------------- */
-
-/*
- * Search this table to see if the windowsize is
- * supported...
- */
-
-#define M8XX_SIZES_NO 32
-
-static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
-{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
- 0x00000080, 0x00000040, 0x00000010, 0x00000020,
- 0x00008000, 0x00004000, 0x00001000, 0x00002000,
- 0x00000100, 0x00000200, 0x00000800, 0x00000400,
-
- 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
- 0x00010000, 0x00020000, 0x00080000, 0x00040000,
- 0x00800000, 0x00400000, 0x00100000, 0x00200000 };
-
-
-/* -------------------------------------------------------------------- */
-
-#if ( ! defined(CONFIG_I82365) && ! defined(CONFIG_PXA_PCMCIA) )
-
-static u_int m8xx_get_graycode(u_int size)
-{
- u_int k;
-
- for (k = 0; k < M8XX_SIZES_NO; k++) {
- if(m8xx_size_to_gray[k] == size)
- break;
- }
-
- if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
- k = -1;
-
- return k;
-}
-
-#endif /* CONFIG_I82365 */
-
-/* -------------------------------------------------------------------- */
-
-#if 0
-static u_int m8xx_get_speed(u_int ns, u_int is_io)
-{
- u_int reg, clocks, psst, psl, psht;
-
- if(!ns) {
-
- /*
- * We get called with IO maps setup to 0ns
- * if not specified by the user.
- * They should be 255ns.
- */
-
- if(is_io)
- ns = 255;
- else
- ns = 100; /* fast memory if 0 */
- }
-
- /*
- * In PSST, PSL, PSHT fields we tell the controller
- * timing parameters in CLKOUT clock cycles.
- * CLKOUT is the same as GCLK2_50.
- */
-
-/* how we want to adjust the timing - in percent */
-
-#define ADJ 180 /* 80 % longer accesstime - to be sure */
-
- clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
- clocks = (clocks * ADJ) / (100*1000);
-
- if(clocks >= PCMCIA_BMT_LIMIT) {
- DEBUG(0, "Max access time limit reached\n");
- clocks = PCMCIA_BMT_LIMIT-1;
- }
-
- psst = clocks / 7; /* setup time */
- psht = clocks / 7; /* hold time */
- psl = (clocks * 5) / 7; /* strobe length */
-
- psst += clocks - (psst + psht + psl);
-
- reg = psst << 12;
- reg |= psl << 7;
- reg |= psht << 16;
-
- return reg;
-}
-#endif
-
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
-static void print_funcid (int func)
-{
- puts (indent);
- switch (func) {
- case CISTPL_FUNCID_MULTI:
- puts (" Multi-Function");
- break;
- case CISTPL_FUNCID_MEMORY:
- puts (" Memory");
- break;
- case CISTPL_FUNCID_SERIAL:
- puts (" Serial Port");
- break;
- case CISTPL_FUNCID_PARALLEL:
- puts (" Parallel Port");
- break;
- case CISTPL_FUNCID_FIXED:
- puts (" Fixed Disk");
- break;
- case CISTPL_FUNCID_VIDEO:
- puts (" Video Adapter");
- break;
- case CISTPL_FUNCID_NETWORK:
- puts (" Network Adapter");
- break;
- case CISTPL_FUNCID_AIMS:
- puts (" AIMS Card");
- break;
- case CISTPL_FUNCID_SCSI:
- puts (" SCSI Adapter");
- break;
- default:
- puts (" Unknown");
- break;
- }
- puts (" Card\n");
-}
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
-static void print_fixed (volatile uchar *p)
-{
- if (p == NULL)
- return;
-
- puts(indent);
-
- switch (*p) {
- case CISTPL_FUNCE_IDE_IFACE:
- { uchar iface = *(p+2);
-
- puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
- puts (" interface ");
- break;
- }
- case CISTPL_FUNCE_IDE_MASTER:
- case CISTPL_FUNCE_IDE_SLAVE:
- { uchar f1 = *(p+2);
- uchar f2 = *(p+4);
-
- puts ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
-
- if (f1 & CISTPL_IDE_UNIQUE)
- puts (" [unique]");
-
- puts ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
-
- if (f2 & CISTPL_IDE_HAS_SLEEP)
- puts (" [sleep]");
-
- if (f2 & CISTPL_IDE_HAS_STANDBY)
- puts (" [standby]");
-
- if (f2 & CISTPL_IDE_HAS_IDLE)
- puts (" [idle]");
-
- if (f2 & CISTPL_IDE_LOW_POWER)
- puts (" [low power]");
-
- if (f2 & CISTPL_IDE_REG_INHIBIT)
- puts (" [reg inhibit]");
-
- if (f2 & CISTPL_IDE_HAS_INDEX)
- puts (" [index]");
-
- if (f2 & CISTPL_IDE_IOIS16)
- puts (" [IOis16]");
-
- break;
- }
- }
- putc ('\n');
-}
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
-
-#define MAX_IDENT_CHARS 64
-#define MAX_IDENT_FIELDS 4
-
-static uchar *known_cards[] = {
- (uchar *)"ARGOSY PnPIDE D5",
- NULL
-};
-
-static int identify (volatile uchar *p)
-{
- uchar id_str[MAX_IDENT_CHARS];
- uchar data;
- uchar *t;
- uchar **card;
- int i, done;
-
- if (p == NULL)
- return (0); /* Don't know */
-
- t = id_str;
- done =0;
-
- for (i=0; i<=4 && !done; ++i, p+=2) {
- while ((data = *p) != '\0') {
- if (data == 0xFF) {
- done = 1;
- break;
- }
- *t++ = data;
- if (t == &id_str[MAX_IDENT_CHARS-1]) {
- done = 1;
- break;
- }
- p += 2;
- }
- if (!done)
- *t++ = ' ';
- }
- *t = '\0';
- while (--t > id_str) {
- if (*t == ' ')
- *t = '\0';
- else
- break;
- }
- puts ((char *)id_str);
- putc ('\n');
-
- for (card=known_cards; *card; ++card) {
- debug ("## Compare against \"%s\"\n", *card);
- if (strcmp((char *)*card, (char *)id_str) == 0) { /* found! */
- debug ("## CARD FOUND ##\n");
- return (1);
- }
- }
-
- return (0); /* don't know */
-}
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
-/* -------------------------------------------------------------------- */
-/* NETTA board by Intracom S.A. */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_NETTA)
-
-/* some sane bit macros */
-#define _BD(_b) (1U << (31-(_b)))
-#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b) (1U << (15-(_b)))
-#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b) (1U << (7-(_b)))
-#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b) _BD(_b)
-#define _BR(_l, _h) _BDR(_l, _h)
-
-#define PCMCIA_BOARD_MSG "NETTA"
-
-static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
-
-static void cfg_vppd(int no)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- unsigned short mask;
-
- if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
- return;
-
- mask = vppd_masks[no];
-
- immap->im_ioport.iop_papar &= ~mask;
- immap->im_ioport.iop_paodr &= ~mask;
- immap->im_ioport.iop_padir |= mask;
-}
-
-static void set_vppd(int no, int what)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- unsigned short mask;
-
- if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
- return;
-
- mask = vppd_masks[no];
-
- if (what)
- immap->im_ioport.iop_padat |= mask;
- else
- immap->im_ioport.iop_padat &= ~mask;
-}
-
-static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
-
-static void cfg_vccd(int no)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- unsigned short mask;
-
- if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
- return;
-
- mask = vccd_masks[no];
-
- immap->im_ioport.iop_papar &= ~mask;
- immap->im_ioport.iop_paodr &= ~mask;
- immap->im_ioport.iop_padir |= mask;
-}
-
-static void set_vccd(int no, int what)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- unsigned short mask;
-
- if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
- return;
-
- mask = vccd_masks[no];
-
- if (what)
- immap->im_ioport.iop_padat |= mask;
- else
- immap->im_ioport.iop_padat &= ~mask;
-}
-
-static const unsigned short oc_mask = _BW(8);
-
-static void cfg_oc(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- unsigned short mask = oc_mask;
-
- immap->im_ioport.iop_pcdir &= ~mask;
- immap->im_ioport.iop_pcso &= ~mask;
- immap->im_ioport.iop_pcint &= ~mask;
- immap->im_ioport.iop_pcpar &= ~mask;
-}
-
-static int get_oc(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- unsigned short mask = oc_mask;
- int what;
-
- what = !!(immap->im_ioport.iop_pcdat & mask);;
- return what;
-}
-
-static const unsigned short shdn_mask = _BW(12);
-
-static void cfg_shdn(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- unsigned short mask;
-
- mask = shdn_mask;
-
- immap->im_ioport.iop_papar &= ~mask;
- immap->im_ioport.iop_paodr &= ~mask;
- immap->im_ioport.iop_padir |= mask;
-}
-
-static void set_shdn(int what)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- unsigned short mask;
-
- mask = shdn_mask;
-
- if (what)
- immap->im_ioport.iop_padat |= mask;
- else
- immap->im_ioport.iop_padat &= ~mask;
-}
-
-static void cfg_ports (void);
-
-static int hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, pipr, mask;
- int i;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CFG_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
- cfg_ports ();
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- pipr = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- pipr,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- if ((pipr & mask) == mask) {
- set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
- set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */
- puts (" 5.0V card found: ");
- } else {
- set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
- set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */
- puts (" 3.3V card found: ");
- }
-
- /* Wait 500 ms; use this to check for over-current */
- for (i=0; i<5000; ++i) {
- if (!get_oc()) {
- printf (" *** Overcurrent - Safety shutdown ***\n");
- set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */
- return (1);
- }
- udelay (100);
- }
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- /* All voltages off / Hi-Z */
- set_vppd(0, 1); set_vppd(1, 1);
- set_vccd(0, 1); set_vccd(1, 1);
-
- udelay(10000);
-
- return (0);
-}
-#endif /* CFG_CMD_PCMCIA */
-
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
- ushort sreg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CFG_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_ports (); /* Enables switch, but all in Hi-Z */
-
- sreg = immap->im_ioport.iop_pcdat;
- set_vppd(0, 1); set_vppd(1, 1);
-
- switch(vcc) {
- case 0:
- break; /* Switch off */
-
- case 33:
- set_vccd(0, 1); set_vccd(1, 0);
- break;
-
- case 50:
- set_vccd(0, 0); set_vccd(1, 1);
- break;
-
- default:
- goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-static void cfg_ports (void)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
-
- immap = (immap_t *)CFG_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
-
- cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */
- cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */
- cfg_shdn();
- cfg_oc();
-
- /*
- * Configure Port A for TPS2211 PC-Card Power-Interface Switch
- *
- * Switch off all voltages, assert shutdown
- */
- set_vppd(0, 1); set_vppd(1, 1);
- set_vccd(0, 0); set_vccd(1, 0);
- set_shdn(1);
-
- udelay(100000);
-}
-
-#endif /* NETTA */
-
-
-/* -------------------------------------------------------------------- */
-/* UC100 Boards */
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_UC100)
-
-#define PCMCIA_BOARD_MSG "UC100"
-
-/*
- * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board.
- * This leads to board-hangup! (sr, 8 Dez. 2004)
- */
-
-static void cfg_ports (void);
-
-static int hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CFG_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-
- /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
- cfg_ports ();
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
- if ((reg & mask) == mask) {
- puts (" 5.0V card found: ");
- } else {
- puts (" 3.3V card found: ");
- }
-
- /* switch VCC on */
- immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
-
- udelay(10000);
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static int hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-
- /* switch VCC off */
- immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif /* CFG_CMD_PCMCIA */
-
-
-static int voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CFG_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_ports (); /* Enables switch, but all in Hi-Z */
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-static void cfg_ports (void)
-{
- volatile immap_t *immap;
-
- immap = (immap_t *)CFG_IMMR;
-
- /*
- * Configure Port A for MAX1602 PC-Card Power-Interface Switch
- */
- immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */
- immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */
-
- debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n",
- immap->im_ioport.iop_papar, immap->im_ioport.iop_padir,
- immap->im_ioport.iop_padat);
-}
-
-#endif /* UC100 */
-
-
-/* -------------------------------------------------------------------- */
-
-#endif /* CFG_CMD_PCMCIA || (CFG_CMD_IDE && CONFIG_IDE_8xx_PCCARD) */
-
-/**************************************************/
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-U_BOOT_CMD(
- pinit, 2, 1, do_pinit,
- "pinit - PCMCIA sub-system\n",
- "on - power on PCMCIA socket\n"
- "pinit off - power off PCMCIA socket\n"
-);
-#endif
+#endif /* CHECK_IDE_DEVICE */
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index 15ac16a..f428f7e 100644
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -328,7 +328,7 @@
(*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
printf ("\tSDRAMCS0: %08X\n",
*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
- printf ("\tSDRAMCS0: %08X\n",
+ printf ("\tSDRAMCS1: %08X\n",
*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#endif /* CONFIG_MPC5200 */
return 0;
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index fdfd042..28c05aa 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -186,7 +186,7 @@
void usb_display_if_desc(struct usb_interface_descriptor *ifdesc,struct usb_device *dev)
{
printf(" Interface: %d\n",ifdesc->bInterfaceNumber);
- printf(" - Alternate Settings %d, Endpoints: %d\n",ifdesc->bAlternateSetting,ifdesc->bNumEndpoints);
+ printf(" - Alternate Setting %d, Endpoints: %d\n",ifdesc->bAlternateSetting,ifdesc->bNumEndpoints);
printf(" - Class ");
usb_display_class_sub(ifdesc->bInterfaceClass,ifdesc->bInterfaceSubClass,ifdesc->bInterfaceProtocol);
printf("\n");
@@ -444,6 +444,7 @@
int i;
struct usb_device *dev = NULL;
+ extern char usb_started;
#ifdef CONFIG_USB_STORAGE
block_dev_desc_t *stor_dev;
#endif
@@ -477,6 +478,10 @@
usb_stop();
return 0;
}
+ if (!usb_started) {
+ printf("USB is stopped. Please issue 'usb start' first.\n");
+ return 1;
+ }
if (strncmp(argv[1],"tree",4) == 0) {
printf("\nDevice Tree:\n");
usb_show_tree(usb_get_dev_index(0));
diff --git a/common/crc16.c b/common/crc16.c
index 3cef106..6904365 100644
--- a/common/crc16.c
+++ b/common/crc16.c
@@ -101,7 +101,7 @@
cksum = 0;
for (i = 0; i < len; i++) {
- cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8);
+ cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8);
}
return cksum;
}
diff --git a/common/main.c b/common/main.c
index 758ef8d..3788bd5 100644
--- a/common/main.c
+++ b/common/main.c
@@ -2,6 +2,10 @@
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * Add to readline cmdline-editing by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -49,7 +53,6 @@
#define MAX_DELAY_STOP_STR 32
-static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
static int parse_line (char *, char *[]);
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
static int abortboot(int);
@@ -59,8 +62,11 @@
char console_buffer[CFG_CBSIZE]; /* console I/O buffer */
+#ifndef CONFIG_CMDLINE_EDITING
+static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
static char erase_seq[] = "\b \b"; /* erase sequence */
static char tab_seq[] = " "; /* used to expand TABs */
+#endif /* CONFIG_CMDLINE_EDITING */
#ifdef CONFIG_BOOT_RETRY_TIME
static uint64_t endtime = 0; /* must be set, default is instant timeout */
@@ -516,6 +522,406 @@
}
#endif
+#ifdef CONFIG_CMDLINE_EDITING
+
+/*
+ * cmdline-editing related codes from vivi.
+ * Author: Janghoon Lyu <nandy@mizi.com>
+ */
+
+#if 1 /* avoid redundand code -- wd */
+#define putnstr(str,n) do { \
+ printf ("%.*s", n, str); \
+ } while (0)
+#else
+void putnstr(const char *str, size_t n)
+{
+ if (str == NULL)
+ return;
+
+ while (n && *str != '\0') {
+ putc(*str);
+ str++;
+ n--;
+ }
+}
+#endif
+
+#define CTL_CH(c) ((c) - 'a' + 1)
+
+#define MAX_CMDBUF_SIZE 256
+
+#define CTL_BACKSPACE ('\b')
+#define DEL ((char)255)
+#define DEL7 ((char)127)
+#define CREAD_HIST_CHAR ('!')
+
+#define getcmd_putch(ch) putc(ch)
+#define getcmd_getch() getc()
+#define getcmd_cbeep() getcmd_putch('\a')
+
+#define HIST_MAX 20
+#define HIST_SIZE MAX_CMDBUF_SIZE
+
+static int hist_max = 0;
+static int hist_add_idx = 0;
+static int hist_cur = -1;
+unsigned hist_num = 0;
+
+char* hist_list[HIST_MAX];
+char hist_lines[HIST_MAX][HIST_SIZE];
+
+#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
+
+static void hist_init(void)
+{
+ int i;
+
+ hist_max = 0;
+ hist_add_idx = 0;
+ hist_cur = -1;
+ hist_num = 0;
+
+ for (i = 0; i < HIST_MAX; i++) {
+ hist_list[i] = hist_lines[i];
+ hist_list[i][0] = '\0';
+ }
+}
+
+static void cread_add_to_hist(char *line)
+{
+ strcpy(hist_list[hist_add_idx], line);
+
+ if (++hist_add_idx >= HIST_MAX)
+ hist_add_idx = 0;
+
+ if (hist_add_idx > hist_max)
+ hist_max = hist_add_idx;
+
+ hist_num++;
+}
+
+static char* hist_prev(void)
+{
+ char *ret;
+ int old_cur;
+
+ if (hist_cur < 0)
+ return NULL;
+
+ old_cur = hist_cur;
+ if (--hist_cur < 0)
+ hist_cur = hist_max;
+
+ if (hist_cur == hist_add_idx) {
+ hist_cur = old_cur;
+ ret = NULL;
+ } else
+ ret = hist_list[hist_cur];
+
+ return (ret);
+}
+
+static char* hist_next(void)
+{
+ char *ret;
+
+ if (hist_cur < 0)
+ return NULL;
+
+ if (hist_cur == hist_add_idx)
+ return NULL;
+
+ if (++hist_cur > hist_max)
+ hist_cur = 0;
+
+ if (hist_cur == hist_add_idx) {
+ ret = "";
+ } else
+ ret = hist_list[hist_cur];
+
+ return (ret);
+}
+
+#ifndef CONFIG_CMDLINE_EDITING
+static void cread_print_hist_list(void)
+{
+ int i;
+ unsigned long n;
+
+ n = hist_num - hist_max;
+
+ i = hist_add_idx + 1;
+ while (1) {
+ if (i > hist_max)
+ i = 0;
+ if (i == hist_add_idx)
+ break;
+ printf("%s\n", hist_list[i]);
+ n++;
+ i++;
+ }
+}
+#endif /* CONFIG_CMDLINE_EDITING */
+
+#define BEGINNING_OF_LINE() { \
+ while (num) { \
+ getcmd_putch(CTL_BACKSPACE); \
+ num--; \
+ } \
+}
+
+#define ERASE_TO_EOL() { \
+ if (num < eol_num) { \
+ int tmp; \
+ for (tmp = num; tmp < eol_num; tmp++) \
+ getcmd_putch(' '); \
+ while (tmp-- > num) \
+ getcmd_putch(CTL_BACKSPACE); \
+ eol_num = num; \
+ } \
+}
+
+#define REFRESH_TO_EOL() { \
+ if (num < eol_num) { \
+ wlen = eol_num - num; \
+ putnstr(buf + num, wlen); \
+ num = eol_num; \
+ } \
+}
+
+static void cread_add_char(char ichar, int insert, unsigned long *num,
+ unsigned long *eol_num, char *buf, unsigned long len)
+{
+ unsigned long wlen;
+
+ /* room ??? */
+ if (insert || *num == *eol_num) {
+ if (*eol_num > len - 1) {
+ getcmd_cbeep();
+ return;
+ }
+ (*eol_num)++;
+ }
+
+ if (insert) {
+ wlen = *eol_num - *num;
+ if (wlen > 1) {
+ memmove(&buf[*num+1], &buf[*num], wlen-1);
+ }
+
+ buf[*num] = ichar;
+ putnstr(buf + *num, wlen);
+ (*num)++;
+ while (--wlen) {
+ getcmd_putch(CTL_BACKSPACE);
+ }
+ } else {
+ /* echo the character */
+ wlen = 1;
+ buf[*num] = ichar;
+ putnstr(buf + *num, wlen);
+ (*num)++;
+ }
+}
+
+static void cread_add_str(char *str, int strsize, int insert, unsigned long *num,
+ unsigned long *eol_num, char *buf, unsigned long len)
+{
+ while (strsize--) {
+ cread_add_char(*str, insert, num, eol_num, buf, len);
+ str++;
+ }
+}
+
+static int cread_line(char *buf, unsigned int *len)
+{
+ unsigned long num = 0;
+ unsigned long eol_num = 0;
+ unsigned long rlen;
+ unsigned long wlen;
+ char ichar;
+ int insert = 1;
+ int esc_len = 0;
+ int rc = 0;
+ char esc_save[8];
+
+ while (1) {
+ rlen = 1;
+ ichar = getcmd_getch();
+
+ if ((ichar == '\n') || (ichar == '\r')) {
+ putc('\n');
+ break;
+ }
+
+ /*
+ * handle standard linux xterm esc sequences for arrow key, etc.
+ */
+ if (esc_len != 0) {
+ if (esc_len == 1) {
+ if (ichar == '[') {
+ esc_save[esc_len] = ichar;
+ esc_len = 2;
+ } else {
+ cread_add_str(esc_save, esc_len, insert,
+ &num, &eol_num, buf, *len);
+ esc_len = 0;
+ }
+ continue;
+ }
+
+ switch (ichar) {
+
+ case 'D': /* <- key */
+ ichar = CTL_CH('b');
+ esc_len = 0;
+ break;
+ case 'C': /* -> key */
+ ichar = CTL_CH('f');
+ esc_len = 0;
+ break; /* pass off to ^F handler */
+ case 'H': /* Home key */
+ ichar = CTL_CH('a');
+ esc_len = 0;
+ break; /* pass off to ^A handler */
+ case 'A': /* up arrow */
+ ichar = CTL_CH('p');
+ esc_len = 0;
+ break; /* pass off to ^P handler */
+ case 'B': /* down arrow */
+ ichar = CTL_CH('n');
+ esc_len = 0;
+ break; /* pass off to ^N handler */
+ default:
+ esc_save[esc_len++] = ichar;
+ cread_add_str(esc_save, esc_len, insert,
+ &num, &eol_num, buf, *len);
+ esc_len = 0;
+ continue;
+ }
+ }
+
+ switch (ichar) {
+ case 0x1b:
+ if (esc_len == 0) {
+ esc_save[esc_len] = ichar;
+ esc_len = 1;
+ } else {
+ puts("impossible condition #876\n");
+ esc_len = 0;
+ }
+ break;
+
+ case CTL_CH('a'):
+ BEGINNING_OF_LINE();
+ break;
+ case CTL_CH('c'): /* ^C - break */
+ *buf = '\0'; /* discard input */
+ return (-1);
+ case CTL_CH('f'):
+ if (num < eol_num) {
+ getcmd_putch(buf[num]);
+ num++;
+ }
+ break;
+ case CTL_CH('b'):
+ if (num) {
+ getcmd_putch(CTL_BACKSPACE);
+ num--;
+ }
+ break;
+ case CTL_CH('d'):
+ if (num < eol_num) {
+ wlen = eol_num - num - 1;
+ if (wlen) {
+ memmove(&buf[num], &buf[num+1], wlen);
+ putnstr(buf + num, wlen);
+ }
+
+ getcmd_putch(' ');
+ do {
+ getcmd_putch(CTL_BACKSPACE);
+ } while (wlen--);
+ eol_num--;
+ }
+ break;
+ case CTL_CH('k'):
+ ERASE_TO_EOL();
+ break;
+ case CTL_CH('e'):
+ REFRESH_TO_EOL();
+ break;
+ case CTL_CH('o'):
+ insert = !insert;
+ break;
+ case CTL_CH('x'):
+ BEGINNING_OF_LINE();
+ ERASE_TO_EOL();
+ break;
+ case DEL:
+ case DEL7:
+ case 8:
+ if (num) {
+ wlen = eol_num - num;
+ num--;
+ memmove(&buf[num], &buf[num+1], wlen);
+ getcmd_putch(CTL_BACKSPACE);
+ putnstr(buf + num, wlen);
+ getcmd_putch(' ');
+ do {
+ getcmd_putch(CTL_BACKSPACE);
+ } while (wlen--);
+ eol_num--;
+ }
+ break;
+ case CTL_CH('p'):
+ case CTL_CH('n'):
+ {
+ char * hline;
+
+ esc_len = 0;
+
+ if (ichar == CTL_CH('p'))
+ hline = hist_prev();
+ else
+ hline = hist_next();
+
+ if (!hline) {
+ getcmd_cbeep();
+ continue;
+ }
+
+ /* nuke the current line */
+ /* first, go home */
+ BEGINNING_OF_LINE();
+
+ /* erase to end of line */
+ ERASE_TO_EOL();
+
+ /* copy new line into place and display */
+ strcpy(buf, hline);
+ eol_num = strlen(buf);
+ REFRESH_TO_EOL();
+ continue;
+ }
+ default:
+ cread_add_char(ichar, insert, &num, &eol_num, buf, *len);
+ break;
+ }
+ }
+ *len = eol_num;
+ buf[eol_num] = '\0'; /* lose the newline */
+
+ if (buf[0] && buf[0] != CREAD_HIST_CHAR)
+ cread_add_to_hist(buf);
+ hist_cur = hist_add_idx;
+
+ return (rc);
+}
+
+#endif /* CONFIG_CMDLINE_EDITING */
+
/****************************************************************************/
/*
@@ -528,6 +934,21 @@
*/
int readline (const char *const prompt)
{
+#ifdef CONFIG_CMDLINE_EDITING
+ char *p = console_buffer;
+ unsigned int len=MAX_CMDBUF_SIZE;
+ static int initted = 0;
+
+ if (!initted) {
+ hist_init();
+ initted = 1;
+ }
+
+ puts (prompt);
+
+ cread_line(p, &len);
+ return len;
+#else
char *p = console_buffer;
int n = 0; /* buffer index */
int plen = 0; /* prompt length */
@@ -623,10 +1044,12 @@
}
}
}
+#endif /* CONFIG_CMDLINE_EDITING */
}
/****************************************************************************/
+#ifndef CONFIG_CMDLINE_EDITING
static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen)
{
char *s;
@@ -656,6 +1079,7 @@
(*np)--;
return (p);
}
+#endif /* CONFIG_CMDLINE_EDITING */
/****************************************************************************/
diff --git a/common/usb.c b/common/usb.c
index d9515e6..0857494 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -72,6 +72,8 @@
static int asynch_allowed;
static struct devrequest setup_packet;
+char usb_started; /* flag for the started/stopped USB status */
+
/**********************************************************************
* some forward declerations...
*/
@@ -110,10 +112,12 @@
printf("scanning bus for devices... ");
running=1;
usb_scan_devices();
+ usb_started = 1;
return 0;
}
else {
printf("Error, couldn't init Lowlevel part\n");
+ usb_started = 0;
return -1;
}
}
@@ -124,6 +128,7 @@
int usb_stop(void)
{
asynch_allowed=1;
+ usb_started = 0;
usb_hub_reset();
return usb_lowlevel_stop();
}
@@ -280,56 +285,68 @@
int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno)
{
struct usb_descriptor_header *head;
- int index,ifno,epno;
- ifno=-1;
- epno=-1;
+ int index, ifno, epno, curr_if_num;
+ int i;
+ unsigned char *ch;
- dev->configno=cfgno;
- head =(struct usb_descriptor_header *)&buffer[0];
- if(head->bDescriptorType!=USB_DT_CONFIG) {
- printf(" ERROR: NOT USB_CONFIG_DESC %x\n",head->bDescriptorType);
+ ifno = -1;
+ epno = -1;
+ curr_if_num = -1;
+
+ dev->configno = cfgno;
+ head = (struct usb_descriptor_header *) &buffer[0];
+ if(head->bDescriptorType != USB_DT_CONFIG) {
+ printf(" ERROR: NOT USB_CONFIG_DESC %x\n", head->bDescriptorType);
return -1;
}
- memcpy(&dev->config,buffer,buffer[0]);
- dev->config.wTotalLength=swap_16(dev->config.wTotalLength);
- dev->config.no_of_if=0;
+ memcpy(&dev->config, buffer, buffer[0]);
+ dev->config.wTotalLength = swap_16(dev->config.wTotalLength);
+ dev->config.no_of_if = 0;
- index=dev->config.bLength;
+ index = dev->config.bLength;
/* Ok the first entry must be a configuration entry, now process the others */
- head=(struct usb_descriptor_header *)&buffer[index];
- while(index+1 < dev->config.wTotalLength) {
+ head = (struct usb_descriptor_header *) &buffer[index];
+ while(index + 1 < dev->config.wTotalLength) {
switch(head->bDescriptorType) {
case USB_DT_INTERFACE:
- ifno=dev->config.no_of_if;
- dev->config.no_of_if++; /* found an interface desc, increase numbers */
- memcpy(&dev->config.if_desc[ifno],&buffer[index],buffer[index]); /* copy new desc */
- dev->config.if_desc[ifno].no_of_ep=0;
-
+ if(((struct usb_interface_descriptor *) &buffer[index])->
+ bInterfaceNumber != curr_if_num) {
+ /* this is a new interface, copy new desc */
+ ifno = dev->config.no_of_if;
+ dev->config.no_of_if++;
+ memcpy(&dev->config.if_desc[ifno],
+ &buffer[index], buffer[index]);
+ dev->config.if_desc[ifno].no_of_ep = 0;
+ dev->config.if_desc[ifno].num_altsetting = 1;
+ curr_if_num = dev->config.if_desc[ifno].bInterfaceNumber;
+ } else {
+ /* found alternate setting for the interface */
+ dev->config.if_desc[ifno].num_altsetting++;
+ }
break;
case USB_DT_ENDPOINT:
- epno=dev->config.if_desc[ifno].no_of_ep;
+ epno = dev->config.if_desc[ifno].no_of_ep;
dev->config.if_desc[ifno].no_of_ep++; /* found an endpoint */
- memcpy(&dev->config.if_desc[ifno].ep_desc[epno],&buffer[index],buffer[index]);
- dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize
- =swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize);
- USB_PRINTF("if %d, ep %d\n",ifno,epno);
+ memcpy(&dev->config.if_desc[ifno].ep_desc[epno],
+ &buffer[index], buffer[index]);
+ dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize =
+ swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize);
+ USB_PRINTF("if %d, ep %d\n", ifno, epno);
break;
default:
- if(head->bLength==0)
+ if(head->bLength == 0)
return 1;
- USB_PRINTF("unknown Description Type : %x\n",head->bDescriptorType);
+ USB_PRINTF("unknown Description Type : %x\n", head->bDescriptorType);
{
- int i;
- unsigned char *ch;
- ch=(unsigned char *)head;
- for(i=0;i<head->bLength; i++)
- USB_PRINTF("%02X ",*ch++);
+ ch = (unsigned char *)head;
+ for(i = 0; i < head->bLength; i++)
+ USB_PRINTF("%02X ", *ch++);
USB_PRINTF("\n\n\n");
}
break;
}
- index+=head->bLength;
- head=(struct usb_descriptor_header *)&buffer[index];
+ index += head->bLength;
+ head = (struct usb_descriptor_header *)&buffer[index];
}
return 1;
}
@@ -443,6 +460,14 @@
printf("selecting invalid interface %d", interface);
return -1;
}
+ /*
+ * We should return now for devices with only one alternate setting.
+ * According to 9.4.10 of the Universal Serial Bus Specification Revision 2.0
+ * such devices can return with a STALL. This results in some USB sticks
+ * timeouting during initialization and then being unusable in U-Boot.
+ */
+ if (if_face->num_altsetting == 1)
+ return 0;
if ((ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE, alternate,
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 99e4ab0..e64470c 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -1139,6 +1139,10 @@
/* USB007 Mini-USB2 Flash Drive */
(dev->descriptor.idVendor == 0x066f &&
dev->descriptor.idProduct == 0x2010)
+ ||
+ /* SanDisk Corporation Cruzer Micro 20044318410546613953 */
+ (dev->descriptor.idVendor == 0x0781 &&
+ dev->descriptor.idProduct == 0x5151)
)
USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n");
else
diff --git a/common/xyzModem.c b/common/xyzModem.c
index 9b455a3..d1d66e8 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -261,8 +261,8 @@
static void
zm_flush(void)
{
- char *p = zm_out_start;
#ifdef REDBOOT
+ char *p = zm_out_start;
while (*p) mon_write_char(*p++);
#endif
zm_out = zm_out_start;
diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c
index 3ec9b54..1b36412 100644
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/interrupts.c
@@ -176,7 +176,9 @@
#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9)
+#elif defined(CONFIG_SBC2410X) || \
+ defined(CONFIG_SMDK2410) || \
+ defined(CONFIG_VCMA9)
tbclk = CFG_HZ;
#else
# error "tbclk not configured"
diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk
index c357615..b29986e 100644
--- a/cpu/mips/config.mk
+++ b/cpu/mips/config.mk
@@ -21,7 +21,7 @@
# MA 02111-1307 USA
#
v=$(shell \
-mips-linux-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
+$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
MIPSFLAGS=$(shell \
if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc"; \
diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index 1a7111f..c79e578 100644
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -161,6 +161,7 @@
defined(CONFIG_RMU) || \
defined(CONFIG_RPXCLASSIC) || \
defined(CONFIG_RPXLITE) || \
+ defined(CONFIG_SPC1920) || \
defined(CONFIG_SPD823TS)
memctl->memc_br0 = CFG_BR0_PRELIM;
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index 6006478..6d2755e 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -396,8 +396,10 @@
* * to 2.5 MHz.
* * This MDC frequency is equal to system clock / (2 * MII_SPEED).
* * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
+ *
+ * All MII configuration is done via FEC1 registers:
*/
- fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
+ immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
/* our PHYs are the limit at 2.5 MHz */
@@ -508,8 +510,6 @@
#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII)
-
-#warning this configuration is not tested; please report if it works
immr->im_cpm.cp_pepar |= 0x0003fffc;
immr->im_cpm.cp_pedir |= 0x0003fffc;
immr->im_cpm.cp_peso &= ~0x000087fc;
@@ -822,6 +822,7 @@
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
+#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
/* send command to phy using mii, wait for result */
static uint
@@ -907,6 +908,9 @@
case PHY_ID_DM9161:
printf("Davicom DM9161\n");
break;
+ case PHY_ID_KSM8995M:
+ printf("MICREL KS8995M\n");
+ break;
default:
printf("0x%08x\n", phytype);
break;
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index 26a82cc..8ae584f 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -227,9 +227,12 @@
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
- /* Set up the baud rate generator.
- */
+#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
+ *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
+#else
+ /* Set up the baud rate generator */
smc_setbrg ();
+#endif
/* Make the first buffer the only buffer.
*/
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 57f91c0..101d5f9 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -259,7 +259,11 @@
*/
sccr_reg = immr->im_clkrst.car_sccr;
sccr_reg &= ~SCCR_EBDF11;
+#if defined(CONFIG_TQM885D)
+ if (gd->cpu_clk <= 80000000) {
+#else
if (gd->cpu_clk <= 66000000) {
+#endif
sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
gd->bus_clk = gd->cpu_clk;
} else {
@@ -360,7 +364,8 @@
#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+ && !defined(CONFIG_TQM885D)
/*
* Adjust sdram refresh rate to actual CPU clock
* and set timebase source according to actual CPU clock
@@ -384,6 +389,6 @@
return (0);
}
-#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
/* ------------------------------------------------------------------------- */
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index e31d59d..faeea5c 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -379,7 +379,7 @@
/*
* Enable the controller, then wait for DCEN to complete
*/
- mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index 3749811..ad3ca6e 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -635,7 +635,7 @@
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
-#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
+#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
#if defined(CONFIG_SERIAL_MULTI)
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index c0a6933..c24456b 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -1007,9 +1007,9 @@
}
/*
- * program Page Management Unit
+ * program Page Management Unit (0 == enabled)
*/
- cfg0 |= SDRAM_CFG0_PMUD;
+ cfg0 &= ~SDRAM_CFG0_PMUD;
/*
* program Memory Controller Options 0
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 6d6d75f..60ed2d5 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -159,7 +159,7 @@
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
li r0,0
- mtspr esr,r0
+ mtspr esr,r0
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
/*----------------------------------------------------------------*/
diff --git a/doc/README.440-DDR-performance b/doc/README.440-DDR-performance
new file mode 100644
index 0000000..17bc747
--- /dev/null
+++ b/doc/README.440-DDR-performance
@@ -0,0 +1,90 @@
+AMCC suggested to set the PMU bit to 0 for best performace on the
+PPC440 DDR controller. The 440er common DDR setup files (sdram.c &
+spd_sdram.c) are changed accordingly. So all 440er boards using
+these setup routines will automatically receive this performance
+increase.
+
+Please see below some benchmarks done by AMCC to demonstrate this
+performance changes:
+
+
+----------------------------------------
+SDRAM0_CFG0[PMU] = 1 (U-boot default for Bamboo, Yosemite and Yellowstone)
+----------------------------------------
+Stream benchmark results
+-------------------------------------------------------------
+This system uses 8 bytes per DOUBLE PRECISION word.
+-------------------------------------------------------------
+Array size = 2000000, Offset = 0
+Total memory required = 45.8 MB.
+Each test is run 10 times, but only
+the *best* time for each is used.
+-------------------------------------------------------------
+Your clock granularity/precision appears to be 1 microseconds.
+Each test below will take on the order of 112345 microseconds.
+ (= 112345 clock ticks)
+Increase the size of the arrays if this shows that you are not getting
+at least 20 clock ticks per test.
+-------------------------------------------------------------
+WARNING -- The above is only a rough guideline.
+For best results, please be sure you know the precision of your system
+timer.
+-------------------------------------------------------------
+Function Rate (MB/s) RMS time Min time Max time
+Copy: 256.7683 0.1248 0.1246 0.1250
+Scale: 246.0157 0.1302 0.1301 0.1302
+Add: 255.0316 0.1883 0.1882 0.1885
+Triad: 253.1245 0.1897 0.1896 0.1899
+
+
+TTCP Benchmark Results
+ttcp-t: socket
+ttcp-t: connect
+ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp ->
+localhost
+ttcp-t: 16777216 bytes in 0.28 real seconds = 454.29 Mbit/sec +++
+ttcp-t: 2048 I/O calls, msec/call = 0.14, calls/sec = 7268.57
+ttcp-t: 0.0user 0.1sys 0:00real 60% 0i+0d 0maxrss 0+2pf 3+1506csw
+
+----------------------------------------
+SDRAM0_CFG0[PMU] = 0 (Suggested modification)
+Setting PMU = 0 provides a noticeable performance improvement *2% to
+5% improvement in memory performance.
+*Improves the Mbit/sec for TTCP benchmark by almost 76%.
+----------------------------------------
+Stream benchmark results
+-------------------------------------------------------------
+This system uses 8 bytes per DOUBLE PRECISION word.
+-------------------------------------------------------------
+Array size = 2000000, Offset = 0
+Total memory required = 45.8 MB.
+Each test is run 10 times, but only
+the *best* time for each is used.
+-------------------------------------------------------------
+Your clock granularity/precision appears to be 1 microseconds.
+Each test below will take on the order of 120066 microseconds.
+ (= 120066 clock ticks)
+Increase the size of the arrays if this shows that you are not getting
+at least 20 clock ticks per test.
+-------------------------------------------------------------
+WARNING -- The above is only a rough guideline.
+For best results, please be sure you know the precision of your system
+timer.
+-------------------------------------------------------------
+Function Rate (MB/s) RMS time Min time Max time
+Copy: 262.5167 0.1221 0.1219 0.1223
+Scale: 258.4856 0.1238 0.1238 0.1240
+Add: 262.5404 0.1829 0.1828 0.1831
+Triad: 266.8594 0.1800 0.1799 0.1802
+
+TTCP Benchmark Results
+ttcp-t: socket
+ttcp-t: connect
+ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp ->
+localhost
+ttcp-t: 16777216 bytes in 0.16 real seconds = 804.06 Mbit/sec +++
+ttcp-t: 2048 I/O calls, msec/call = 0.08, calls/sec = 12864.89
+ttcp-t: 0.0user 0.0sys 0:00real 46% 0i+0d 0maxrss 0+2pf 120+1csw
+
+
+2006-07-28, Stefan Roese <sr@denx.de>
diff --git a/doc/README.bamboo b/doc/README.bamboo
new file mode 100644
index 0000000..b50be01
--- /dev/null
+++ b/doc/README.bamboo
@@ -0,0 +1,15 @@
+The configuration for the AMCC 440EP eval board "Bamboo" was changed
+to only use 384 kbytes of FLASH for the U-Boot image. This way the
+redundant environment can be saved in the remaining 2 sectors of the
+same flash chip.
+
+Caution: With an upgrade from an earlier U-Boot version the current
+environment will be erased since the environment is now saved in
+different sectors. By using the following command the environment can
+be saved after upgrading the U-Boot image and *before* resetting the
+board:
+
+setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \
+ 'cp.b FFF60000 FFF80000 20000'
+
+2006-07-27, Stefan Roese <sr@denx.de>
diff --git a/drivers/Makefile b/drivers/Makefile
index e6176ed..9be95c7 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -31,7 +31,7 @@
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o \
- i8042.o i82365.o inca-ip_sw.o keyboard.o \
+ i8042.o inca-ip_sw.o keyboard.o \
lan91c96.o \
natsemi.o ne2000.o netarm_eth.o netconsole.o \
ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \
@@ -48,7 +48,9 @@
ti_pci1410a.o tigon3.o tsec.o \
usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
videomodes.o w83c553f.o \
- ks8695eth.o
+ ks8695eth.o \
+ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
+ rpx_pcmcia.o
all: $(LIB)
diff --git a/drivers/keyboard.c b/drivers/keyboard.c
index 41eccf2..9975202 100644
--- a/drivers/keyboard.c
+++ b/drivers/keyboard.c
@@ -33,7 +33,7 @@
#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
int ps2ser_check(void);
#endif
@@ -75,7 +75,7 @@
/* test if a character is in the queue */
static int kbd_testc(void)
{
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif
@@ -90,7 +90,7 @@
{
char c;
while(in_pointer==out_pointer) {
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif
diff --git a/drivers/mpc8xx_pcmcia.c b/drivers/mpc8xx_pcmcia.c
new file mode 100644
index 0000000..399a719
--- /dev/null
+++ b/drivers/mpc8xx_pcmcia.c
@@ -0,0 +1,304 @@
+#include <common.h>
+#if defined(CONFIG_8xx)
+#include <mpc8xx.h>
+#endif
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_8xx) && defined(CONFIG_PCMCIA)
+
+#if defined(CONFIG_IDE_8xx_PCCARD)
+extern int check_ide_device (int slot);
+#endif
+
+extern int pcmcia_hardware_enable (int slot);
+extern int pcmcia_voltage_set(int slot, int vcc, int vpp);
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+extern int pcmcia_hardware_disable(int slot);
+#endif
+
+static u_int m8xx_get_graycode(u_int size);
+#if 0 /* Disabled */
+static u_int m8xx_get_speed(u_int ns, u_int is_io);
+#endif
+
+/* look up table for pgcrx registers */
+u_int *pcmcia_pgcrx[2] = {
+ &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra,
+ &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb,
+};
+
+/*
+ * Search this table to see if the windowsize is
+ * supported...
+ */
+
+#define M8XX_SIZES_NO 32
+
+static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
+{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
+ 0x00000080, 0x00000040, 0x00000010, 0x00000020,
+ 0x00008000, 0x00004000, 0x00001000, 0x00002000,
+ 0x00000100, 0x00000200, 0x00000800, 0x00000400,
+
+ 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
+ 0x00010000, 0x00020000, 0x00080000, 0x00040000,
+ 0x00800000, 0x00400000, 0x00100000, 0x00200000 };
+
+
+/* -------------------------------------------------------------------- */
+
+#ifdef CONFIG_HMI10
+#define HMI10_FRAM_TIMING ( PCMCIA_SHT(2) \
+ | PCMCIA_SST(2) \
+ | PCMCIA_SL(4))
+#endif
+
+#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
+#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(9) \
+ | PCMCIA_SST(3) \
+ | PCMCIA_SL(12))
+#else
+#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(2) \
+ | PCMCIA_SST(4) \
+ | PCMCIA_SL(9))
+#endif
+
+/* -------------------------------------------------------------------- */
+
+int pcmcia_on (void)
+{
+ u_long reg, base;
+ pcmcia_win_t *win;
+ u_int slotbit;
+ u_int rc, slot;
+ int i;
+
+ debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ /* intialize the fixed memory windows */
+ win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0);
+ base = CFG_PCMCIA_MEM_ADDR;
+
+ if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) {
+ printf ("Cannot set window size to 0x%08x\n",
+ CFG_PCMCIA_MEM_SIZE);
+ return (1);
+ }
+
+ slotbit = PCMCIA_SLOT_x;
+ for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
+ win->br = base;
+
+#if (PCMCIA_SOCKETS_NO == 2)
+ if (i == 4) /* Another slot starting from win 4 */
+ slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
+#endif
+ switch (i) {
+#ifdef CONFIG_IDE_8xx_PCCARD
+ case 4:
+#ifdef CONFIG_HMI10
+ { /* map FRAM area */
+ win->or = ( PCMCIA_BSIZE_256K
+ | PCMCIA_PPS_8
+ | PCMCIA_PRS_ATTR
+ | slotbit
+ | PCMCIA_PV
+ | HMI10_FRAM_TIMING );
+ break;
+ }
+#endif
+ case 0: { /* map attribute memory */
+ win->or = ( PCMCIA_BSIZE_64M
+ | PCMCIA_PPS_8
+ | PCMCIA_PRS_ATTR
+ | slotbit
+ | PCMCIA_PV
+ | CFG_PCMCIA_TIMING );
+ break;
+ }
+ case 5:
+ case 1: { /* map I/O window for data reg */
+ win->or = ( PCMCIA_BSIZE_1K
+ | PCMCIA_PPS_16
+ | PCMCIA_PRS_IO
+ | slotbit
+ | PCMCIA_PV
+ | CFG_PCMCIA_TIMING );
+ break;
+ }
+ case 6:
+ case 2: { /* map I/O window for cmd/ctrl reg block */
+ win->or = ( PCMCIA_BSIZE_1K
+ | PCMCIA_PPS_8
+ | PCMCIA_PRS_IO
+ | slotbit
+ | PCMCIA_PV
+ | CFG_PCMCIA_TIMING );
+ break;
+ }
+#endif /* CONFIG_IDE_8xx_PCCARD */
+#ifdef CONFIG_HMI10
+ case 3: { /* map I/O window for 4xUART data/ctrl */
+ win->br += 0x40000;
+ win->or = ( PCMCIA_BSIZE_256K
+ | PCMCIA_PPS_8
+ | PCMCIA_PRS_IO
+ | slotbit
+ | PCMCIA_PV
+ | CFG_PCMCIA_TIMING );
+ break;
+ }
+#endif /* CONFIG_HMI10 */
+ default: /* set to not valid */
+ win->or = 0;
+ break;
+ }
+
+ debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",
+ i, win->br, win->or);
+ base += CFG_PCMCIA_MEM_SIZE;
+ ++win;
+ }
+
+ for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
+ /* turn off voltage */
+ if ((rc = pcmcia_voltage_set(slot, 0, 0)))
+ continue;
+
+ /* Enable external hardware */
+ if ((rc = pcmcia_hardware_enable(slot)))
+ continue;
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+ if ((rc = check_ide_device(i)))
+ continue;
+#endif
+ }
+ return rc;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+ int i;
+ pcmcia_win_t *win;
+
+ printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ /* clear interrupt state, and disable interrupts */
+ ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);
+ ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /* turn off interrupt and disable CxOE */
+ PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
+
+ /* turn off memory windows */
+ win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0);
+
+ for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
+ /* disable memory window */
+ win->or = 0;
+ ++win;
+ }
+
+ /* turn off voltage */
+ pcmcia_voltage_set(_slot_, 0, 0);
+
+ /* disable external hardware */
+ printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
+ pcmcia_hardware_disable(_slot_);
+ return 0;
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+static u_int m8xx_get_graycode(u_int size)
+{
+ u_int k;
+
+ for (k = 0; k < M8XX_SIZES_NO; k++) {
+ if(m8xx_size_to_gray[k] == size)
+ break;
+ }
+
+ if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
+ k = -1;
+
+ return k;
+}
+
+#if 0
+
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+
+/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
+ * SYPCR is write once only, therefore must the slowest memory be faster
+ * than the bus monitor or we will get a machine check due to the bus timeout.
+ */
+#undef PCMCIA_BMT_LIMIT
+#define PCMCIA_BMT_LIMIT (6*8)
+#endif
+
+static u_int m8xx_get_speed(u_int ns, u_int is_io)
+{
+ u_int reg, clocks, psst, psl, psht;
+
+ if(!ns) {
+
+ /*
+ * We get called with IO maps setup to 0ns
+ * if not specified by the user.
+ * They should be 255ns.
+ */
+
+ if(is_io)
+ ns = 255;
+ else
+ ns = 100; /* fast memory if 0 */
+ }
+
+ /*
+ * In PSST, PSL, PSHT fields we tell the controller
+ * timing parameters in CLKOUT clock cycles.
+ * CLKOUT is the same as GCLK2_50.
+ */
+
+ /* how we want to adjust the timing - in percent */
+
+#define ADJ 180 /* 80 % longer accesstime - to be sure */
+
+ clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
+ clocks = (clocks * ADJ) / (100*1000);
+
+ if(clocks >= PCMCIA_BMT_LIMIT) {
+ DEBUG(0, "Max access time limit reached\n");
+ clocks = PCMCIA_BMT_LIMIT-1;
+ }
+
+ psst = clocks / 7; /* setup time */
+ psht = clocks / 7; /* hold time */
+ psl = (clocks * 5) / 7; /* strobe length */
+
+ psst += clocks - (psst + psht + psl);
+
+ reg = psst << 12;
+ reg |= psl << 7;
+ reg |= psht << 16;
+
+ return reg;
+}
+#endif /* 0 */
+
+#endif /* CONFIG_8xx && CONFIG_PCMCIA */
diff --git a/drivers/ps2ser.c b/drivers/ps2ser.c
index 8aea8fd..4e304f7 100644
--- a/drivers/ps2ser.c
+++ b/drivers/ps2ser.c
@@ -20,7 +20,7 @@
#include <asm/io.h>
#include <asm/atomic.h>
#include <ps2mult.h>
-#ifdef CFG_NS16550
+#if defined(CFG_NS16550) || defined(CONFIG_MPC85xx)
#include <ns16550.h>
#endif
@@ -49,7 +49,7 @@
#error CONFIG_PS2SERIAL must be in 1 ... 6
#endif
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#if CONFIG_PS2SERIAL == 1
#define COM_BASE (CFG_CCSRBAR+0x4500)
@@ -59,13 +59,13 @@
#error CONFIG_PS2SERIAL must be in 1 ... 2
#endif
-#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx */
+#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
static int ps2ser_getc_hw(void);
static void ps2ser_interrupt(void *dev_id);
extern struct serial_state rs_table[]; /* in serial.c */
-#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC85xx)
+#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555)
static struct serial_state *state;
#endif
@@ -120,7 +120,7 @@
return (0);
}
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
int ps2ser_init(void)
{
NS16550_t com_port = (NS16550_t)COM_BASE;
@@ -136,7 +136,7 @@
return (0);
}
-#else /* !CONFIG_MPC5xxx && !CONFIG_MPC85xx */
+#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */
static inline unsigned int ps2ser_in(int offset)
{
@@ -180,13 +180,13 @@
return 0;
}
-#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx / other */
+#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
void ps2ser_putc(int chr)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
#ifdef DEBUG
@@ -197,7 +197,7 @@
while (!(psc->psc_status & PSC_SR_TXRDY));
psc->psc_buffer_8 = chr;
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
while ((com_port->lsr & LSR_THRE) == 0);
com_port->thr = chr;
#else
@@ -211,7 +211,7 @@
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int res = -1;
@@ -220,7 +220,7 @@
if (psc->psc_status & PSC_SR_RXRDY) {
res = (psc->psc_buffer_8);
}
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
if (com_port->lsr & LSR_DR) {
res = com_port->rbr;
}
@@ -279,7 +279,7 @@
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int chr;
@@ -289,7 +289,7 @@
chr = ps2ser_getc_hw();
#ifdef CONFIG_MPC5xxx
status = psc->psc_status;
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
status = com_port->lsr;
#else
status = ps2ser_in(UART_IIR);
@@ -305,7 +305,7 @@
}
#ifdef CONFIG_MPC5xxx
} while (status & PSC_SR_RXRDY);
-#elif defined(CONFIG_MPC85xx)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
} while (status & LSR_DR);
#else
} while (status & UART_IIR_RDI);
diff --git a/drivers/pxa_pcmcia.c b/drivers/pxa_pcmcia.c
new file mode 100644
index 0000000..d9d38bb
--- /dev/null
+++ b/drivers/pxa_pcmcia.c
@@ -0,0 +1,95 @@
+#include <common.h>
+#include <config.h>
+
+#ifdef CONFIG_PXA_PCMCIA
+
+#include <pcmcia.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+static inline void msWait(unsigned msVal)
+{
+ udelay(msVal*1000);
+}
+
+int pcmcia_on (void)
+{
+ unsigned int reg_arr[] = {
+ 0x48000028, CFG_MCMEM0_VAL,
+ 0x4800002c, CFG_MCMEM1_VAL,
+ 0x48000030, CFG_MCATT0_VAL,
+ 0x48000034, CFG_MCATT1_VAL,
+ 0x48000038, CFG_MCIO0_VAL,
+ 0x4800003c, CFG_MCIO1_VAL,
+
+ 0, 0
+ };
+ int i, rc;
+
+#ifdef CONFIG_EXADRON1
+ int cardDetect;
+ volatile unsigned int *v_pBCRReg =
+ (volatile unsigned int *) 0x08000000;
+#endif
+
+ debug ("%s\n", __FUNCTION__);
+
+ i = 0;
+ while (reg_arr[i])
+ *((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++];
+ udelay (1000);
+
+ debug ("%s: programmed mem controller \n", __FUNCTION__);
+
+#ifdef CONFIG_EXADRON1
+
+/*define useful BCR masks */
+#define BCR_CF_INIT_VAL 0x00007230
+#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231
+#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233
+#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213
+#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211
+
+ /* we see from the GPIO bit if the card is present */
+ cardDetect = !(GPLR0 & GPIO_bit (14));
+
+ if (cardDetect) {
+ printf ("No PCMCIA card found!\n");
+ }
+
+ /* reset the card via the BCR line */
+ *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL;
+ msWait (500);
+
+ *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL;
+ msWait (500);
+
+ *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL;
+ msWait (500);
+
+ *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL;
+ msWait (500);
+
+ *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL;
+ msWait (1500);
+
+ /* enable address bus */
+ GPCR1 = 0x01;
+ /* and the first CF slot */
+ MECR = 0x00000002;
+
+#endif /* EXADRON 1 */
+
+ rc = check_ide_device (0); /* use just slot 0 */
+
+ return rc;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+ return 0;
+}
+#endif
+
+#endif /* CONFIG_PXA_PCMCIA */
diff --git a/drivers/rpx_pcmcia.c b/drivers/rpx_pcmcia.c
new file mode 100644
index 0000000..2a0a9e0
--- /dev/null
+++ b/drivers/rpx_pcmcia.c
@@ -0,0 +1,73 @@
+/* -------------------------------------------------------------------- */
+/* RPX Boards from Embedded Planet */
+/* -------------------------------------------------------------------- */
+#include <common.h>
+#ifdef CONFIG_8xx
+#include <mpc8xx.h>
+#endif
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if CONFIG_COMMANDS & CFG_CMD_PCMCIA
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_PCMCIA) \
+ && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE))
+
+#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ u_long reg = 0;
+
+ switch(vcc) {
+ case 0: break;
+ case 33: reg |= BCSR1_PCVCTL4; break;
+ case 50: reg |= BCSR1_PCVCTL5; break;
+ default: return 1;
+ }
+
+ switch(vpp) {
+ case 0: break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= BCSR1_PCVCTL6;
+ else
+ return 1;
+ break;
+ case 120:
+ reg |= BCSR1_PCVCTL7;
+ default: return 1;
+ }
+
+ /* first, turn off all power */
+ *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5
+ | BCSR1_PCVCTL6 | BCSR1_PCVCTL7);
+
+ /* enable new powersettings */
+ *((uint *)RPX_CSR_ADDR) |= reg;
+
+ return 0;
+}
+
+int pcmcia_hardware_enable (int slot)
+{
+ return 0; /* No hardware to enable */
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+static int pcmcia_hardware_disable(int slot)
+{
+ return 0; /* No hardware to disable */
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_PCMCIA */
+
+
+#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */
diff --git a/drivers/s3c4510b_eth.c b/drivers/s3c4510b_eth.c
index 0274dd2..48901aa 100644
--- a/drivers/s3c4510b_eth.c
+++ b/drivers/s3c4510b_eth.c
@@ -175,7 +175,7 @@
}
/* copy user data into frame data pointer */
- memcpy((void *)eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr,
+ memcpy((void *)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr),
(void *)packet,
length);
diff --git a/drivers/tqm8xx_pcmcia.c b/drivers/tqm8xx_pcmcia.c
new file mode 100644
index 0000000..a0f53cd
--- /dev/null
+++ b/drivers/tqm8xx_pcmcia.c
@@ -0,0 +1,330 @@
+/* -------------------------------------------------------------------- */
+/* TQM8xxL Boards by TQ Components */
+/* SC8xx Boards by SinoVee Microsystems */
+/* -------------------------------------------------------------------- */
+#include <common.h>
+#ifdef CONFIG_8xx
+#include <mpc8xx.h>
+#endif
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_PCMCIA) \
+ && (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx))
+
+#if defined(CONFIG_VIRTLAB2)
+#define PCMCIA_BOARD_MSG "Virtlab2"
+#elif defined(CONFIG_TQM8xxL)
+#define PCMCIA_BOARD_MSG "TQM8xxL"
+#elif defined(CONFIG_SVM_SC8xx)
+#define PCMCIA_BOARD_MSG "SC8xx"
+#endif
+
+#if defined(CONFIG_NSCU)
+
+#define power_config(slot) do {} while (0)
+#define power_off(slot) do {} while (0)
+#define power_on_5_0(slot) do {} while (0)
+#define power_on_3_3(slot) do {} while (0)
+
+#elif defined(CONFIG_HMI10)
+
+static inline void power_config(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ /*
+ * Configure Port B pins for
+ * 5 Volts Enable and 3 Volts enable
+ */
+ immap->im_cpm.cp_pbpar &= ~(0x00000300);
+}
+
+static inline void power_off(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ /* remove all power */
+ immap->im_cpm.cp_pbdat |= 0x00000300;
+}
+
+static inline void power_on_5_0(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_cpm.cp_pbdat &= ~(0x0000100);
+ immap->im_cpm.cp_pbdir |= 0x00000300;
+}
+
+static inline void power_on_3_3(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_cpm.cp_pbdat &= ~(0x0000200);
+ immap->im_cpm.cp_pbdir |= 0x00000300;
+}
+
+#elif defined(CONFIG_VIRTLAB2)
+
+#define power_config(slot) do {} while (0)
+static inline void power_off(int slot)
+{
+ volatile unsigned char *powerctl =
+ (volatile unsigned char *)PCMCIA_CTRL;
+ *powerctl = 0;
+}
+
+static inline void power_on_5_0(int slot)
+{
+ volatile unsigned char *powerctl =
+ (volatile unsigned char *)PCMCIA_CTRL;
+ *powerctl = 2; /* Enable 5V Vccout */
+}
+
+static inline void power_on_3_3(int slot)
+{
+ volatile unsigned char *powerctl =
+ (volatile unsigned char *)PCMCIA_CTRL;
+ *powerctl = 1; /* Enable 3.3V Vccout */
+}
+
+#else
+
+static inline void power_config(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ /*
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable
+ */
+ immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004);
+ immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004);
+}
+
+static inline void power_off(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
+}
+
+static inline void power_on_5_0(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_ioport.iop_pcdat |= 0x0004;
+ immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
+}
+
+static inline void power_on_3_3(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_ioport.iop_pcdat |= 0x0002;
+ immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
+}
+
+#endif
+
+#ifdef CONFIG_HMI10
+static inline int check_card_is_absent(int slot)
+{
+ volatile pcmconf8xx_t *pcmp =
+ (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ return pcmp->pcmc_pipr & (0x10000000 >> (slot << 4));
+}
+#else
+static inline int check_card_is_absent(int slot)
+{
+ volatile pcmconf8xx_t *pcmp =
+ (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ return pcmp->pcmc_pipr & (0x18000000 >> (slot << 4));
+}
+#endif
+
+#ifdef NSCU_OE_INV
+#define NSCU_GCRX_CXOE 0
+#else
+#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE
+#endif
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile pcmconf8xx_t *pcmp =
+ (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ volatile sysconf8xx_t *sysp =
+ (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ uint reg, mask;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(slot);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= NSCU_GCRX_CXOE;
+
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(500);
+
+ power_config(slot);
+ power_off(slot);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+
+ if (check_card_is_absent(slot)) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+ if ((reg & mask) == mask) {
+ power_on_5_0(slot);
+ puts (" 5.0V card found: ");
+ } else {
+ power_on_3_3(slot);
+ puts (" 3.3V card found: ");
+ }
+
+#if 0
+ /* VCC switch error flag, PCMCIA slot INPACK_ pin */
+ cp->cp_pbdir &= ~(0x0020 | 0x0010);
+ cp->cp_pbpar &= ~(0x0020 | 0x0010);
+ udelay(500000);
+#endif
+
+ udelay(1000);
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ reg &= ~NSCU_GCRX_CXOE;
+
+ PCMCIA_PGCRX(slot) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+
+ /* remove all power */
+ power_off(slot);
+
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= NSCU_GCRX_CXOE; /* active low */
+
+ PCMCIA_PGCRX(slot) = reg;
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+#ifndef CONFIG_NSCU
+ u_long reg;
+# ifdef DEBUG
+ volatile pcmconf8xx_t *pcmp =
+ (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+# endif
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ reg |= NSCU_GCRX_CXOE; /* active low */
+
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(500);
+
+ debug ("PCMCIA power OFF\n");
+ power_config(slot);
+ power_off(slot);
+
+ switch(vcc) {
+ case 0: break;
+ case 33: power_on_3_3(slot); break;
+ case 50: power_on_5_0(slot); break;
+ default: goto done;
+ }
+
+ /* Checking supported voltages */
+
+ debug("PIPR: 0x%x --> %s\n", pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+ if (vcc)
+ debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3");
+ else
+ debug("PCMCIA powered down\n");
+
+done:
+ debug("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ reg &= ~NSCU_GCRX_CXOE; /* active low */
+
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(500);
+
+ debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
+#endif /* CONFIG_NSCU */
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */
diff --git a/include/common.h b/include/common.h
index 5f00f91..bd41ae1 100644
--- a/include/common.h
+++ b/include/common.h
@@ -116,12 +116,13 @@
/*
* enable common handling for all TQM8xxL/M boards:
- * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
+ * - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards
* - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
*/
#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
- defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
+ defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \
+ defined(CONFIG_TQM885D)
# ifndef CONFIG_TQM8xxM
# define CONFIG_TQM8xxM
# endif
diff --git a/include/commproc.h b/include/commproc.h
index 061468e..12400e3 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -1405,15 +1405,16 @@
#endif /* CONFIG_SXNI855T */
-/*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/
+/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
- defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \
- defined(CONFIG_VIRTLAB2)|| \
+ defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
+ defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
+
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
@@ -1438,6 +1439,11 @@
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
+
+# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
+#define FEC_ENET
+# endif /* CONFIG_FEC_ENET */
+
#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 9a98e5c..7a1dada 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -455,7 +455,7 @@
#define CFG_MIN_AM_MASK 0xC0000000
/*
- * we use the same values for 32 MB and 128 MB SDRAM
+ * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
* refresh rate = 7.68 uS (100 MHz Bus Clock)
*/
@@ -510,6 +510,24 @@
PSDMR_WRC_1C |\
PSDMR_CL_2)
+ /* SDRAM initialization values for 10-column chips
+ */
+#define CFG_OR2_10COL (CFG_MIN_AM_MASK |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI1_A4 |\
+ ORxS_NUMR_13)
+
+#define CFG_PSDMR_10COL (PSDMR_PBI |\
+ PSDMR_SDAM_A17_IS_A5 |\
+ PSDMR_BSMA_A13_A15 |\
+ PSDMR_SDA10_PBI1_A6 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_2W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+
/*
* Init Memory Controller:
*
@@ -588,9 +606,9 @@
BRx_MS_SDRAM_P |\
BRx_V)
-#define CFG_OR2_PRELIM CFG_OR2_9COL
+#define CFG_OR2_PRELIM CFG_OR2_8COL
-#define CFG_PSDMR CFG_PSDMR_9COL
+#define CFG_PSDMR CFG_PSDMR_8COL
#endif /* CFG_RAMBOOT */
/* Bank 3 - Dual Ported SRAM
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
new file mode 100644
index 0000000..8a6e5a6
--- /dev/null
+++ b/include/configs/TB5200.h
@@ -0,0 +1,507 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
+#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
+
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
+#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
+#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_VIDEO
+#define ADD_BMP_CMD CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD 0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/* IDE */
+#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ ADD_BMP_CMD | \
+ ADD_IDE_CMD | \
+ ADD_PCI_CMD | \
+ ADD_USB_CMD | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PING | \
+ CFG_CMD_POST_DIAG | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SNTP | \
+ CFG_CMD_BSP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_TIMESTAMP /* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000) /* Boot low */
+# define CFG_LOWBOOT 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#if defined(CONFIG_TQM5200_B)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "bootfile=/tftpboot/tqm5200/uImage\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
+ "update=protect off FC000000 FC07FFFF;" \
+ "erase FC000000 FC07FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC07FFFF\0" \
+ ""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "bootfile=/tftpboot/tqm5200/uImage\0" \
+ "load=tftp 200000 $(u-boot)\0" \
+ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
+ "update=protect off FC000000 FC05FFFF;" \
+ "erase FC000000 FC05FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC05FFFF\0" \
+ ""
+#endif /* CONFIG_TQM5200_B */
+
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #2 */
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/* List of I2C addresses to be verified by POST */
+#undef I2C_ADDR_LIST
+#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
+ CFG_I2C_RTC_ADDR, \
+ CFG_I2C_SLAVE }
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else /* CFG_LOWBOOT */
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
+#else
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
+#endif /* CONFIG_TQM5200_B */
+#endif /* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
+ (= chip selects) */
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM5200-0"
+#if defined(CONFIG_TQM5200_B)
+#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
+ "1280k(kernel)," \
+ "2m(initrd)," \
+ "4m(small-fs)," \
+ "16m(big-fs)," \
+ "8m(misc)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+ "1408k(kernel)," \
+ "2m(initrd)," \
+ "4m(small-fs)," \
+ "16m(big-fs)," \
+ "8m(misc)"
+#endif /* CONFIG_TQM5200_B */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_SECT_SIZE 0x40000
+#else
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CONFIG_TQM5200_B */
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#if defined(CONFIG_TQM5200_B)
+#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#endif /* CONFIG_TQM5200_B */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ * Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ * Use for REV200 STK52XX boards. Do not use with REV100 modules
+ * (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ * 000 -> All PSC2 pins are GIOPs
+ * 001 -> CAN1/2 on PSC2 pins
+ * Use for REV100 STK52xx boards
+ * use PSC3: Bits 20:23 (mask: 0x00000300):
+ * 0001 -> USB2
+ * 0000 -> GPIO
+ * use PSC6:
+ * on STK52xx:
+ * use as UART. Pins PSC6_0 to PSC6_3 are used.
+ * Bits 9:11 (mask: 0x00700000):
+ * 101 -> PSC6 : Extended POST test is not available
+ * on MINI-FAP and TQM5200_IB:
+ * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ * 000 -> PSC6 could not be used as UART, CODEC or IrDA
+ * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ * tests.
+ */
+#define CFG_GPS_PORT_CONFIG 0x81500114
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_M41T11 1
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
+ year */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#define CFG_CS2_START 0xE5000000
+#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
+#define CFG_CS2_CFG 0x0004D930
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#define SM501_FB_BASE 0xE0000000
+#define CFG_CS1_START (SM501_FB_BASE)
+#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
+#define CFG_CS1_CFG 0x8F48FF70
+#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 6b8759f..be83b67 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -2,7 +2,7 @@
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2004-2005
+ * (C) Copyright 2004-2006
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
@@ -32,27 +32,30 @@
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
-#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
-#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */
+#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_STK52XX
@@ -96,7 +99,7 @@
/*
* Video console
*/
-#if 1
+#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
@@ -129,10 +132,12 @@
#define ADD_USB_CMD 0
#endif
+#ifndef CONFIG_CAM5200
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_I2C)
+#endif
#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
@@ -176,8 +181,8 @@
#define CONFIG_TIMESTAMP /* display image timestamps */
-#if (TEXT_BASE == 0xFC000000) /* Boot low */
-# define CFG_LOWBOOT 1
+#if (TEXT_BASE != 0xFFF00000)
+# define CFG_LOWBOOT 1 /* Boot low */
#endif
/*
@@ -186,11 +191,43 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
+#ifdef CONFIG_STK52XX
+# if defined(CONFIG_TQM5200_B)
+# if defined(CFG_LOWBOOT)
+# define ENV_UPDT \
+ "update=protect off FC000000 FC07FFFF;" \
+ "erase FC000000 FC07FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC07FFFF\0"
+# else /* highboot */
+# define ENV_UPDT \
+ "update=protect off FFF00000 FFF7FFFF;" \
+ "erase FFF00000 FFF7FFFF;" \
+ "cp.b 200000 FFF00000 ${filesize};" \
+ "protect on FFF00000 FFF7FFFF\0"
+# endif /* CFG_LOWBOOT */
+# else /* !CONFIG_TQM5200_B */
+# define ENV_UPDT \
+ "update=protect off FC000000 FC05FFFF;" \
+ "erase FC000000 FC05FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC05FFFF\0"
+# endif /* CONFIG_TQM5200_B */
+#elif defined (CONFIG_CAM5200)
+# define ENV_UPDT \
+ "update=protect off FC000000 FC03FFFF;" \
+ "erase FC000000 FC03FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC03FFFF\0"
+#else
+# error "Unknown Carrier Board"
+#endif /* CONFIG_STK52XX */
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
@@ -200,18 +237,18 @@
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate}\0" \
+ "flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
+ "flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
+ "bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC05FFFF\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ ENV_UPDT \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
@@ -283,45 +320,80 @@
/*
* Flash configuration
*/
-#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+#define CFG_FLASH_BASE 0xFC000000
-/* use CFI flash driver if no module variant is spezified */
+/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
-#if !defined(CFG_LOWBOOT)
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CFG_LOWBOOT */
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
-#endif /* CFG_LOWBOOT */
+#if defined (CONFIG_CAM5200)
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
+#elif defined(CONFIG_TQM5200_B)
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
+#else
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
+#endif
+
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
-#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/* Dynamic MTD partition support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM5200-0"
-#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+
+#ifdef CONFIG_STK52XX
+# if defined(CONFIG_TQM5200_B)
+# if defined(CFG_LOWBOOT)
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \
+ "1536k(kernel)," \
+ "3584k(small-fs)," \
+ "2m(initrd)," \
+ "8m(misc)," \
+ "16m(big-fs)"
+# else /* highboot */
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \
+ "3584k(small-fs)," \
+ "2m(initrd)," \
+ "8m(misc)," \
+ "15m(big-fs)," \
+ "1m(firmware)"
+# endif /* CFG_LOWBOOT */
+# else /* !CONFIG_TQM5200_B */
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
- "16m(big-fs)," \
- "8m(misc)"
+ "8m(misc)," \
+ "16m(big-fs)"
+# endif /* CONFIG_TQM5200_B */
+#elif defined (CONFIG_CAM5200)
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
+ "1792k(kernel)," \
+ "3584k(small-fs)," \
+ "2m(initrd)," \
+ "8m(misc)," \
+ "16m(big-fs)"
+#else
+# error "Unknown Carrier Board"
+#endif /* CONFIG_STK52XX */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_SECT_SIZE 0x40000
+#else
#define CFG_ENV_SECT_SIZE 0x20000
+#endif /* CONFIG_TQM5200_B */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Memory map
@@ -349,8 +421,15 @@
# define CFG_RAMBOOT 1
#endif
-#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
+#if defined (CONFIG_CAM5200)
+# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#elif defined(CONFIG_TQM5200_B)
+# define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
+#else
+# define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#endif
+
+#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
@@ -411,6 +490,8 @@
#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
# define CONFIG_RTC_M41T11 1
# define CFG_I2C_RTC_ADDR 0x68
+# define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
+ year */
#else
# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
#endif
@@ -420,6 +501,10 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
@@ -466,32 +551,25 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
-#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
-#if defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#define CFG_CS2_CFG 0x0004D930
-#endif
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
-#if defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
-#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index da6946b..780f274 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -158,7 +158,7 @@
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#else
+#else /* ! TQM8560 */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
@@ -170,6 +170,15 @@
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+/* PS/2 Keyboard */
+#if !defined(CONFIG_TQM8560)
+#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
+#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
+#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
+#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
+#define CONFIG_BOARD_EARLY_INIT_R 1
+#endif /* !CONFIG_TQM8560 */
+
#endif /* CONFIG_TQM8560 */
#define CONFIG_BAUDRATE 115200
@@ -177,13 +186,6 @@
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-/* PS/2 Keyboard */
-#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
-#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
-#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
-#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
-#define CONFIG_BOARD_EARLY_INIT_R 1
-
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
new file mode 100644
index 0000000..ede4e3b
--- /dev/null
+++ b/include/configs/TQM885D.h
@@ -0,0 +1,492 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
+#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
+
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
+#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
+#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
+#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */
+ /* (it will be used if there is no */
+ /* 'cpuclk' variable with valid value) */
+
+#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */
+ /* (function measure_gclk() */
+ /* will be called) */
+#ifdef CFG_MEASURE_CPUCLK
+#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
+#endif
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/TQM866M/uImage\0" \
+ "kernel_addr=40080000\0" \
+ "ramdisk_addr=40180000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+
+#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
+#define CFG_I2C_SLAVE 0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+# define CONFIG_RTC_DS1337 1
+# define CFG_I2C_RTC_ADDR 0x68
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
+
+#define CONFIG_TIMESTAMP /* but print image timestmps */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PING )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if 0
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#endif
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
+#define CFG_ALT_MEMTEST /* alternate, more extensive
+ memory test.*/
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else /* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif /* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+ OR_SCY_6_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP CFG_OR0_REMAP
+#define CFG_OR1_PRELIM CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
+#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM 0x00000A00
+
+#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_OR3_PRELIM CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
+#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
+#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
+ BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif /* CONFIG_CAN_DRIVER */
+
+/*
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Memory Periodic Timer Prescaler
+ * Periodic timer for refresh, start with refresh rate for 40 MHz clock
+ * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
+ */
+#define CFG_MAMR_PTA 39
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Network configuration
+ */
+#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
+#define CONFIG_FEC_ENET /* enable ethernet on FEC */
+#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
+#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#define CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
+ switching to another netwok (if the
+ tried network is unreachable) */
+
+#define CONFIG_ETHPRIME "SCC ETHERNET"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/aev.h b/include/configs/aev.h
index aa6bc91..8d9f0a1 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2005
@@ -370,10 +370,7 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
-#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 6d32821..2c1c319 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -49,7 +49,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
@@ -257,8 +257,8 @@
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
- "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
- "cp.b 100000 fff80000 80000;" \
+ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
+ "cp.b 100000 fffa0000 60000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
@@ -358,6 +358,14 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#else
+#define CONFIG_AUTO_COMPLETE
+#endif
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index 77d2d56..a49ed3b 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -34,7 +34,7 @@
#define CONFIG_AU1000 1
-#define CONFIG_MISC_INIT_R 1
+#define CONFIG_MISC_INIT_R 1
#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */
@@ -59,21 +59,21 @@
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTARGS "panic=1"
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#define CONFIG_BOOTARGS "panic=1"
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
"addmisc=setenv bootargs $(bootargs) " \
- "ethaddr=$(ethaddr) \0" \
- "netboot=bootp;run addmisc;bootm\0" \
- ""
+ "ethaddr=$(ethaddr) \0" \
+ "netboot=bootp;run addmisc;bootm\0" \
+ ""
/* Boot from Compact flash partition 2 as default */
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
- CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \
+ CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \
CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
#include <cmd_confdefs.h>
@@ -81,11 +81,11 @@
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args*/
#define CFG_MALLOC_LEN 128*1024
@@ -93,16 +93,16 @@
#define CFG_MHZ 500
-#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
-#define CFG_LOAD_ADDR 0x81000000 /* default load address */
+#define CFG_LOAD_ADDR 0x81000000 /* default load address */
#define CFG_MEMTEST_START 0x80100000
#define CFG_MEMTEST_END 0x83000000
-#define CONFIG_HW_WATCHDOG 1
+#define CONFIG_HW_WATCHDOG 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
@@ -113,8 +113,8 @@
#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (192 << 10)
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (192 << 10)
#define CFG_INIT_SP_OFFSET 0x400000
@@ -125,7 +125,7 @@
#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
-#define CFG_ENV_IS_NOWHERE 1
+#define CFG_ENV_IS_NOWHERE 1
/* Address and size of Primary Environment Sector */
#define CFG_ENV_ADDR 0xB0030000
@@ -158,21 +158,21 @@
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_ATA_IDE0_OFFSET 0
-#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE
/* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET 0
+#define CFG_ATA_DATA_OFFSET 0
-/* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET 0
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET 0
-/* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET 0x0200
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0200
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
new file mode 100644
index 0000000..61cf705
--- /dev/null
+++ b/include/configs/kvme080.h
@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC824X 1
+#define CONFIG_MPC8245 1
+#define CONFIG_KVME080 1
+
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_IPADDR 192.168.0.2
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_SERVERIP 192.168.0.1
+
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 " \
+ "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
+ "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
+ "kvme080:eth0:none " \
+ "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
+
+#define CONFIG_BOOTCOMMAND \
+ "tftp 800000 kvme080/uImage; " \
+ "bootm 800000"
+
+#define CONFIG_LOADADDR 800000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_LOADS_ECHO 1
+#undef CFG_LOADS_BAUD_CHANGE
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_DS164x
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP)
+
+#define CONFIG_NETCONSOLE
+
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE CFG_CBSIZE
+
+#define CFG_MEMTEST_START 0x00400000
+#define CFG_MEMTEST_END 0x07C00000
+
+#define CFG_LOAD_ADDR 0x00100000
+#define CFG_HZ 1000
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_SIZE 128
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x7C000000
+#define CFG_EUMB_ADDR 0xFC000000
+#define CFG_NVRAM_BASE_ADDR 0xFF000000
+#define CFG_NS16550_COM1 0xFF080000
+#define CFG_NS16550_COM2 0xFF080010
+#define CFG_NS16550_COM3 0xFF080020
+#define CFG_NS16550_COM4 0xFF080030
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#define CFG_MAX_RAM_SIZE 0x20000000
+#define CFG_FLASH_SIZE (16 * 1024 * 1024)
+#define CFG_NVRAM_SIZE 0x7FFF8
+
+#define CONFIG_VERY_BIG_RAM
+
+#define CFG_MONITOR_LEN 0x00040000
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MALLOC_LEN (512 << 10)
+
+#define CFG_BOOTMAPSZ (8 << 20)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_USE_BUFFER_WRITE
+#define CFG_FLASH_PROTECTION
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_PROTECT_CLEAR
+
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 256
+
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+
+#define CFG_ENV_IS_IN_NVRAM 1
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_NVRAM_ACCESS_ROUTINE
+#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
+#define CFG_ENV_SIZE 0x400
+#define CFG_ENV_OFFSET 0
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK 14745600
+
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define CFG_RX_ETH_BUFFER 8
+
+#define CONFIG_HARD_I2C 1
+#define CFG_I2C_SPEED 400000
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_SYS_CLK_FREQ 33333333
+
+#define CFG_CACHELINE_SIZE 32
+#if CONFIG_COMMANDS & CFG_CMD_KGDB
+# define CFG_CACHELINE_SHIFT 5
+#endif
+
+#define CFG_DLL_EXTEND 0x00
+#define CFG_PCI_HOLD_DEL 0x20
+
+#define CFG_ROMNAL 15
+#define CFG_ROMFAL 31
+
+#define CFG_REFINT 430
+
+#define CFG_DBUS_SIZE2 1
+
+#define CFG_BSTOPRE 121
+#define CFG_REFREC 8
+#define CFG_RDLAT 4
+#define CFG_PRETOACT 3
+#define CFG_ACTTOPRE 5
+#define CFG_ACTORW 3
+#define CFG_SDMODE_CAS_LAT 3
+#define CFG_SDMODE_WRAP 0
+
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM 1
+#define CFG_REGDIMM 0
+
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (0x4000000 - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x04000000
+#define CFG_BANK1_END (0x8000000 - 1)
+#define CFG_BANK1_ENABLE 1
+#define CFG_BANK2_START 0x3ff00000
+#define CFG_BANK2_END 0x3fffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x3ff00000
+#define CFG_BANK3_END 0x3fffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x00000000
+#define CFG_BANK4_END 0x00000000
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x00000000
+#define CFG_BANK5_END 0x00000000
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x00000000
+#define CFG_BANK6_END 0x00000000
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x00000000
+#define CFG_BANK7_END 0x00000000
+#define CFG_BANK7_ENABLE 0
+
+#define CFG_BANK_ENABLE 0x03
+
+#define CFG_ODCR 0x75
+#define CFG_PGMAX 0x32
+
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+#define BOOTFLAG_COLD 0x01
+#define BOOTFLAG_WARM 0x02
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index d8d63a1..ce33b85 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -47,8 +47,22 @@
/*
* Serial console configuration
+ *
+ * To select console on the one of 8 external UARTs,
+ * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
+ * or as 5, 6, 7, or 8 for the second Quad UART.
+ *
+ * CONFIG_PSC_CONSOLE must be undefined in this case.
+ */
+/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */
+/*
+ * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
+ * and undefine CONFIG_QUART_CONSOLE.
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
+#error "Select only one console device!"
+#endif
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
@@ -256,11 +270,59 @@
#define CFG_CS2_SIZE 0x00001000
#define CFG_CS2_CFG 0x1d300
+/* Second Quad UART @0x80010000 */
+#define CFG_CS1_START 0x80010000
+#define CFG_CS1_SIZE 0x00001000
+#define CFG_CS1_CFG 0x1d300
+
+/*
+ * Select one of quarts as a default
+ * console. If undefined - PSC console
+ * wil be default
+ */
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CFG_RESET_ADDRESS 0xff000000
+/*
+ * QUART Expanders support
+ */
+#if defined(CONFIG_QUART_CONSOLE)
+/*
+ * We'll use NS16550 chip routines,
+ */
+#define CFG_NS16550 1
+#define CFG_NS16550_SERIAL 1
+#define CONFIG_CONS_INDEX 1
+/*
+ * To achieve necessary offset on SC16C554
+ * A0-A2 (register select) pins with NS16550
+ * functions (in struct NS16550), REG_SIZE
+ * should be 4, because A0-A2 pins are connected
+ * to DA2-DA4 address bus lines.
+ */
+#define CFG_NS16550_REG_SIZE 4
+/*
+ * LocalPlus Bus already inited in cpu_init_f(),
+ * so can work with QUART's chip selects.
+ * One of four SC16C554 UARTs is selected with
+ * A3-A4 (DA5-DA6) lines.
+ */
+#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
+#define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
+#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
+#define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
+#elif
+#error "Wrong QUART expander number."
+#endif
+
+/*
+ * SC16C554 chip's external crystal oscillator frequency
+ * is 7.3728 MHz
+ */
+#define CFG_NS16550_CLK 7372800
+#endif /* CONFIG_QUART_CONSOLE */
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index ea15524..072b9dd 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -1,9 +1,9 @@
/*
* ppmc7xx.h
* ---------
- *
+ *
* Wind River PPMC 7xx/74xx board configuration file.
- *
+ *
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
@@ -16,15 +16,15 @@
/*===================================================================
- *
+ *
* User configurable settings - Modify to your preference
- *
+ *
*===================================================================
*/
/*
* Debug
- *
+ *
* DEBUG - Define this is you want extra debug info
* GTREGREAD - Required to build with debug
* do_bdinfo - Required to build with debug
@@ -37,7 +37,7 @@
/*
* CPU type
- *
+ *
* CONFIG_7xx - We have a 750 or 755 CPU
* CONFIG_74xx - We have a 7400 CPU
* CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
@@ -52,11 +52,11 @@
/*
* Monitor configuration
- *
+ *
* CONFIG_COMMANDS - List of command sets to include in shell
- *
+ *
* The following command sets have been tested and known to work:
- *
+ *
* CFG_CMD_CACHE - Cache control commands
* CFG_CMD_MEMORY - Memory display, change and test commands
* CFG_CMD_FLASH - Erase and program flash
@@ -91,7 +91,7 @@
/*
* PCI config
- *
+ *
* CONFIG_PCI - Enable PCI bus
* CONFIG_PCI_PNP - Enable Plug & Play support
* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
@@ -104,7 +104,7 @@
/*
* Network config
- *
+ *
* CONFIG_NET_MULTI - Support for multiple network interfaces
* CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
* CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
@@ -117,18 +117,18 @@
/*
* Enable extra init functions
- *
+ *
* CONFIG_MISC_INIT_F - Call pre-relocation init functions
* CONFIG_MISC_INIT_R - Call post relocation init functions
*/
#undef CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
+#define CONFIG_MISC_INIT_R
/*
* Boot config
- *
+ *
* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
* CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
*/
@@ -142,9 +142,9 @@
/*===================================================================
- *
+ *
* Board configuration settings - You should not need to modify these
- *
+ *
*===================================================================
*/
@@ -154,9 +154,9 @@
/*
* Memory map
- *
+ *
* This board runs in a standard CHRP (Map-B) configuration.
- *
+ *
* Type Start End Size Width Chip Sel
* ----------- ----------- ----------- ------- ------- --------
* SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
@@ -164,9 +164,9 @@
* UART 0x7C000000 RCS2
* Mailbox 0xFF000000 RCS1
* Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
- *
+ *
* Flash sectors are laid out as follows.
- *
+ *
* Sector Start End Size Comments
* ------- ----------- ----------- ------- -----------
* 0 0xFFC00000 0xFFC3FFFF 256KB
@@ -193,7 +193,7 @@
/*
* SDRAM config - see memory map details above.
- *
+ *
* CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
* CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
*/
@@ -202,9 +202,9 @@
#define CFG_SDRAM_SIZE 0x04000000
-/*
+/*
* Flash config - see memory map details above.
- *
+ *
* CFG_FLASH_BASE - Start address of flash memory
* CFG_FLASH_SIZE - Total size of contiguous flash mem
* CFG_FLASH_ERASE_TOUT - Erase timeout in ms
@@ -223,7 +223,7 @@
/*
* Monitor config - see memory map details above
- *
+ *
* CFG_MONITOR_BASE - Base address of monitor code
* CFG_MALLOC_LEN - Size of malloc pool (128KB)
*/
@@ -234,7 +234,7 @@
/*
* Command shell settings
- *
+ *
* CFG_BARGSIZE - Boot Argument buffer size
* CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
* CFG_CBSIZE - Console Buffer (input) size
@@ -261,10 +261,10 @@
/*
* Environment config - see memory map details above
- *
+ *
* CFG_ENV_IS_IN_FLASH - The env variables are stored in flash
* CFG_ENV_ADDR - Address of the sector containing env vars
- * CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
+ * CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
* CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
*/
@@ -282,7 +282,7 @@
* Since the main system RAM is initialised very early, we place the INIT_RAM
* in the main system RAM just above the exception vectors. The contents are
* copied to top of RAM by the init code.
- *
+ *
* CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
* CFG_INIT_RAM_END - Size of Init RAM
* CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
@@ -297,7 +297,7 @@
/*
* Initial BAT config
- *
+ *
* BAT0 - System SDRAM
* BAT1 - LED's and Serial Port
* BAT2 - PCI Memory
@@ -327,7 +327,7 @@
/*
* Cache config
- *
+ *
* CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
* CFG_L2 - L2 cache enabled if defined
* L2_INIT - L2 cache init flags
@@ -342,7 +342,7 @@
/*
* Clocks config
- *
+ *
* CFG_BUS_HZ - Bus clock frequency in Hz
* CFG_BUS_CLK - As above (?)
* CFG_HZ - Decrementer freq in Hz
@@ -355,7 +355,7 @@
/*
* Serial port config
- *
+ *
* CFG_BAUDRATE_TABLE - List of valid baud rates
* CFG_NS16550 - Include the NS16550 driver
* CFG_NS16550_SERIAL - Include the serial (wrapper) driver
@@ -398,7 +398,7 @@
/*
* Extra init functions
- *
+ *
* CFG_BOARD_ASM_INIT - Call assembly init code
*/
@@ -407,11 +407,11 @@
/*
* Boot flags
- *
+ *
* BOOTFLAG_COLD - Indicates a power-on boot
* BOOTFLAG_WARM - Indicates a software reset
*/
-
+
#define BOOTFLAG_COLD 0x01
#define BOOTFLAG_WARM 0x02
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
new file mode 100644
index 0000000..866f7b0
--- /dev/null
+++ b/include/configs/sbc2410x.h
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Modified for the friendly-arm SBC-2410X by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * Configuation settings for the friendly-arm SBC-2410X board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
+#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
+
+
+#define USE_920T_MMU 1
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
+#define CS8900_BASE 0x19000300
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define CONFIG_RTC_S3C24X0 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#define CONFIG_COMMANDS \
+ (CONFIG_CMD_DFL | \
+ CFG_CMD_CACHE | \
+ /*CFG_CMD_NAND |*/ \
+ /*CFG_CMD_EEPROM |*/ \
+ /*CFG_CMD_I2C |*/ \
+ /*CFG_CMD_USB |*/ \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_DATE | \
+ CFG_CMD_PING | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.69
+#define CONFIG_SERVERIP 192.168.0.1
+/*#define CONFIG_BOOTFILE "elinos-lart" */
+#define CONFIG_BOOTCOMMAND "dhcp; bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x33000000 /* default load address */
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define CFG_HZ 1562500
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
+
+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
+#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#endif
+
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
+#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#endif
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * NAND flash settings
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_WAIT_READY(nand) NF_WaitRB()
+#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
+#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
+#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
+#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
+#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
+#define WRITE_NAND(d, adr) NF_Write(d)
+#define READ_NAND(adr) NF_Read()
+/* the following functions are NOP's because S3C24X0 handles this in hardware */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
+#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#else
+#define CONFIG_AUTO_COMPLETE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
new file mode 100644
index 0000000..9d3609a
--- /dev/null
+++ b/include/configs/spc1920.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
+ *
+ * Configuation settings for the SPC1920 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __H
+#define __CONFIG_H
+
+#define CONFIG_SPC1920 1 /* SPC1920 board */
+#define CONFIG_MPC885 1 /* MPC885 CPU */
+
+#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_MII
+/* #define MII_DEBUG */
+/* #define CONFIG_FEC_ENET */
+#undef CONFIG_ETHER_ON_FEC1
+#define CONFIG_ETHER_ON_FEC2
+#define FEC_ENET
+/* #define CONFIG_FEC2_PHY_NORXERR */
+/* #define CFG_DISCOVER_PHY */
+/* #define CONFIG_PHY_ADDR 0x1 */
+#define CONFIG_FEC2_PHY 1
+
+#define CONFIG_BAUDRATE 19200
+
+/* use PLD CLK4 instead of brg */
+#undef CFG_SPC1920_SMC1_CLK4
+
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
+#define CFG_8xx_CPUCLK_MIN 40000000
+#define CFG_8xx_CPUCLK_MAX 133000000
+
+#define CFG_RESET_ADDRESS 0xf8000000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+
+#if 1
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "dhcp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
+ "bootm"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
+ "bootm fe080000"
+
+#undef CONFIG_BOOTARGS
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
+
+#ifndef CONFIG_COMMANDS
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_ECHO \
+ | CFG_CMD_IMMAP \
+ | CFG_CMD_JFFS2 \
+ | CFG_CMD_PING \
+ | CFG_CMD_DHCP \
+ | CFG_CMD_IMMAP \
+ | CFG_CMD_MII)
+ /* & ~( CFG_CMD_NET)) */
+
+
+#endif /* !CONFIG_COMMANDS */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=>" /* Monitor Command Prompt */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR 0x00100000
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
+
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
+#else
+#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
+#endif /* CONFIG_BZIP2 */
+
+#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
+
+/*
+ * Flash
+ */
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CFG_FLASH_BASE 0xFE000000
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+
+/*-----------------------------------------------------------------------
+ * I2C configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
+#define CFG_I2C_SLAVE 0x7F
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+/* #define CFG_SCCR SCCR_TBS */
+#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Enable Register
+ *-----------------------------------------------------------------------
+ * Set to zero to prevent the processor from entering debug mode
+ */
+#define CFG_DER 0
+
+
+/* Because of the way the 860 starts up and assigns CS0 the entire
+ * address space, we have to set the memory controller differently.
+ * Normally, you write the option register first, and then enable the
+ * chip select by writing the base register. For CS0, you must write
+ * the base register first, followed by the option register.
+ */
+
+
+/*
+ * Init Memory Controller:
+ */
+
+/* BR0 and OR0 (FLASH) */
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+
+/*
+ * SDRAM CS1 UPMB
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
+#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
+
+#define CFG_PRELIM_OR1_AM 0xF0000000
+/* #define CFG_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
+#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
+
+#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
+#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
+
+/* #define CFG_OR1_FINAL ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
+/* #define CFG_BR1_FINAL ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
+
+#define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
+#define CFG_PTA_PER_CLK 195
+#define CFG_MBMR_PTB 195
+#define CFG_MPTPR MPTPR_PTP_DIV16
+#define CFG_MAR 0x88
+
+#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
+ MBMR_AMB_TYPE_0 | \
+ MBMR_G0CLB_A10 | \
+ MBMR_DSB_1_CYCL | \
+ MBMR_RLFB_1X | \
+ MBMR_WLFB_1X | \
+ MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
+
+#define CFG_MBMR_9COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
+ MBMR_AMB_TYPE_1 | \
+ MBMR_G0CLB_A10 | \
+ MBMR_DSB_1_CYCL | \
+ MBMR_RLFB_1X | \
+ MBMR_WLFB_1X | \
+ MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
+
+
+/* PLD CS5 */
+#define CFG_SPC1920_PLD_BASE 0x80000000
+#define CFG_PRELIM_OR5_AM 0xffff8000
+
+#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
+ OR_CSNT_SAM | \
+ OR_ACS_DIV1 | \
+ OR_BI | \
+ OR_SCY_0_CLK | \
+ OR_TRLX)
+
+#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+/* #define CFG_PLD_BASE 0x30000000 */
+/* #define CFG_OR5_PRELIM 0xffff1110 */
+/* #define CFG_BR5_PRELIM 0x30000401 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index 9ebb51e..f40dde2 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -452,32 +452,25 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
-#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
-#if defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#define CFG_CS2_CFG 0x0004D930
-#endif
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
-#if defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
-#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 8f71acf..a2dc8e7 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -402,7 +402,7 @@
#endif
/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_ERASE_TOUT (15*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_FLASH 1
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 952f73b..825bfd1 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -119,9 +119,9 @@
/*
* Definitions related to passing arguments to kernel.
*/
-#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
-#undef CONFIG_INITRD_TAG /* do not send initrd params */
+#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG 1 /* do not send initrd params */
#undef CONFIG_VFD /* do not send framebuffer setup */
/*
diff --git a/include/galileo/core.h b/include/galileo/core.h
index 0735d07..49f4dd2 100644
--- a/include/galileo/core.h
+++ b/include/galileo/core.h
@@ -110,7 +110,10 @@
#define _1G 0x40000000
#define _2G 0x80000000
+#ifndef BOOL_WAS_DEFINED
+#define BOOL_WAS_DEFINED
typedef enum _bool{false,true} bool;
+#endif
/* Little to Big endian conversion macros */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index a522718..4b48564 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -2,7 +2,7 @@
* linux/include/linux/mtd/nand.h
*
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- * Steven J. Hill <sjhill@realitydiluted.com>
+ * Steven J. Hill <sjhill@realitydiluted.com>
* Thomas Gleixner <tglx@linutronix.de>
*
* $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
@@ -15,15 +15,15 @@
* Contains standard defines and IDs for NAND flash devices
*
* Changelog:
- * 01-31-2000 DMW Created
- * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
+ * 01-31-2000 DMW Created
+ * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
* so it can be used by other NAND flash device
* drivers. I also changed the copyright since none
* of the original contents of this file are specific
* to DoC devices. David can whack me with a baseball
* bat later if I did something naughty.
- * 10-11-2000 SJH Added private NAND flash structure for driver
- * 10-24-2000 SJH Added prototype for 'nand_scan' function
+ * 10-11-2000 SJH Added private NAND flash structure for driver
+ * 10-24-2000 SJH Added prototype for 'nand_scan' function
* 10-29-2001 TG changed nand_chip structure to support
* hardwarespecific function for accessing control lines
* 02-21-2002 TG added support for different read/write adress and
@@ -36,7 +36,7 @@
* CONFIG_MTD_NAND_ECC_JFFS2 is not set
* 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
*
- * 08-29-2002 tglx nand_chip structure: data_poi for selecting
+ * 08-29-2002 tglx nand_chip structure: data_poi for selecting
* internal / fs-driver buffer
* support for 6byte/512byte hardware ECC
* read_ecc, write_ecc extended for different oob-layout
@@ -45,8 +45,8 @@
* 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
* Split manufacturer and device ID structures
*
- * 02-08-2004 tglx added option field to nand structure for chip anomalities
- * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
+ * 02-08-2004 tglx added option field to nand structure for chip anomalities
+ * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
* update of nand_chip structure description
*/
#ifndef __LINUX_MTD_NAND_H
@@ -75,7 +75,7 @@
* Constants for hardware specific CLE/ALE/NCE function
*/
/* Select the chip by setting nCE to low */
-#define NAND_CTL_SETNCE 1
+#define NAND_CTL_SETNCE 1
/* Deselect the chip by setting nCE to high */
#define NAND_CTL_CLRNCE 2
/* Select the command latch by setting CLE to high */
@@ -215,7 +215,7 @@
#if 0
/**
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
- * @lock: protection lock
+ * @lock: protection lock
* @active: the mtd device which holds the controller currently
*/
struct nand_hw_control {
@@ -244,20 +244,20 @@
* is read from the chip status register
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
- * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
+ * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
* @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
* @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
* be provided if a hardware ECC is available
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
* @scan_bbt: [REPLACEABLE] function to scan bad block table
* @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
- * @eccsize: [INTERN] databytes used per ecc-calculation
- * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
+ * @eccsize: [INTERN] databytes used per ecc-calculation
+ * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
* @eccsteps: [INTERN] number of ecc calculation steps per page
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
* @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
- * @state: [INTERN] the current state of the NAND device
+ * @state: [INTERN] the current state of the NAND device
* @page_shift: [INTERN] number of address bits in a page (column address bits)
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
@@ -284,7 +284,7 @@
struct nand_chip {
void __iomem *IO_ADDR_R;
- void __iomem *IO_ADDR_W;
+ void __iomem *IO_ADDR_W;
u_char (*read_byte)(struct mtd_info *mtd);
void (*write_byte)(struct mtd_info *mtd, u_char byte);
@@ -297,12 +297,12 @@
void (*select_chip)(struct mtd_info *mtd, int chip);
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
- void (*hwcontrol)(struct mtd_info *mtd, int cmd);
- int (*dev_ready)(struct mtd_info *mtd);
- void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
- int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
+ void (*hwcontrol)(struct mtd_info *mtd, int cmd);
+ int (*dev_ready)(struct mtd_info *mtd);
+ void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
+ int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
- int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+ int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
void (*enable_hwecc)(struct mtd_info *mtd, int mode);
void (*erase_cmd)(struct mtd_info *mtd, int page);
int (*scan_bbt)(struct mtd_info *mtd);
@@ -310,17 +310,17 @@
int eccsize;
int eccbytes;
int eccsteps;
- int chip_delay;
+ int chip_delay;
#if 0
spinlock_t chip_lock;
wait_queue_head_t wq;
- nand_state_t state;
+ nand_state_t state;
#endif
- int page_shift;
+ int page_shift;
int phys_erase_shift;
int bbt_erase_shift;
int chip_shift;
- u_char *data_buf;
+ u_char *data_buf;
u_char *oob_buf;
int oobdirty;
u_char *data_poi;
@@ -335,7 +335,7 @@
struct nand_bbt_descr *bbt_td;
struct nand_bbt_descr *bbt_md;
struct nand_bbt_descr *badblock_pattern;
- struct nand_hw_control *controller;
+ struct nand_hw_control *controller;
void *priv;
};
@@ -352,14 +352,14 @@
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
*
- * @name: Identify the device type
- * @id: device ID code
- * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
+ * @name: Identify the device type
+ * @id: device ID code
+ * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
* If the pagesize is 0, then the real pagesize
* and the eraseize are determined from the
* extended id bytes in the chip
- * @erasesize: Size of an erase block in the flash device.
- * @chipsize: Total chipsize in Mega Bytes
+ * @erasesize: Size of an erase block in the flash device.
+ * @chipsize: Total chipsize in Mega Bytes
* @options: Bitfield to store chip relevant options
*/
struct nand_flash_dev {
@@ -374,7 +374,7 @@
/**
* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
* @name: Manufacturer name
- * @id: manufacturer ID code of device.
+ * @id: manufacturer ID code of device.
*/
struct nand_manufacturers {
int id;
@@ -398,7 +398,7 @@
* blocks is reserved at the end of the device where the tables are
* written.
* @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
- * bad) block in the stored bbt
+ * bad) block in the stored bbt
* @pattern: pattern to identify bad block table or factory marked good /
* bad blocks, can be NULL, if len = 0
*
@@ -412,11 +412,11 @@
int pages[NAND_MAX_CHIPS];
int offs;
int veroffs;
- uint8_t version[NAND_MAX_CHIPS];
+ uint8_t version[NAND_MAX_CHIPS];
int len;
- int maxblocks;
+ int maxblocks;
int reserved_block_code;
- uint8_t *pattern;
+ uint8_t *pattern;
};
/* Options for the bad block table descriptors */
@@ -428,7 +428,7 @@
#define NAND_BBT_4BIT 0x00000004
#define NAND_BBT_8BIT 0x00000008
/* The bad block table is in the last good block of the device */
-#define NAND_BBT_LASTBLOCK 0x00000010
+#define NAND_BBT_LASTBLOCK 0x00000010
/* The bbt is at the given page, else we must scan for the bbt */
#define NAND_BBT_ABSPAGE 0x00000020
/* The bbt is at the given page, else we must scan for the bbt */
@@ -451,7 +451,7 @@
#define NAND_BBT_SCAN2NDPAGE 0x00004000
/* The maximum number of blocks to scan for a bbt */
-#define NAND_BBT_SCAN_MAXBLOCKS 4
+#define NAND_BBT_SCAN_MAXBLOCKS 4
extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
diff --git a/include/ns16550.h b/include/ns16550.h
index 996d915..34888a1 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -7,7 +7,7 @@
* added prototypes for ns16550.c
* reduced no of com ports to 2
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
+ *
* added support for port on 64-bit bus
* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
*/
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 43d4510..8f564da 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -308,4 +308,14 @@
#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */
+#ifdef CONFIG_8xx
+extern u_int *pcmcia_pgcrx[];
+#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \
+ || defined(CONFIG_PXA_PCMCIA)
+extern int check_ide_device(int slot);
+#endif
+
#endif /* _PCMCIA_H */
diff --git a/include/usb.h b/include/usb.h
index 39d7f23..bf71554 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -108,6 +108,7 @@
unsigned char iInterface;
unsigned char no_of_ep;
+ unsigned char num_altsetting;
unsigned char act_altsetting;
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
} __attribute__ ((packed));
diff --git a/include/xyzModem.h b/include/xyzModem.h
index 4ec10b5..f437bbd 100644
--- a/include/xyzModem.h
+++ b/include/xyzModem.h
@@ -97,7 +97,10 @@
#endif
} connection_info_t;
+#ifndef BOOL_WAS_DEFINED
+#define BOOL_WAS_DEFINED
typedef unsigned int bool;
+#endif
#define false 0
#define true 1
diff --git a/lib_i386/i386_linux.c b/lib_i386/i386_linux.c
index e5d8eea..b4a6f5a 100644
--- a/lib_i386/i386_linux.c
+++ b/lib_i386/i386_linux.c
@@ -151,6 +151,12 @@
initrd_end = 0;
}
+ /* if multi-part image, we need to advance base ptr */
+ if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) {
+ int i;
+ for (i=0, addr+=sizeof(int); len_ptr[i++]; addr+=sizeof(int));
+ }
+
base_ptr = load_zimage((void*)addr + sizeof(image_header_t), ntohl(hdr->ih_size),
initrd_start, initrd_end-initrd_start, 0);
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index dbb752e..db80f77 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -270,7 +270,8 @@
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
get_clocks, /* get CPU and bus clocks (etc.) */
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+ && !defined(CONFIG_TQM885D)
adjust_sdram_tbs_8xx,
#endif
init_timebase,
diff --git a/mkconfig b/mkconfig
index 54775d3..4fe6e44 100755
--- a/mkconfig
+++ b/mkconfig
@@ -9,19 +9,23 @@
#
APPEND=no # Default: Create new config file
+BOARD_NAME="" # Name to print in make output
while [ $# -gt 0 ] ; do
case "$1" in
--) shift ; break ;;
-a) shift ; APPEND=yes ;;
+ -n) shift ; BOARD_NAME="${1%%_config}" ; shift ;;
*) break ;;
esac
done
+[ "${BOARD_NAME}" ] || BOARD_NAME="$1"
+
[ $# -lt 4 ] && exit 1
[ $# -gt 6 ] && exit 1
-echo "Configuring for $1 board..."
+echo "Configuring for ${BOARD_NAME} board..."
cd ./include