* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 3ec27b8..c96b98b 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -41,9 +41,12 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
/*
* When initializing flash, if we cannot find the manufacturer ID,
@@ -360,7 +363,9 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
@@ -368,7 +373,9 @@
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
-#define CONFIG_ETHPRIME "MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */