| commit | db14f11dfe348550d8c10c6609277488d9f500d6 | [log] [tgz] |
|---|---|---|
| author | Zhichun Hua <zhichun.hua@freescale.com> | Mon Jun 29 15:50:42 2015 +0800 |
| committer | York Sun <yorksun@freescale.com> | Mon Jul 20 11:44:40 2015 -0700 |
| tree | 22d4e2a1e32e8f9d626a65173b994b49de54bb07 | |
| parent | 21a257b9b3b29ddb1445fdafe12e05727080a198 [diff] |
armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup. When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>