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wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf4675562002-10-02 14:20:15 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
22
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenkf4675562002-10-02 14:20:15 +000025#ifdef CONFIG_LCD /* with LCD controller ? */
Jeroen Hofstee59155f42013-01-22 10:44:09 +000026#define CONFIG_MPC8XX_LCD
Wolfgang Denk21f971e2008-07-07 01:22:29 +020027#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
28#define CONFIG_LCD_INFO 1 /* ... and some board info */
wdenk27b207f2003-07-24 23:38:38 +000029#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenkf4675562002-10-02 14:20:15 +000030#endif
31
32#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020033#define CONFIG_SYS_SMC_RXBUFLEN 128
34#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000035#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf4675562002-10-02 14:20:15 +000036
wdenkae3af052003-08-07 22:18:11 +000037#define CONFIG_BOOTCOUNT_LIMIT
38
39#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000040
41#define CONFIG_BOARD_TYPES 1 /* support board types */
42
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010043#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf4675562002-10-02 14:20:15 +000044
45#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000046
47#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000048 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000049 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010050 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000051 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010052 "addip=setenv bootargs ${bootargs} " \
53 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
54 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000055 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010056 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000057 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010058 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
59 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000060 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020061 "hostname=TQM823L\0" \
62 "bootfile=TQM823L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020063 "fdt_addr=40040000\0" \
64 "kernel_addr=40060000\0" \
65 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020066 "u-boot=TQM823L/u-image.bin\0" \
67 "load=tftp 200000 ${u-boot}\0" \
68 "update=prot off 40000000 +${filesize};" \
69 "era 40000000 +${filesize};" \
70 "cp.b 200000 40000000 ${filesize};" \
71 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000072 ""
73#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000074
75#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000077
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
wdenka522fa02004-01-04 22:51:12 +000080#if defined(CONFIG_LCD)
wdenkf4675562002-10-02 14:20:15 +000081# undef CONFIG_STATUS_LED /* disturbs display */
82#else
83# define CONFIG_STATUS_LED 1 /* Status LED enabled */
84#endif /* CONFIG_LCD */
85
wdenka522fa02004-01-04 22:51:12 +000086#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
wdenkf4675562002-10-02 14:20:15 +000087
Jon Loeliger37d4bb72007-07-09 21:38:02 -050088/*
89 * BOOTP options
90 */
91#define CONFIG_BOOTP_SUBNETMASK
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94#define CONFIG_BOOTP_BOOTPATH
95#define CONFIG_BOOTP_BOOTFILESIZE
96
wdenkf4675562002-10-02 14:20:15 +000097
98#define CONFIG_MAC_PARTITION
99#define CONFIG_DOS_PARTITION
100
101#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
102
Jon Loeliger26946902007-07-04 22:30:50 -0500103
104/*
105 * Command line configuration.
106 */
107#include <config_cmd_default.h>
108
109#define CONFIG_CMD_ASKENV
110#define CONFIG_CMD_DATE
111#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200112#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100113#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500114#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200115#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500116#define CONFIG_CMD_NFS
117#define CONFIG_CMD_SNTP
118
wdenk27b207f2003-07-24 23:38:38 +0000119#ifdef CONFIG_SPLASH_SCREEN
Jon Loeliger26946902007-07-04 22:30:50 -0500120 #define CONFIG_CMD_BMP
wdenk27b207f2003-07-24 23:38:38 +0000121#endif
wdenkf4675562002-10-02 14:20:15 +0000122
wdenkf4675562002-10-02 14:20:15 +0000123
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200124#define CONFIG_NETCONSOLE
125
wdenkf4675562002-10-02 14:20:15 +0000126/*
127 * Miscellaneous configurable options
128 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_LONGHELP /* undef to save memory */
130#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk6aff3112002-12-17 01:51:00 +0000131
Wolfgang Denk2751a952006-10-28 02:29:14 +0200132#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenk6aff3112002-12-17 01:51:00 +0000134
Jon Loeliger26946902007-07-04 22:30:50 -0500135#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000137#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000139#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
141#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
142#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
145#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf4675562002-10-02 14:20:15 +0000150
wdenkf4675562002-10-02 14:20:15 +0000151/*
152 * Low Level Configuration Settings
153 * (address mappings, register initial values, etc.)
154 * You should know what you are doing if you make changes here.
155 */
156/*-----------------------------------------------------------------------
157 * Internal Memory Mapped Register
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000160
161/*-----------------------------------------------------------------------
162 * Definitions for initial stack pointer and data area (in DPRAM)
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200165#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200166#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_SDRAM_BASE 0x00000000
175#define CONFIG_SYS_FLASH_BASE 0x40000000
176#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
177#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
178#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000179
180/*
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000186
187/*-----------------------------------------------------------------------
188 * FLASH organization
189 */
wdenkf4675562002-10-02 14:20:15 +0000190
Martin Krausee318d9e2007-09-27 11:10:08 +0200191/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200193#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
195#define CONFIG_SYS_FLASH_EMPTY_INFO
196#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
197#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
198#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000199
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200200#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
202#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000203
204/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200205#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
206#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200209
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200210#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
211
wdenkf4675562002-10-02 14:20:15 +0000212/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200213 * Dynamic MTD partition support
214 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100215#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200216#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
217#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200218#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
219
220#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
221 "128k(dtb)," \
222 "1664k(kernel)," \
223 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200224 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200225
226/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000227 * Hardware Information Block
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
230#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
231#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000232
233/*-----------------------------------------------------------------------
234 * Cache Configuration
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500237#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000239#endif
240
241/*-----------------------------------------------------------------------
242 * SYPCR - System Protection Control 11-9
243 * SYPCR can only be written once after reset!
244 *-----------------------------------------------------------------------
245 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
246 */
247#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000249 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
250#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000252#endif
253
254/*-----------------------------------------------------------------------
255 * SIUMCR - SIU Module Configuration 11-6
256 *-----------------------------------------------------------------------
257 * PCMCIA config., multi-function pin tri-state
258 */
259#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000261#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000263#endif /* CONFIG_CAN_DRIVER */
264
265/*-----------------------------------------------------------------------
266 * TBSCR - Time Base Status and Control 11-26
267 *-----------------------------------------------------------------------
268 * Clear Reference Interrupt Status, Timebase freezing enabled
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000271
272/*-----------------------------------------------------------------------
273 * RTCSC - Real-Time Clock Status and Control Register 11-27
274 *-----------------------------------------------------------------------
275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000277
278/*-----------------------------------------------------------------------
279 * PISCR - Periodic Interrupt Status and Control 11-31
280 *-----------------------------------------------------------------------
281 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000284
285/*-----------------------------------------------------------------------
286 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
287 *-----------------------------------------------------------------------
288 * Reset PLL lock status sticky bit, timer expired status bit and timer
289 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000292
293/*-----------------------------------------------------------------------
294 * SCCR - System Clock and reset Control Register 15-27
295 *-----------------------------------------------------------------------
296 * Set clock output, timebase and RTC source and divider,
297 * power management and some other internal clocks
298 */
299#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000301 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
302 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000303
304/*-----------------------------------------------------------------------
305 * PCMCIA stuff
306 *-----------------------------------------------------------------------
307 *
308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
310#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
311#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
312#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
313#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
314#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
315#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
316#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000317
318/*-----------------------------------------------------------------------
319 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
320 *-----------------------------------------------------------------------
321 */
322
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000323#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf4675562002-10-02 14:20:15 +0000324#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
325
326#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
327#undef CONFIG_IDE_LED /* LED for ide not supported */
328#undef CONFIG_IDE_RESET /* reset for ide not supported */
329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
331#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000336
337/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000339
340/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000342
343/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000345
346/*-----------------------------------------------------------------------
347 *
348 *-----------------------------------------------------------------------
349 *
350 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000352
353/*
354 * Init Memory Controller:
355 *
356 * BR0/1 and OR0/1 (FLASH)
357 */
358
359#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
360#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
361
362/* used to re-map FLASH both when starting from SRAM or FLASH:
363 * restrict access enough to keep SRAM working (if any)
364 * but not too much to meddle with FLASH accesses
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
367#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000368
369/*
370 * FLASH timing:
371 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000373 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
376#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
377#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
380#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
381#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000382
383/*
384 * BR2/3 and OR2/3 (SDRAM)
385 *
386 */
387#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
388#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
389#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
390
391/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
395#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000396
397#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
399#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000400#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
402#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
403#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
404#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000405 BR_PS_8 | BR_MS_UPMB | BR_V )
406#endif /* CONFIG_CAN_DRIVER */
407
408/*
409 * Memory Periodic Timer Prescaler
410 *
411 * The Divider for PTA (refresh timer) configuration is based on an
412 * example SDRAM configuration (64 MBit, one bank). The adjustment to
413 * the number of chip selects (NCS) and the actually needed refresh
414 * rate is done by setting MPTPR.
415 *
416 * PTA is calculated from
417 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
418 *
419 * gclk CPU clock (not bus clock!)
420 * Trefresh Refresh cycle * 4 (four word bursts used)
421 *
422 * 4096 Rows from SDRAM example configuration
423 * 1000 factor s -> ms
424 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
425 * 4 Number of refresh cycles per period
426 * 64 Refresh cycle in ms per number of rows
427 * --------------------------------------------
428 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
429 *
430 * 50 MHz => 50.000.000 / Divider = 98
431 * 66 Mhz => 66.000.000 / Divider = 129
432 * 80 Mhz => 80.000.000 / Divider = 156
433 */
wdenke9132ea2004-04-24 23:23:30 +0000434
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
436#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000437
438/*
439 * For 16 MBit, refresh rates could be 31.3 us
440 * (= 64 ms / 2K = 125 / quad bursts).
441 * For a simpler initialization, 15.6 us is used instead.
442 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
444 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000445 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
447#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000448
449/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
451#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000452
453/*
454 * MAMR settings for SDRAM
455 */
456
457/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000459 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
460 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
461/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000463 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
464 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
465
Heiko Schocher7026ead2010-02-09 15:50:27 +0100466/* pass open firmware flat tree */
467#define CONFIG_OF_LIBFDT 1
468#define CONFIG_OF_BOARD_SETUP 1
469#define CONFIG_HWCONFIG 1
470
wdenkf4675562002-10-02 14:20:15 +0000471#endif /* __CONFIG_H */