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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuation settings for the WindRiver PPMC8260 board.
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*****************************************************************************
38 *
39 * These settings must match the way _your_ board is set up
40 *
41 *****************************************************************************/
42
43/* What is the oscillator's (UX2) frequency in Hz? */
44#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
45
46/*-----------------------------------------------------------------------
47 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
48 *-----------------------------------------------------------------------
49 * What should MODCK_H be? It is dependent on the oscillator
50 * frequency, MODCK[1-3], and desired CPM and core frequencies.
51 * Here are some example values (all frequencies are in MHz):
52 *
53 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
54 * ------- ---------- --- --- ---- ----- ----- -----
55 * 0x2 0x2 33 133 133 Close Open Close
56 * 0x2 0x3 33 133 166 Close Open Open
57 * 0x2 0x4 33 133 200 Open Close Close
58 * 0x2 0x5 33 133 233 Open Close Open
59 * 0x2 0x6 33 133 266 Open Open Close
60 *
61 * 0x5 0x5 66 133 133 Open Close Open
62 * 0x5 0x6 66 133 166 Open Open Close
63 * 0x5 0x7 66 133 200 Open Open Open
64 * 0x6 0x0 66 133 233 Close Close Close
65 * 0x6 0x1 66 133 266 Close Close Open
66 * 0x6 0x2 66 133 300 Close Open Close
67 */
68#define CFG_PPMC_MODCK_H 0x05
69
70/* Define this if you want to boot from 0x00000100. If you don't define
71 * this, you will need to program the bootloader to 0xfff00000, and
72 * get the hardware reset config words at 0xfe000000. The simplest
73 * way to do that is to program the bootloader at both addresses.
74 * It is suggested that you just let U-Boot live at 0x00000000.
75 */
76#define CFG_PPMC_BOOT_LOW 1
77
78/* What should the base address of the main FLASH be and how big is
79 * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
80 * The main FLASH is whichever is connected to *CS0. U-Boot expects
81 * this to be the SIMM.
82 */
83#define CFG_FLASH0_BASE 0xFE000000
84#define CFG_FLASH0_SIZE 16
85
86/* What should be the base address of the first SDRAM DIMM and how big is
87 * it (in Mbytes)?
88*/
89#define CFG_SDRAM0_BASE 0x00000000
90#define CFG_SDRAM0_SIZE 128
91
92/* What should be the base address of the second SDRAM DIMM and how big is
93 * it (in Mbytes)?
94*/
95#define CFG_SDRAM1_BASE 0x08000000
96#define CFG_SDRAM1_SIZE 128
97
98/* What should be the base address of the on board SDRAM and how big is
99 * it (in Mbytes)?
100*/
101#define CFG_SDRAM2_BASE 0x38000000
102#define CFG_SDRAM2_SIZE 16
103
104/* What should be the base address of the MAILBOX and how big is it
105 * (in Bytes)
106 * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000
107 */
108#define CFG_MAILBOX_BASE 0x32000000
109#define CFG_MAILBOX_SIZE 8192
110
111/* What is the base address of the I/O select lines and how big is it
112 * (In Mbytes)?
113 */
114
115#define CFG_IOSELECT_BASE 0xE0000000
116#define CFG_IOSELECT_SIZE 32
117
118
119/* What should be the base address of the LEDs and switch S0?
120 * If you don't want them enabled, don't define this.
121 */
122#define CFG_LED_BASE 0xF1000000
123
124/*
125 * PPMC8260 with 256 16 MB DIMM:
126 *
127 * 0x0000 0000 Exception Vector code, 8k
128 * :
129 * 0x0000 1FFF
130 * 0x0000 2000 Free for Application Use
131 * :
132 * :
133 *
134 * :
135 * :
136 * 0x0FF5 FF30 Monitor Stack (Growing downward)
137 * Monitor Stack Buffer (0x80)
138 * 0x0FF5 FFB0 Board Info Data
139 * 0x0FF6 0000 Malloc Arena
140 * : CFG_ENV_SECT_SIZE, 256k
141 * : CFG_MALLOC_LEN, 128k
142 * 0x0FFC 0000 RAM Copy of Monitor Code
143 * : CFG_MONITOR_LEN, 256k
144 * 0x0FFF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
145 */
146
147
148/*
149 * select serial console configuration
150 *
151 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
152 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
153 * for SCC).
154 *
155 * if CONFIG_CONS_NONE is defined, then the serial console routines must
156 * defined elsewhere.
157 * The console can be on SMC1 or SMC2
158 */
159#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
160#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
161#undef CONFIG_CONS_NONE /* define if console on neither */
162#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
163
164/*
165 * select ethernet configuration
166 *
167 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
168 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
169 * for FCC)
170 *
171 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
172 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
173 * from CONFIG_COMMANDS to remove support for networking.
174 */
175
176#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
177#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
178#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
179#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
180#define CONFIG_MII /* MII PHY management */
181#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
182/*
183 * Port pins used for bit-banged MII communictions (if applicable).
184 */
185#define MDIO_PORT 2 /* Port C */
186#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
187#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
188#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
189
190#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
191 else iop->pdat &= ~0x00400000
192
193#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
194 else iop->pdat &= ~0x00200000
195
196#define MIIDELAY udelay(1)
197
198
199/* Define this to reserve an entire FLASH sector (256 KB) for
200 * environment variables. Otherwise, the environment will be
201 * put in the same sector as U-Boot, and changing variables
202 * will erase U-Boot temporarily
203 */
204#define CFG_ENV_IN_OWN_SECT 1
205
206/* Define to allow the user to overwrite serial and ethaddr */
207#define CONFIG_ENV_OVERWRITE
208
209/* What should the console's baud rate be? */
210#define CONFIG_BAUDRATE 9600
211
212/* Ethernet MAC address */
213
214#define CONFIG_ETHADDR 00:a0:1e:90:2b:00
215
216/* Define this to set the last octet of the ethernet address
217 * from the DS0-DS7 switch and light the leds with the result
218 * The DS0-DS7 switch and the leds are backwards with respect
219 * to each other. DS7 is on the board edge side of both the
220 * led strip and the DS0-DS7 switch.
221 */
222#define CONFIG_MISC_INIT_R
223
224/* Set to a positive value to delay for running BOOTCOMMAND */
225#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
226
227#if 0
228/* Be selective on what keys can delay or stop the autoboot process
229 * To stop use: " "
230 */
231# define CONFIG_AUTOBOOT_KEYED
232# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
233# define CONFIG_AUTOBOOT_STOP_STR " "
234# undef CONFIG_AUTOBOOT_DELAY_STR
235# define DEBUG_BOOTKEYS 0
236#endif
237
238/* Define a command string that is automatically executed when no character
239 * is read on the console interface withing "Boot Delay" after reset.
240 */
wdenkb79a11c2004-03-25 15:14:43 +0000241#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
242#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenkfe8c2802002-11-03 00:38:21 +0000243
wdenk42dfe7a2004-03-14 22:25:36 +0000244#ifdef CONFIG_BOOT_ROOT_INITRD
wdenkfe8c2802002-11-03 00:38:21 +0000245#define CONFIG_BOOTCOMMAND \
246 "version;" \
247 "echo;" \
248 "bootp;" \
249 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100250 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000251 "bootm"
252#endif /* CONFIG_BOOT_ROOT_INITRD */
253
wdenk42dfe7a2004-03-14 22:25:36 +0000254#ifdef CONFIG_BOOT_ROOT_NFS
wdenkfe8c2802002-11-03 00:38:21 +0000255#define CONFIG_BOOTCOMMAND \
256 "version;" \
257 "echo;" \
258 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100259 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
260 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000261 "bootm"
262#endif /* CONFIG_BOOT_ROOT_NFS */
263
264/* Add support for a few extra bootp options like:
265 * - File size
266 * - DNS
267 */
268#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
269 CONFIG_BOOTP_BOOTFILESIZE | \
270 CONFIG_BOOTP_DNS)
271
272/* undef this to save memory */
273#define CFG_LONGHELP
274
275/* Monitor Command Prompt */
276#define CFG_PROMPT "=> "
277
278/* What U-Boot subsytems do you want enabled? */
279#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
280 CFG_CMD_ELF | \
281 CFG_CMD_ASKENV | \
wdenkfe8c2802002-11-03 00:38:21 +0000282 CFG_CMD_REGINFO | \
283 CFG_CMD_MEMTEST | \
284 CFG_CMD_MII | \
285 CFG_CMD_IMMAP)
286
287
288/* Where do the internal registers live? */
289#define CFG_IMMR 0xf0000000
290
291/*****************************************************************************
292 *
293 * You should not have to modify any of the following settings
294 *
295 *****************************************************************************/
296
297#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
298#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500299#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000300
301/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
302#include <cmd_confdefs.h>
303
304/*
305 * Miscellaneous configurable options
306 */
307#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
308# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
309#else
310# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
311#endif
312
313/* Print Buffer Size */
314#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
315
316#define CFG_MAXARGS 32 /* max number of command args */
317
318#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
319
320#define CFG_LOAD_ADDR 0x140000 /* default load address */
321#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
322
323#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
324 /* the exception vector table */
325 /* to the end of the DRAM */
326 /* less monitor and malloc area */
327#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
328#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
329 + CFG_MALLOC_LEN \
330 + CFG_ENV_SECT_SIZE \
331 + CFG_STACK_USAGE )
332
333#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
334 - CFG_MEM_END_USAGE )
335
336/* valid baudrates */
337#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
338
339/*
340 * Low Level Configuration Settings
341 * (address mappings, register initial values, etc.)
342 * You should know what you are doing if you make changes here.
343 */
344
345#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
346/*
347 * Attention: This is board specific
348 * - RX clk is CLK11
349 * - TX clk is CLK12
350 */
351#define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\
352 CMXSCR_TS1CS_CLK12)
353
354#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
355/*
356 * Attention: this is board-specific
357 * - Rx-CLK is CLK13
358 * - Tx-CLK is CLK14
359 * - Select bus for bd/buffers (see 28-13)
360 * - Enable Full Duplex in FSMR
361 */
362#define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
363#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
364#define CFG_CPMFCR_RAMTYPE 0
365#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
366#endif /* CONFIG_ETHER_INDEX */
367
368#define CFG_FLASH_BASE CFG_FLASH0_BASE
369#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
370#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
371#define CFG_SDRAM_SIZE (CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE)
372
373/*-----------------------------------------------------------------------
374 * Hard Reset Configuration Words
375 */
376#if defined(CFG_PPMC_BOOT_LOW)
377# define CFG_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
378#else
379# define CFG_PPMC_HRCW_BOOT_FLAGS (0)
380#endif /* defined(CFG_PPMC_BOOT_LOW) */
381
382/* get the HRCW ISB field from CFG_IMMR */
383#define CFG_PPMC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
384 ((CFG_IMMR & 0x01000000) >> 7) | \
385 ((CFG_IMMR & 0x00100000) >> 4) )
386
387#define CFG_HRCW_MASTER ( HRCW_EBM | \
388 HRCW_BPS11 | \
389 HRCW_L2CPC10 | \
390 HRCW_DPPC00 | \
391 CFG_PPMC_HRCW_IMMR | \
392 HRCW_MMR00 | \
393 HRCW_LBPC00 | \
394 HRCW_APPC10 | \
395 HRCW_CS10PC00 | \
396 (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
397 CFG_PPMC_HRCW_BOOT_FLAGS )
398
399/* no slaves */
400#define CFG_HRCW_SLAVE1 0
401#define CFG_HRCW_SLAVE2 0
402#define CFG_HRCW_SLAVE3 0
403#define CFG_HRCW_SLAVE4 0
404#define CFG_HRCW_SLAVE5 0
405#define CFG_HRCW_SLAVE6 0
406#define CFG_HRCW_SLAVE7 0
407
408/*-----------------------------------------------------------------------
409 * Definitions for initial stack pointer and data area (in DPRAM)
410 */
411#define CFG_INIT_RAM_ADDR CFG_IMMR
412#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
413#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
414#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
415#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
416
417/*-----------------------------------------------------------------------
418 * Start addresses for the final memory configuration
419 * (Set up by the startup code)
420 * Please note that CFG_SDRAM_BASE _must_ start at 0
421 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
422 */
423#define CFG_MONITOR_BASE CFG_FLASH0_BASE
424
425#ifndef CFG_MONITOR_BASE
426#define CFG_MONITOR_BASE 0x0ff80000
427#endif
428
429#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
430# define CFG_RAMBOOT
431#endif
432
433#define CFG_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */
434#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
435
436/*
437 * For booting Linux, the board info and command line data
438 * have to be in the first 8 MB of memory, since this is
439 * the maximum mapped by the Linux kernel during initialization.
440 */
441#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
442
443/*-----------------------------------------------------------------------
444 * FLASH and environment organization
445 */
446
447#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
wdenkbf9e3b32004-02-12 00:47:09 +0000448#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
wdenkfe8c2802002-11-03 00:38:21 +0000449#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
450#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
451#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
452#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
453#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
454
455
456#ifndef CFG_RAMBOOT
457
458# define CFG_ENV_IS_IN_FLASH 1
459# ifdef CFG_ENV_IN_OWN_SECT
460# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
461# define CFG_ENV_SECT_SIZE 0x40000
462# else
463# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
464# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
465# define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
466# endif /* CFG_ENV_IN_OWN_SECT */
467
468#else
469# define CFG_ENV_IS_IN_FLASH 1
470# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
471#define CFG_ENV_SIZE 0x1000
472# define CFG_ENV_SECT_SIZE 0x40000
473#endif /* CFG_RAMBOOT */
474
475/*-----------------------------------------------------------------------
476 * Cache Configuration
477 */
478#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
479
480#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
481# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
482#endif
483
484/*-----------------------------------------------------------------------
485 * HIDx - Hardware Implementation-dependent Registers 2-11
486 *-----------------------------------------------------------------------
487 * HID0 also contains cache control - initially enable both caches and
488 * invalidate contents, then the final state leaves only the instruction
489 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
490 * but Soft reset does not.
491 *
492 * HID1 has only read-only information - nothing to set.
493 */
494#define CFG_HID0_INIT (HID0_ICE |\
495 HID0_DCE |\
496 HID0_ICFI |\
497 HID0_DCI |\
498 HID0_IFEM |\
499 HID0_ABE)
500
501#define CFG_HID0_FINAL (HID0_ICE |\
502 HID0_IFEM |\
503 HID0_ABE |\
504 HID0_EMCP)
505#define CFG_HID2 0
506
507/*-----------------------------------------------------------------------
508 * RMR - Reset Mode Register
509 *-----------------------------------------------------------------------
510 */
511#define CFG_RMR 0
512
513/*-----------------------------------------------------------------------
514 * BCR - Bus Configuration 4-25
515 *-----------------------------------------------------------------------
516 */
517#define CFG_BCR (BCR_EBM |\
518 0x30000000)
519
520/*-----------------------------------------------------------------------
521 * SIUMCR - SIU Module Configuration 4-31
522 * Ref Section 4.3.2.6 page 4-31
523 *-----------------------------------------------------------------------
524 */
525
526#define CFG_SIUMCR (SIUMCR_ESE |\
527 SIUMCR_DPPC00 |\
528 SIUMCR_L2CPC10 |\
529 SIUMCR_LBPC00 |\
530 SIUMCR_APPC10 |\
531 SIUMCR_CS10PC00 |\
532 SIUMCR_BCTLC00 |\
533 SIUMCR_MMR00)
534
535
536/*-----------------------------------------------------------------------
537 * SYPCR - System Protection Control 11-9
538 * SYPCR can only be written once after reset!
539 *-----------------------------------------------------------------------
540 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
541 */
542#define CFG_SYPCR (SYPCR_SWTC |\
543 SYPCR_BMT |\
544 SYPCR_PBME |\
545 SYPCR_LBME |\
546 SYPCR_SWRI |\
547 SYPCR_SWP)
548
549/*-----------------------------------------------------------------------
550 * TMCNTSC - Time Counter Status and Control 4-40
551 *-----------------------------------------------------------------------
552 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
553 * and enable Time Counter
554 */
555#define CFG_TMCNTSC (TMCNTSC_SEC |\
556 TMCNTSC_ALR |\
557 TMCNTSC_TCF |\
558 TMCNTSC_TCE)
559
560/*-----------------------------------------------------------------------
561 * PISCR - Periodic Interrupt Status and Control 4-42
562 *-----------------------------------------------------------------------
563 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
564 * Periodic timer
565 */
566#define CFG_PISCR (PISCR_PS |\
567 PISCR_PTF |\
568 PISCR_PTE)
569
570/*-----------------------------------------------------------------------
571 * SCCR - System Clock Control 9-8
572 *-----------------------------------------------------------------------
573 */
574#define CFG_SCCR 0
575
576/*-----------------------------------------------------------------------
577 * RCCR - RISC Controller Configuration 13-7
578 *-----------------------------------------------------------------------
579 */
580#define CFG_RCCR 0
581
582/*
583 * Initialize Memory Controller:
584 *
585 * Bank Bus Machine PortSz Device
586 * ---- --- ------- ------ ------
587 * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) *
588 * 1 unused
589 * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
590 * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
591 * 4 Local SDRAM 32 bit SDRAM (on board - 16MB)
592 * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB)
593 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
594 * 7 60x GPCM 8 bit LEDs, switches
595 *
596 * (*) This configuration requires the PPMC8260 be configured
597 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
598 * the on board FLASH. In other words, JP24 should have
599 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
600 *
601 */
602
603/*-----------------------------------------------------------------------
604 * BR0,BR1 - Base Register
605 * Ref: Section 10.3.1 on page 10-14
606 * OR0,OR1 - Option Register
607 * Ref: Section 10.3.2 on page 10-18
608 *-----------------------------------------------------------------------
609 */
610
611/* Bank 0,1 - FLASH SIMM
612 *
613 * This expects the FLASH SIMM to be connected to *CS0
614 * It consists of 4 AM29F080B parts.
615 *
616 * Note: For the 4 MB SIMM, *CS1 is unused.
617 */
618
619/* BR0 is configured as follows:
620 *
621 * - Base address of 0xFE000000
622 * - 32 bit port size
623 * - Data errors checking is disabled
624 * - Read and write access
625 * - GPCM 60x bus
626 * - Access are handled by the memory controller according to MSEL
627 * - Not used for atomic operations
628 * - No data pipelining is done
629 * - Valid
630 */
631#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
632 BRx_PS_32 |\
633 BRx_MS_GPCM_P |\
634 BRx_V)
635
636/* OR0 is configured as follows:
637 *
638 * - 32 MB
639 * - *BCTL0 is asserted upon access to the current memory bank
640 * - *CW / *WE are negated a quarter of a clock earlier
641 * - *CS is output at the same time as the address lines
642 * - Uses a clock cycle length of 5
643 * - *PSDVAL is generated internally by the memory controller
644 * unless *GTA is asserted earlier externally.
645 * - Relaxed timing is generated by the GPCM for accesses
646 * initiated to this memory region.
647 * - One idle clock is inserted between a read access from the
648 * current bank and the next access.
649 */
650#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
651 ORxG_CSNT |\
652 ORxG_ACS_DIV1 |\
653 ORxG_SCY_5_CLK |\
654 ORxG_TRLX |\
655 ORxG_EHTR)
656
657/*-----------------------------------------------------------------------
658 * BR2,BR3 - Base Register
659 * Ref: Section 10.3.1 on page 10-14
660 * OR2,OR3 - Option Register
661 * Ref: Section 10.3.2 on page 10-16
662 *-----------------------------------------------------------------------
663 */
664
665/*
666 * Bank 2,3 - 128 MB SDRAM DIMM
667 */
668
669/* With a 128 MB DIMM, the BR2 is configured as follows:
670 *
671 * - Base address of 0x00000000/0x08000000
672 * - 64 bit port size (60x bus only)
673 * - Data errors checking is disabled
674 * - Read and write access
675 * - SDRAM 60x bus
676 * - Access are handled by the memory controller according to MSEL
677 * - Not used for atomic operations
678 * - No data pipelining is done
679 * - Valid
680 */
681#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
682 BRx_PS_64 |\
683 BRx_MS_SDRAM_P |\
684 BRx_V)
685
686#define CFG_BR3_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
687 BRx_PS_64 |\
688 BRx_MS_SDRAM_P |\
689 BRx_V)
690
691/* With a 128 MB DIMM, the OR2 is configured as follows:
692 *
693 * - 128 MB
694 * - 4 internal banks per device
695 * - Row start address bit is A8 with PSDMR[PBI] = 0
696 * - 13 row address lines
697 * - Back-to-back page mode
698 * - Internal bank interleaving within save device enabled
699 */
700
701#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
702 ORxS_BPD_4 |\
703 ORxS_ROWST_PBI0_A7 |\
704 ORxS_NUMR_13)
705
706#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
707 ORxS_BPD_4 |\
708 ORxS_ROWST_PBI0_A7 |\
709 ORxS_NUMR_13)
710
711
712/*-----------------------------------------------------------------------
713 * PSDMR - 60x Bus SDRAM Mode Register
714 * Ref: Section 10.3.3 on page 10-21
715 *-----------------------------------------------------------------------
716 */
717
718/* With a 128 MB DIMM, the PSDMR is configured as follows:
719 *
720 * - Page Based Interleaving,
721 * - Refresh Enable,
722 * - Normal Operation
723 * - Address Multiplexing where A5 is output on A14 pin
724 * (A6 on A15, and so on),
725 * - use address pins A13-A15 as bank select,
726 * - A9 is output on SDA10 during an ACTIVATE command,
727 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
728 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
729 * is 3 clocks,
730 * - earliest timing for READ/WRITE command after ACTIVATE command is
731 * 2 clocks,
732 * - earliest timing for PRECHARGE after last data was read is 1 clock,
733 * - earliest timing for PRECHARGE after last data was written is 1 clock,
734 * - External Address Multiplexing enabled
735 * - CAS Latency is 2.
736 */
737#define CFG_PSDMR (PSDMR_RFEN |\
738 PSDMR_SDAM_A14_IS_A5 |\
739 PSDMR_BSMA_A13_A15 |\
740 PSDMR_SDA10_PBI0_A9 |\
741 PSDMR_RFRC_7_CLK |\
742 PSDMR_PRETOACT_3W |\
743 PSDMR_ACTTORW_2W |\
744 PSDMR_LDOTOPRE_1C |\
745 PSDMR_WRC_1C |\
746 PSDMR_EAMUX |\
747 PSDMR_CL_2)
748
749
750#define CFG_PSRT 0x0e
751#define CFG_MPTPR MPTPR_PTP_DIV32
752
753
754/*-----------------------------------------------------------------------
755 * BR4 - Base Register
756 * Ref: Section 10.3.1 on page 10-14
757 * OR4 - Option Register
758 * Ref: Section 10.3.2 on page 10-16
759 *-----------------------------------------------------------------------
760 */
761
762/*
763 * Bank 4 - On board SDRAM
764 *
765 */
766/* With 16 MB of onboard SDRAM BR4 is configured as follows
767 *
768 * - Base address 0x38000000
769 * - 32 bit port size
770 * - Data error checking disabled
771 * - Read/Write access
772 * - SDRAM local bus
773 * - Not used for atomic operations
774 * - No data pipelining is done
775 * - Valid
776 *
777 */
778
779#define CFG_BR4_PRELIM ((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
780 BRx_PS_32 |\
781 BRx_DECC_NONE |\
782 BRx_MS_SDRAM_L |\
783 BRx_V)
784
785/*
786 * With 16MB SDRAM, OR4 is configured as follows
787 * - 4 internal banks per device
788 * - Row start address bit is A10 with LSDMR[PBI] = 0
789 * - 12 row address lines
790 * - Back-to-back page mode
791 * - Internal bank interleaving within save device enabled
792 */
793
794#define CFG_OR4_PRELIM (MEG_TO_AM(CFG_SDRAM2_SIZE) |\
795 ORxS_BPD_4 |\
796 ORxS_ROWST_PBI0_A10 |\
797 ORxS_NUMR_12)
798
799
800/*-----------------------------------------------------------------------
801 * LSDMR - Local Bus SDRAM Mode Register
802 * Ref: Section 10.3.4 on page 10-24
803 *-----------------------------------------------------------------------
804 */
805
806/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
807 *
808 * - Page Based Interleaving,
809 * - Refresh Enable,
810 * - Normal Operation
811 * - Address Multiplexing where A5 is output on A13 pin
812 * (A6 on A15, and so on),
813 * - use address pins A15-A17 as bank select,
814 * - A11 is output on SDA10 during an ACTIVATE command,
815 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
816 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
817 * is 2 clocks,
818 * - earliest timing for READ/WRITE command after ACTIVATE command is
819 * 2 clocks,
820 * - SDRAM burst length is 8
821 * - earliest timing for PRECHARGE after last data was read is 1 clock,
822 * - earliest timing for PRECHARGE after last data was written is 1 clock,
823 * - External Address Multiplexing disabled
824 * - CAS Latency is 2.
825 */
826#define CFG_LSDMR (PSDMR_RFEN |\
827 PSDMR_SDAM_A13_IS_A5 |\
828 PSDMR_BSMA_A15_A17 |\
829 PSDMR_SDA10_PBI0_A11 |\
830 PSDMR_RFRC_7_CLK |\
831 PSDMR_PRETOACT_2W |\
832 PSDMR_ACTTORW_2W |\
833 PSDMR_BL |\
834 PSDMR_LDOTOPRE_1C |\
835 PSDMR_WRC_1C |\
836 PSDMR_CL_2)
837
838#define CFG_LSRT 0x0e
839
840/*-----------------------------------------------------------------------
841 * BR5 - Base Register
842 * Ref: Section 10.3.1 on page 10-14
843 * OR5 - Option Register
844 * Ref: Section 10.3.2 on page 10-16
845 *-----------------------------------------------------------------------
846 */
847
848/*
849 * Bank 5 EEProm and Mailbox
850 *
851 * The EEPROM and mailbox live on the same chip select.
852 * the eeprom is selected if the MSb of the address is set and the mailbox is
853 * selected if the MSb of the address is clear.
854 *
855 */
856
857/* BR5 is configured as follows:
858 *
859 * - Base address of 0x32000000/0xF2000000
860 * - 8 bit
861 * - Data error checking disabled
862 * - Read/Write access
863 * - GPCM 60x Bus
864 * - SDRAM local bus
865 * - No data pipelining is done
866 * - Valid
867 */
868
869#define CFG_BR5_PRELIM ((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
870 BRx_PS_8 |\
871 BRx_DECC_NONE |\
872 BRx_MS_GPCM_P |\
873 BRx_V)
874/* OR5 is configured as follows
875 * - buffer control enabled
876 * - chip select negated normally
877 * - CS output 1/2 clock after address
878 * - 15 wait states
879 * - *PSDVAL is generated internally by the memory controller
880 * unless *GTA is asserted earlier externally.
881 * - Relaxed timing is generated by the GPCM for accesses
882 * initiated to this memory region.
883 * - One idle clock is inserted between a read access from the
884 * current bank and the next access.
885 */
886
887#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
888 ORxG_ACS_DIV2 |\
889 ORxG_SCY_15_CLK |\
890 ORxG_TRLX |\
891 ORxG_EHTR)
892
893/*-----------------------------------------------------------------------
894 * BR6 - Base Register
895 * Ref: Section 10.3.1 on page 10-14
896 * OR6 - Option Register
897 * Ref: Section 10.3.2 on page 10-18
898 *-----------------------------------------------------------------------
899 */
900
901/* Bank 6 - I/O select
902 *
903 */
904
905/* BR6 is configured as follows:
906 *
907 * - Base address of 0xE0000000
908 * - 16 bit port size
909 * - Data errors checking is disabled
910 * - Read and write access
911 * - GPCM 60x bus
912 * - Access are handled by the memory controller according to MSEL
913 * - Not used for atomic operations
914 * - No data pipelining is done
915 * - Valid
916 */
917#define CFG_BR6_PRELIM ((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
918 BRx_PS_16 |\
919 BRx_MS_GPCM_P |\
920 BRx_V)
921
922/* OR6 is configured as follows
923 * - buffer control enabled
924 * - chip select negated normally
925 * - CS output 1/2 clock after address
926 * - 15 wait states
927 * - *PSDVAL is generated internally by the memory controller
928 * unless *GTA is asserted earlier externally.
929 * - Relaxed timing is generated by the GPCM for accesses
930 * initiated to this memory region.
931 * - One idle clock is inserted between a read access from the
932 * current bank and the next access.
933 */
934
935#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
936 ORxG_ACS_DIV2 |\
937 ORxG_SCY_15_CLK |\
938 ORxG_TRLX |\
939 ORxG_EHTR)
940
941
942/*-----------------------------------------------------------------------
943 * BR7 - Base Register
944 * Ref: Section 10.3.1 on page 10-14
945 * OR7 - Option Register
946 * Ref: Section 10.3.2 on page 10-18
947 *-----------------------------------------------------------------------
948 */
949
950/* Bank 7 - LEDs and switches
951 *
952 * LEDs are at 0x00001 (write only)
953 * switches are at 0x00001 (read only)
954 */
955#ifdef CFG_LED_BASE
956
957/* BR7 is configured as follows:
958 *
959 * - Base address of 0xA0000000
960 * - 8 bit port size
961 * - Data errors checking is disabled
962 * - Read and write access
963 * - GPCM 60x bus
964 * - Access are handled by the memory controller according to MSEL
965 * - Not used for atomic operations
966 * - No data pipelining is done
967 * - Valid
968 */
969#define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
970 BRx_PS_8 |\
971 BRx_DECC_NONE |\
972 BRx_MS_GPCM_P |\
973 BRx_V)
974
975/* OR7 is configured as follows:
976 *
977 * - 1 byte
978 * - *BCTL0 is asserted upon access to the current memory bank
979 * - *CW / *WE are negated a quarter of a clock earlier
980 * - *CS is output at the same time as the address lines
981 * - Uses a clock cycle length of 15
982 * - *PSDVAL is generated internally by the memory controller
983 * unless *GTA is asserted earlier externally.
984 * - Relaxed timing is generated by the GPCM for accesses
985 * initiated to this memory region.
986 * - One idle clock is inserted between a read access from the
987 * current bank and the next access.
988 */
989#define CFG_OR7_PRELIM (ORxG_AM_MSK |\
990 ORxG_CSNT |\
991 ORxG_ACS_DIV1 |\
992 ORxG_SCY_15_CLK |\
993 ORxG_TRLX |\
994 ORxG_EHTR)
995#endif /* CFG_LED_BASE */
996
997/*
998 * Internal Definitions
999 *
1000 * Boot Flags
1001 */
1002#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1003#define BOOTFLAG_WARM 0x02 /* Software reboot */
1004
1005#endif /* __CONFIG_H */