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wdenkf4675562002-10-02 14:20:15 +00001/*
wdenkf12e5682003-07-07 20:07:54 +00002 * (C) Copyright 2000-2003
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
38
39#ifdef CONFIG_LCD /* with LCD controller ? */
wdenk27b207f2003-07-24 23:38:38 +000040#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenkf4675562002-10-02 14:20:15 +000041#endif
42
43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44#undef CONFIG_8xx_CONS_SMC2
45#undef CONFIG_8xx_CONS_NONE
46#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
47#if 0
48#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
49#else
50#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
51#endif
52
53#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
54
55#define CONFIG_BOARD_TYPES 1 /* support board types */
56
57#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
58
59#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000060
61#define CONFIG_EXTRA_ENV_SETTINGS \
62 "nfsargs=setenv bootargs root=/dev/nfs rw " \
63 "nfsroot=$(serverip):$(rootpath)\0" \
64 "ramargs=setenv bootargs root=/dev/ram rw\0" \
65 "addip=setenv bootargs $(bootargs) " \
66 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
67 ":$(hostname):$(netdev):off panic=1\0" \
68 "flash_nfs=run nfsargs addip;" \
69 "bootm $(kernel_addr)\0" \
70 "flash_self=run ramargs addip;" \
71 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
72 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
73 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenk3bac3512003-03-12 10:41:04 +000074 "bootfile=/tftpboot/TQM860L/uImage\0" \
wdenk6aff3112002-12-17 01:51:00 +000075 "kernel_addr=40040000\0" \
76 "ramdisk_addr=40100000\0" \
77 ""
78#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000079
80#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
81#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
82
83#undef CONFIG_WATCHDOG /* watchdog disabled */
84
85#ifdef CONFIG_LCD
86# undef CONFIG_STATUS_LED /* disturbs display */
87#else
88# define CONFIG_STATUS_LED 1 /* Status LED enabled */
89#endif /* CONFIG_LCD */
90
91#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
92
93#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
94
95#define CONFIG_MAC_PARTITION
96#define CONFIG_DOS_PARTITION
97
98#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
99
wdenk27b207f2003-07-24 23:38:38 +0000100#ifdef CONFIG_SPLASH_SCREEN
101# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk6aff3112002-12-17 01:51:00 +0000102 CFG_CMD_ASKENV | \
wdenk27b207f2003-07-24 23:38:38 +0000103 CFG_CMD_BMP | \
104 CFG_CMD_DATE | \
wdenkf4675562002-10-02 14:20:15 +0000105 CFG_CMD_DHCP | \
wdenk27b207f2003-07-24 23:38:38 +0000106 CFG_CMD_IDE )
107#else
108# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
109 CFG_CMD_ASKENV | \
110 CFG_CMD_DATE | \
111 CFG_CMD_DHCP | \
112 CFG_CMD_IDE )
113#endif
wdenkf4675562002-10-02 14:20:15 +0000114
115/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
116#include <cmd_confdefs.h>
117
118/*
119 * Miscellaneous configurable options
120 */
121#define CFG_LONGHELP /* undef to save memory */
wdenk6aff3112002-12-17 01:51:00 +0000122#define CFG_PROMPT "=> " /* Monitor Command Prompt */
123
124#if 0
125#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
126#endif
127#ifdef CFG_HUSH_PARSER
128#define CFG_PROMPT_HUSH_PS2 "> "
129#endif
130
wdenkf4675562002-10-02 14:20:15 +0000131#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk6aff3112002-12-17 01:51:00 +0000132#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000133#else
wdenk6aff3112002-12-17 01:51:00 +0000134#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000135#endif
136#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenk6aff3112002-12-17 01:51:00 +0000137#define CFG_MAXARGS 16 /* max number of command args */
wdenkf4675562002-10-02 14:20:15 +0000138#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
139
140#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
141#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
142
143#define CFG_LOAD_ADDR 0x100000 /* default load address */
144
wdenk6aff3112002-12-17 01:51:00 +0000145#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf4675562002-10-02 14:20:15 +0000146
147#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
148
149/*
150 * Low Level Configuration Settings
151 * (address mappings, register initial values, etc.)
152 * You should know what you are doing if you make changes here.
153 */
154/*-----------------------------------------------------------------------
155 * Internal Memory Mapped Register
156 */
157#define CFG_IMMR 0xFFF00000
158
159/*-----------------------------------------------------------------------
160 * Definitions for initial stack pointer and data area (in DPRAM)
161 */
162#define CFG_INIT_RAM_ADDR CFG_IMMR
163#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
164#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
165#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
166#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
167
168/*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
171 * Please note that CFG_SDRAM_BASE _must_ start at 0
172 */
173#define CFG_SDRAM_BASE 0x00000000
174#define CFG_FLASH_BASE 0x40000000
175#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
176#define CFG_MONITOR_BASE CFG_FLASH_BASE
177#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
178
179/*
180 * For booting Linux, the board info and command line data
181 * have to be in the first 8 MB of memory, since this is
182 * the maximum mapped by the Linux kernel during initialization.
183 */
184#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
185
186/*-----------------------------------------------------------------------
187 * FLASH organization
188 */
189#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenkaacf9a42003-01-17 16:27:01 +0000190#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000191
192#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
193#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
194
195#define CFG_ENV_IS_IN_FLASH 1
196#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
197#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
198
199/* Address and size of Redundant Environment Sector */
200#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
201#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
202
203/*-----------------------------------------------------------------------
204 * Hardware Information Block
205 */
206#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
207#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
208#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
209
210/*-----------------------------------------------------------------------
211 * Cache Configuration
212 */
213#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
214#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
215#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
216#endif
217
218/*-----------------------------------------------------------------------
219 * SYPCR - System Protection Control 11-9
220 * SYPCR can only be written once after reset!
221 *-----------------------------------------------------------------------
222 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
223 */
224#if defined(CONFIG_WATCHDOG)
225#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
226 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
227#else
228#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
229#endif
230
231/*-----------------------------------------------------------------------
232 * SIUMCR - SIU Module Configuration 11-6
233 *-----------------------------------------------------------------------
234 * PCMCIA config., multi-function pin tri-state
235 */
236#ifndef CONFIG_CAN_DRIVER
237#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
238#else /* we must activate GPL5 in the SIUMCR for CAN */
239#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
240#endif /* CONFIG_CAN_DRIVER */
241
242/*-----------------------------------------------------------------------
243 * TBSCR - Time Base Status and Control 11-26
244 *-----------------------------------------------------------------------
245 * Clear Reference Interrupt Status, Timebase freezing enabled
246 */
247#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
248
249/*-----------------------------------------------------------------------
250 * RTCSC - Real-Time Clock Status and Control Register 11-27
251 *-----------------------------------------------------------------------
252 */
253#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
254
255/*-----------------------------------------------------------------------
256 * PISCR - Periodic Interrupt Status and Control 11-31
257 *-----------------------------------------------------------------------
258 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
259 */
260#define CFG_PISCR (PISCR_PS | PISCR_PITF)
261
262/*-----------------------------------------------------------------------
263 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
264 *-----------------------------------------------------------------------
265 * Reset PLL lock status sticky bit, timer expired status bit and timer
266 * interrupt status bit
267 *
268 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
269 */
270#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
271#define CFG_PLPRCR \
272 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
wdenkf12e5682003-07-07 20:07:54 +0000273#else /* up to 66 MHz we use a 1:1 clock */
wdenkf4675562002-10-02 14:20:15 +0000274#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
275#endif /* CONFIG_80MHz */
276
277/*-----------------------------------------------------------------------
278 * SCCR - System Clock and reset Control Register 15-27
279 *-----------------------------------------------------------------------
280 * Set clock output, timebase and RTC source and divider,
281 * power management and some other internal clocks
282 */
283#define SCCR_MASK SCCR_EBDF11
284#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
285#define CFG_SCCR (/* SCCR_TBS | */ \
286 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
287 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
288 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000289#else /* up to 66 MHz we use a 1:1 clock */
wdenkf4675562002-10-02 14:20:15 +0000290#define CFG_SCCR (SCCR_TBS | \
291 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
292 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
293 SCCR_DFALCD00)
294#endif /* CONFIG_80MHz */
295
296/*-----------------------------------------------------------------------
297 * PCMCIA stuff
298 *-----------------------------------------------------------------------
299 *
300 */
301#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
302#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
303#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
304#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
305#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
306#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
307#define CFG_PCMCIA_IO_ADDR (0xEC000000)
308#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
309
310/*-----------------------------------------------------------------------
311 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
312 *-----------------------------------------------------------------------
313 */
314
315#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
316
317#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
318#undef CONFIG_IDE_LED /* LED for ide not supported */
319#undef CONFIG_IDE_RESET /* reset for ide not supported */
320
321#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
322#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
323
324#define CFG_ATA_IDE0_OFFSET 0x0000
325
326#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
327
328/* Offset for data I/O */
329#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
330
331/* Offset for normal register accesses */
332#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
333
334/* Offset for alternate registers */
335#define CFG_ATA_ALT_OFFSET 0x0100
336
337/*-----------------------------------------------------------------------
338 *
339 *-----------------------------------------------------------------------
340 *
341 */
wdenkf4675562002-10-02 14:20:15 +0000342#define CFG_DER 0
343
344/*
345 * Init Memory Controller:
346 *
347 * BR0/1 and OR0/1 (FLASH)
348 */
349
350#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
351#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
352
353/* used to re-map FLASH both when starting from SRAM or FLASH:
354 * restrict access enough to keep SRAM working (if any)
355 * but not too much to meddle with FLASH accesses
356 */
357#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
358#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
359
360/*
361 * FLASH timing:
362 */
363#if defined(CONFIG_80MHz)
364/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
365#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
366 OR_SCY_3_CLK | OR_EHTR | OR_BI)
367#elif defined(CONFIG_66MHz)
368/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
369#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
370 OR_SCY_3_CLK | OR_EHTR | OR_BI)
371#else /* 50 MHz */
372/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
373#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
374 OR_SCY_2_CLK | OR_EHTR | OR_BI)
375#endif /*CONFIG_??MHz */
376
377#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
378#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
379#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
380
381#define CFG_OR1_REMAP CFG_OR0_REMAP
382#define CFG_OR1_PRELIM CFG_OR0_PRELIM
383#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
384
385/*
386 * BR2/3 and OR2/3 (SDRAM)
387 *
388 */
389#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
390#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
391#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
392
393/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
394#define CFG_OR_TIMING_SDRAM 0x00000A00
395
396#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
397#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
398
399#ifndef CONFIG_CAN_DRIVER
400#define CFG_OR3_PRELIM CFG_OR2_PRELIM
401#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
402#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
403#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
404#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
405#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
406#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
407 BR_PS_8 | BR_MS_UPMB | BR_V )
408#endif /* CONFIG_CAN_DRIVER */
409
410/*
411 * Memory Periodic Timer Prescaler
412 *
413 * The Divider for PTA (refresh timer) configuration is based on an
414 * example SDRAM configuration (64 MBit, one bank). The adjustment to
415 * the number of chip selects (NCS) and the actually needed refresh
416 * rate is done by setting MPTPR.
417 *
418 * PTA is calculated from
419 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
420 *
421 * gclk CPU clock (not bus clock!)
422 * Trefresh Refresh cycle * 4 (four word bursts used)
423 *
424 * 4096 Rows from SDRAM example configuration
425 * 1000 factor s -> ms
426 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
427 * 4 Number of refresh cycles per period
428 * 64 Refresh cycle in ms per number of rows
429 * --------------------------------------------
430 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
431 *
432 * 50 MHz => 50.000.000 / Divider = 98
433 * 66 Mhz => 66.000.000 / Divider = 129
434 * 80 Mhz => 80.000.000 / Divider = 156
435 */
436#if defined(CONFIG_80MHz)
437#define CFG_MAMR_PTA 156
438#elif defined(CONFIG_66MHz)
439#define CFG_MAMR_PTA 129
440#else /* 50 MHz */
441#define CFG_MAMR_PTA 98
442#endif /*CONFIG_??MHz */
443
444/*
445 * For 16 MBit, refresh rates could be 31.3 us
446 * (= 64 ms / 2K = 125 / quad bursts).
447 * For a simpler initialization, 15.6 us is used instead.
448 *
449 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
450 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
451 */
452#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
453#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
454
455/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
456#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
457#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
458
459/*
460 * MAMR settings for SDRAM
461 */
462
463/* 8 column SDRAM */
464#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
465 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
467/* 9 column SDRAM */
468#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
469 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
471
472
473/*
474 * Internal Definitions
475 *
476 * Boot Flags
477 */
478#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
479#define BOOTFLAG_WARM 0x02 /* Software reboot */
480
481#endif /* __CONFIG_H */