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wdenk42d1f032003-10-15 23:53:47 +00001/*
Dipen Dudhatbeba93e2011-01-19 12:46:27 +05302 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
Kumar Gala39aaca12009-03-19 02:46:19 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000011 */
12
13#include <common.h>
14#include <ppc_asm.tmpl>
Haiying Wanga52d2f82011-02-11 01:25:30 -060015#include <linux/compiler.h>
wdenk42d1f032003-10-15 23:53:47 +000016#include <asm/processor.h>
Trent Piephoada591d2008-12-03 15:16:37 -080017#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000018
Wolfgang Denkd87080b2006-03-31 18:32:53 +020019DECLARE_GLOBAL_DATA_PTR;
20
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053021
22#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24#endif
wdenk42d1f032003-10-15 23:53:47 +000025/* --------------------------------------------------------------- */
26
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053027void get_sys_info(sys_info_t *sys_info)
wdenk42d1f032003-10-15 23:53:47 +000028{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala800c73c2012-10-08 07:44:06 +000030#ifdef CONFIG_FSL_IFC
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -070031 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
Kumar Gala800c73c2012-10-08 07:44:06 +000032 u32 ccr;
33#endif
Kumar Gala39aaca12009-03-19 02:46:19 -050034#ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
Timur Tabifbb9ecf2011-08-05 16:15:24 -050036 unsigned int cpu;
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +053037#ifdef CONFIG_HETROGENOUS_CLUSTERS
38 unsigned int dsp_cpu;
39 uint rcw_tmp1, rcw_tmp2;
40#endif
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053041#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
42 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
43#endif
York Sun14109c72014-10-27 11:31:33 -070044 __maybe_unused u32 svr;
Kumar Gala39aaca12009-03-19 02:46:19 -050045
46 const u8 core_cplx_PLL[16] = {
47 [ 0] = 0, /* CC1 PPL / 1 */
48 [ 1] = 0, /* CC1 PPL / 2 */
49 [ 2] = 0, /* CC1 PPL / 4 */
50 [ 4] = 1, /* CC2 PPL / 1 */
51 [ 5] = 1, /* CC2 PPL / 2 */
52 [ 6] = 1, /* CC2 PPL / 4 */
53 [ 8] = 2, /* CC3 PPL / 1 */
54 [ 9] = 2, /* CC3 PPL / 2 */
55 [10] = 2, /* CC3 PPL / 4 */
56 [12] = 3, /* CC4 PPL / 1 */
57 [13] = 3, /* CC4 PPL / 2 */
58 [14] = 3, /* CC4 PPL / 4 */
59 };
60
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053061 const u8 core_cplx_pll_div[16] = {
Kumar Gala39aaca12009-03-19 02:46:19 -050062 [ 0] = 1, /* CC1 PPL / 1 */
63 [ 1] = 2, /* CC1 PPL / 2 */
64 [ 2] = 4, /* CC1 PPL / 4 */
65 [ 4] = 1, /* CC2 PPL / 1 */
66 [ 5] = 2, /* CC2 PPL / 2 */
67 [ 6] = 4, /* CC2 PPL / 4 */
68 [ 8] = 1, /* CC3 PPL / 1 */
69 [ 9] = 2, /* CC3 PPL / 2 */
70 [10] = 4, /* CC3 PPL / 4 */
71 [12] = 1, /* CC4 PPL / 1 */
72 [13] = 2, /* CC4 PPL / 2 */
73 [14] = 4, /* CC4 PPL / 4 */
74 };
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053075 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
76#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
77 uint rcw_tmp;
78#endif
79 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
Kumar Gala39aaca12009-03-19 02:46:19 -050080 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080081 uint mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -050082
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053083 sys_info->freq_systembus = sysclk;
Priyanka Jainb1359912013-12-17 14:25:52 +053084#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
vijay rai0c12a152014-04-15 11:34:12 +053085 uint ddr_refclk_sel;
86 unsigned int porsr1_sys_clk;
87 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
88 & FSL_DCFG_PORSR1_SYSCLK_MASK;
89 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
90 sys_info->diff_sysclk = 1;
91 else
92 sys_info->diff_sysclk = 0;
93
Priyanka Jainb1359912013-12-17 14:25:52 +053094 /*
95 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
96 * are driven by separate DDR Refclock or single source
97 * differential clock.
98 */
vijay rai0c12a152014-04-15 11:34:12 +053099 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
Priyanka Jainb1359912013-12-17 14:25:52 +0530100 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
101 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
102 /*
vijay rai0c12a152014-04-15 11:34:12 +0530103 * For single source clocking, both ddrclock and sysclock
Priyanka Jainb1359912013-12-17 14:25:52 +0530104 * are driven by differential sysclock.
105 */
vijay rai0c12a152014-04-15 11:34:12 +0530106 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
Priyanka Jainb1359912013-12-17 14:25:52 +0530107 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
vijay rai0c12a152014-04-15 11:34:12 +0530108 else
Priyanka Jainb1359912013-12-17 14:25:52 +0530109#endif
York Sun98ffa192012-10-08 07:44:31 +0000110#ifdef CONFIG_DDR_CLK_FREQ
Priyanka Jainb1359912013-12-17 14:25:52 +0530111 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
York Sun98ffa192012-10-08 07:44:31 +0000112#else
Priyanka Jainb1359912013-12-17 14:25:52 +0530113 sys_info->freq_ddrbus = sysclk;
York Sun98ffa192012-10-08 07:44:31 +0000114#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500115
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530116 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
York Sunf77329c2012-10-08 07:44:09 +0000117 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
118 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
119 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
York Sunc3678b02014-03-28 15:07:27 -0700120#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
121 if (mem_pll_rat == 0) {
122 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
123 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
124 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
125 }
126#endif
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800127 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
128 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
129 * it uses 6.
York Sun14109c72014-10-27 11:31:33 -0700130 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800131 */
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800132#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
York Sun14109c72014-10-27 11:31:33 -0700133 defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
134 svr = get_svr();
135 switch (SVR_SOC_VER(svr)) {
136 case SVR_T4240:
137 case SVR_T4160:
138 case SVR_T4120:
139 case SVR_T4080:
140 if (SVR_MAJ(svr) >= 2)
141 mem_pll_rat *= 2;
142 break;
143 case SVR_T2080:
144 case SVR_T2081:
145 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
146 mem_pll_rat *= 2;
147 break;
148 default:
149 break;
150 }
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800151#endif
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800152 if (mem_pll_rat > 2)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530153 sys_info->freq_ddrbus *= mem_pll_rat;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800154 else
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530155 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -0500156
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530157 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
158 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800159 if (ratio[i] > 4)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530160 freq_c_pll[i] = sysclk * ratio[i];
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800161 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530162 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800163 }
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530164
York Sun9a653a92012-10-08 07:44:11 +0000165#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
166 /*
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530167 * As per CHASSIS2 architeture total 12 clusters are posible and
York Sun9a653a92012-10-08 07:44:11 +0000168 * Each cluster has up to 4 cores, sharing the same PLL selection.
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530169 * The cluster clock assignment is SoC defined.
170 *
171 * Total 4 clock groups are possible with 3 PLLs each.
172 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
173 * clock group B has 3, 4, 6 and so on.
174 *
175 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
176 * depends upon the SoC architeture. Same applies to other
177 * clock groups and clusters.
178 *
York Sun9a653a92012-10-08 07:44:11 +0000179 */
180 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunf6981432013-03-25 07:40:07 +0000181 int cluster = fsl_qoriq_core_to_cluster(cpu);
182 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
York Sun9a653a92012-10-08 07:44:11 +0000183 & 0xf;
184 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530185 cplx_pll += cc_group[cluster] - 1;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530186 sys_info->freq_processor[cpu] =
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530187 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
York Sun9a653a92012-10-08 07:44:11 +0000188 }
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530189
190#ifdef CONFIG_HETROGENOUS_CLUSTERS
191 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
192 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
193 u32 c_pll_sel = (in_be32
194 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
195 & 0xf;
196 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
197 cplx_pll += cc_group[dsp_cluster] - 1;
198 sys_info->freq_processor_dsp[dsp_cpu] =
199 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
200 }
201#endif
202
Prabhakar Kushwahab33bd8c2014-04-21 10:47:41 +0530203#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
204 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
Sandeep Singh0cb33252013-03-25 07:33:09 +0000205#define FM1_CLK_SEL 0xe0000000
206#define FM1_CLK_SHIFT 29
Shengzhou Liuf6050792014-11-24 17:11:54 +0800207#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
208#define FM1_CLK_SEL 0x00000007
209#define FM1_CLK_SHIFT 0
Sandeep Singh0cb33252013-03-25 07:33:09 +0000210#else
York Sun9a653a92012-10-08 07:44:11 +0000211#define PME_CLK_SEL 0xe0000000
212#define PME_CLK_SHIFT 29
213#define FM1_CLK_SEL 0x1c000000
214#define FM1_CLK_SHIFT 26
Sandeep Singh0cb33252013-03-25 07:33:09 +0000215#endif
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530216#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
Shengzhou Liuf6050792014-11-24 17:11:54 +0800217#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
218 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
219#else
York Sun9a653a92012-10-08 07:44:11 +0000220 rcw_tmp = in_be32(&gur->rcwsr[7]);
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530221#endif
Shengzhou Liuf6050792014-11-24 17:11:54 +0800222#endif
York Sun9a653a92012-10-08 07:44:11 +0000223
224#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530225#ifndef CONFIG_PME_PLAT_CLK_DIV
York Sun9a653a92012-10-08 07:44:11 +0000226 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
227 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530228 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
York Sun9a653a92012-10-08 07:44:11 +0000229 break;
230 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530231 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000232 break;
233 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530234 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000235 break;
236 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530237 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000238 break;
239 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530240 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000241 break;
242 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530243 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000244 break;
245 default:
246 printf("Error: Unknown PME clock select!\n");
247 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530248 sys_info->freq_pme = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000249 break;
250
251 }
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530252#else
253 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
254
255#endif
York Sun9a653a92012-10-08 07:44:11 +0000256#endif
257
Haiying Wang990e1a82012-10-11 07:13:39 +0000258#ifdef CONFIG_SYS_DPAA_QBMAN
Shengzhou Liuf6050792014-11-24 17:11:54 +0800259#ifndef CONFIG_QBMAN_CLK_DIV
260#define CONFIG_QBMAN_CLK_DIV 2
261#endif
262 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
Haiying Wang990e1a82012-10-11 07:13:39 +0000263#endif
264
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530265#if defined(CONFIG_SYS_MAPLE)
266#define CPRI_CLK_SEL 0x1C000000
267#define CPRI_CLK_SHIFT 26
268#define CPRI_ALT_CLK_SEL 0x00007000
269#define CPRI_ALT_CLK_SHIFT 12
270
271 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
272 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
273 /* For MAPLE and CPRI frequency */
274 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
275 case 1:
276 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
277 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
278 break;
279 case 2:
280 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
281 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
282 break;
283 case 3:
284 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
285 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
286 break;
287 case 4:
288 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
289 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
290 break;
291 case 5:
292 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
293 >> CPRI_ALT_CLK_SHIFT) == 6) {
294 sys_info->freq_maple =
295 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
296 sys_info->freq_cpri =
297 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
298 }
299 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
300 >> CPRI_ALT_CLK_SHIFT) == 7) {
301 sys_info->freq_maple =
302 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
303 sys_info->freq_cpri =
304 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
305 }
306 break;
307 case 6:
308 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
309 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
310 break;
311 case 7:
312 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
313 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
314 break;
315 default:
316 printf("Error: Unknown MAPLE/CPRI clock select!\n");
317 }
318
319 /* For MAPLE ULB and eTVPE frequencies */
320#define ULB_CLK_SEL 0x00000038
321#define ULB_CLK_SHIFT 3
322#define ETVPE_CLK_SEL 0x00000007
323#define ETVPE_CLK_SHIFT 0
324
325 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
326 case 1:
327 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
328 break;
329 case 2:
330 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
331 break;
332 case 3:
333 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
334 break;
335 case 4:
336 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
337 break;
338 case 5:
339 sys_info->freq_maple_ulb = sys_info->freq_systembus;
340 break;
341 case 6:
342 sys_info->freq_maple_ulb =
343 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
344 break;
345 case 7:
346 sys_info->freq_maple_ulb =
347 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
348 break;
349 default:
350 printf("Error: Unknown MAPLE ULB clock select!\n");
351 }
352
353 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
354 case 1:
355 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
356 break;
357 case 2:
358 sys_info->freq_maple_etvpe =
359 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
360 break;
361 case 3:
362 sys_info->freq_maple_etvpe =
363 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
364 break;
365 case 4:
366 sys_info->freq_maple_etvpe =
367 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
368 break;
369 case 5:
370 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
371 break;
372 case 6:
373 sys_info->freq_maple_etvpe =
374 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
375 break;
376 case 7:
377 sys_info->freq_maple_etvpe =
378 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
379 break;
380 default:
381 printf("Error: Unknown MAPLE eTVPE clock select!\n");
382 }
383
384#endif
385
York Sun9a653a92012-10-08 07:44:11 +0000386#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530387#ifndef CONFIG_FM_PLAT_CLK_DIV
York Sun9a653a92012-10-08 07:44:11 +0000388 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
389 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530390 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
York Sun9a653a92012-10-08 07:44:11 +0000391 break;
392 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530393 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000394 break;
395 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530396 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000397 break;
398 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530399 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000400 break;
Sandeep Singh0cb33252013-03-25 07:33:09 +0000401 case 5:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530402 sys_info->freq_fman[0] = sys_info->freq_systembus;
Sandeep Singh0cb33252013-03-25 07:33:09 +0000403 break;
York Sun9a653a92012-10-08 07:44:11 +0000404 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530405 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000406 break;
407 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530408 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000409 break;
410 default:
411 printf("Error: Unknown FMan1 clock select!\n");
412 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530413 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000414 break;
415 }
416#if (CONFIG_SYS_NUM_FMAN) == 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530417#ifdef CONFIG_SYS_FM2_CLK
York Sun9a653a92012-10-08 07:44:11 +0000418#define FM2_CLK_SEL 0x00000038
419#define FM2_CLK_SHIFT 3
420 rcw_tmp = in_be32(&gur->rcwsr[15]);
421 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
422 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530423 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
York Sun9a653a92012-10-08 07:44:11 +0000424 break;
425 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530426 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000427 break;
428 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530429 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000430 break;
431 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530432 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000433 break;
Shaohui Xiec1015c62013-11-28 13:52:51 +0800434 case 5:
435 sys_info->freq_fman[1] = sys_info->freq_systembus;
436 break;
York Sun9a653a92012-10-08 07:44:11 +0000437 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530438 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000439 break;
440 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530441 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000442 break;
443 default:
444 printf("Error: Unknown FMan2 clock select!\n");
445 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530446 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000447 break;
448 }
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530449#endif
York Sun9a653a92012-10-08 07:44:11 +0000450#endif /* CONFIG_SYS_NUM_FMAN == 2 */
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530451#else
452 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
453#endif
454#endif
York Sun9a653a92012-10-08 07:44:11 +0000455
456#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
457
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500458 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunf6981432013-03-25 07:40:07 +0000459 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
460 & 0xf;
Kumar Gala39aaca12009-03-19 02:46:19 -0500461 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
462
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530463 sys_info->freq_processor[cpu] =
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530464 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
Kumar Gala39aaca12009-03-19 02:46:19 -0500465 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500466#define PME_CLK_SEL 0x80000000
467#define FM1_CLK_SEL 0x40000000
468#define FM2_CLK_SEL 0x20000000
Kumar Galab5c87532011-02-16 02:03:29 -0600469#define HWA_ASYNC_DIV 0x04000000
470#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
471#define HWA_CC_PLL 1
Timur Tabi49054432012-10-05 11:09:19 +0000472#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
473#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600474#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
Wolfgang Denkcd6881b2011-05-19 22:21:41 +0200475#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600476#else
477#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
478#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500479 rcw_tmp = in_be32(&gur->rcwsr[7]);
480
481#ifdef CONFIG_SYS_DPAA_PME
Kumar Galab5c87532011-02-16 02:03:29 -0600482 if (rcw_tmp & PME_CLK_SEL) {
483 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530484 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600485 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530486 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600487 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530488 sys_info->freq_pme = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600489 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500490#endif
491
492#ifdef CONFIG_SYS_DPAA_FMAN
Kumar Galab5c87532011-02-16 02:03:29 -0600493 if (rcw_tmp & FM1_CLK_SEL) {
494 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530495 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600496 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530497 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600498 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530499 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600500 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500501#if (CONFIG_SYS_NUM_FMAN) == 2
Kumar Galab5c87532011-02-16 02:03:29 -0600502 if (rcw_tmp & FM2_CLK_SEL) {
503 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530504 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600505 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530506 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600507 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530508 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600509 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500510#endif
511#endif
512
Shaohui Xie3e83fc92013-03-25 07:33:25 +0000513#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530514 sys_info->freq_qman = sys_info->freq_systembus / 2;
Shaohui Xie3e83fc92013-03-25 07:33:25 +0000515#endif
516
York Sun9a653a92012-10-08 07:44:11 +0000517#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
518
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800519#ifdef CONFIG_U_QE
520 sys_info->freq_qe = sys_info->freq_systembus / 2;
521#endif
522
York Sun9a653a92012-10-08 07:44:11 +0000523#else /* CONFIG_FSL_CORENET */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530524 uint plat_ratio, e500_ratio, half_freq_systembus;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500525 int i;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400526#ifdef CONFIG_QE
Haiying Wanga52d2f82011-02-11 01:25:30 -0600527 __maybe_unused u32 qe_ratio;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400528#endif
wdenk42d1f032003-10-15 23:53:47 +0000529
530 plat_ratio = (gur->porpllsr) & 0x0000003e;
531 plat_ratio >>= 1;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530532 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500533
534 /* Divide before multiply to avoid integer
535 * overflow for processor speeds above 2GHz */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530536 half_freq_systembus = sys_info->freq_systembus/2;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530537 for (i = 0; i < cpu_numcores(); i++) {
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500538 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530539 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500540 }
James Yanga3e77fa2008-02-08 18:05:08 -0600541
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530542 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
543 sys_info->freq_ddrbus = sys_info->freq_systembus;
Kumar Galad4357932007-12-07 04:59:26 -0600544
545#ifdef CONFIG_DDR_CLK_FREQ
546 {
Jason Jinc0391112008-09-27 14:40:57 +0800547 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
548 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Galad4357932007-12-07 04:59:26 -0600549 if (ddr_ratio != 0x7)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530550 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
Kumar Galad4357932007-12-07 04:59:26 -0600551 }
552#endif
Trent Piephoada591d2008-12-03 15:16:37 -0800553
Haiying Wangb3d7f202009-05-20 12:30:29 -0400554#ifdef CONFIG_QE
York Sunbe7bebe2012-08-10 11:07:26 +0000555#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530556 sys_info->freq_qe = sys_info->freq_systembus;
Haiying Wanga52d2f82011-02-11 01:25:30 -0600557#else
Haiying Wangb3d7f202009-05-20 12:30:29 -0400558 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
559 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530560 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400561#endif
Haiying Wanga52d2f82011-02-11 01:25:30 -0600562#endif
Haiying Wangb3d7f202009-05-20 12:30:29 -0400563
Haiying Wang24995d82011-01-20 22:26:31 +0000564#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530565 sys_info->freq_fman[0] = sys_info->freq_systembus;
Haiying Wang24995d82011-01-20 22:26:31 +0000566#endif
567
568#endif /* CONFIG_FSL_CORENET */
569
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530570#if defined(CONFIG_FSL_LBC)
York Sun9a653a92012-10-08 07:44:11 +0000571 uint lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800572#if defined(CONFIG_SYS_LBC_LCRR)
573 /* We will program LCRR to this value later */
574 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
575#else
Becky Brucef51cdaf2010-06-17 11:37:20 -0500576 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
Trent Piephoada591d2008-12-03 15:16:37 -0800577#endif
578 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
Dave Liu0fd2fa62009-11-17 20:49:05 +0800579#if defined(CONFIG_FSL_CORENET)
580 /* If this is corenet based SoC, bit-representation
581 * for four times the clock divider values.
582 */
583 lcrr_div *= 4;
584#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
Trent Piephoada591d2008-12-03 15:16:37 -0800585 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
586 /*
587 * Yes, the entire PQ38 family use the same
588 * bit-representation for twice the clock divider values.
589 */
590 lcrr_div *= 2;
591#endif
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530592 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800593 } else {
594 /* In case anyone cares what the unknown value is */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530595 sys_info->freq_localbus = lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800596 }
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530597#endif
Kumar Gala800c73c2012-10-08 07:44:06 +0000598
599#if defined(CONFIG_FSL_IFC)
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700600 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
Kumar Gala800c73c2012-10-08 07:44:06 +0000601 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
602
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530603 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
Kumar Gala800c73c2012-10-08 07:44:06 +0000604#endif
wdenk42d1f032003-10-15 23:53:47 +0000605}
606
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500607
wdenk42d1f032003-10-15 23:53:47 +0000608int get_clocks (void)
609{
wdenk42d1f032003-10-15 23:53:47 +0000610 sys_info_t sys_info;
Timur Tabi88353a92008-04-04 11:15:58 -0500611#ifdef CONFIG_MPC8544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
Timur Tabi88353a92008-04-04 11:15:58 -0500613#endif
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500614#if defined(CONFIG_CPM2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000616 uint sccr, dfbrg;
617
618 /* set VCO = 4 * BRG */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600619 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
620 sccr = cpm->im_cpm_intctl.sccr;
wdenk42d1f032003-10-15 23:53:47 +0000621 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
622#endif
623 get_sys_info (&sys_info);
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530624 gd->cpu_clk = sys_info.freq_processor[0];
625 gd->bus_clk = sys_info.freq_systembus;
626 gd->mem_clk = sys_info.freq_ddrbus;
627 gd->arch.lbc_clk = sys_info.freq_localbus;
Timur Tabi88353a92008-04-04 11:15:58 -0500628
Haiying Wangb3d7f202009-05-20 12:30:29 -0400629#ifdef CONFIG_QE
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530630 gd->arch.qe_clk = sys_info.freq_qe;
Simon Glass45bae2e2012-12-13 20:48:50 +0000631 gd->arch.brg_clk = gd->arch.qe_clk / 2;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400632#endif
Timur Tabi88353a92008-04-04 11:15:58 -0500633 /*
634 * The base clock for I2C depends on the actual SOC. Unfortunately,
635 * there is no pattern that can be used to determine the frequency, so
636 * the only choice is to look up the actual SOC number and use the value
637 * for that SOC. This information is taken from application note
638 * AN2919.
639 */
640#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
Tang Yuantianf62b1232013-09-06 10:45:40 +0800641 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
642 defined(CONFIG_P1022)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530643 gd->arch.i2c1_clk = sys_info.freq_systembus;
Timur Tabi88353a92008-04-04 11:15:58 -0500644#elif defined(CONFIG_MPC8544)
645 /*
646 * On the 8544, the I2C clock is the same as the SEC clock. This can be
647 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
648 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
649 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
650 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
651 */
652 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530653 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
Kumar Gala42653b82008-10-16 21:58:49 -0500654 else
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530655 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500656#else
657 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530658 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500659#endif
Simon Glass609e6ec2012-12-13 20:48:49 +0000660 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
Timur Tabi943afa22008-01-09 14:35:26 -0600661
Dipen Dudhat6b9ea082009-09-01 17:27:00 +0530662#if defined(CONFIG_FSL_ESDHC)
Priyanka Jain7d640e92011-02-08 15:45:25 +0530663#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
664 defined(CONFIG_P1014)
Simon Glasse9adeca2012-12-13 20:49:05 +0000665 gd->arch.sdhc_clk = gd->bus_clk;
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400666#else
Simon Glasse9adeca2012-12-13 20:49:05 +0000667 gd->arch.sdhc_clk = gd->bus_clk / 2;
Kumar Galaef50d6c2008-08-12 11:14:19 -0500668#endif
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400669#endif /* defined(CONFIG_FSL_ESDHC) */
Kumar Galaef50d6c2008-08-12 11:14:19 -0500670
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500671#if defined(CONFIG_CPM2)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530672 gd->arch.vco_out = 2*sys_info.freq_systembus;
Simon Glass748cd052012-12-13 20:48:46 +0000673 gd->arch.cpm_clk = gd->arch.vco_out / 2;
674 gd->arch.scc_clk = gd->arch.vco_out / 4;
675 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
wdenk42d1f032003-10-15 23:53:47 +0000676#endif
677
678 if(gd->cpu_clk != 0) return (0);
679 else return (1);
680}
681
682
683/********************************************
684 * get_bus_freq
685 * return system bus freq in Hz
686 *********************************************/
687ulong get_bus_freq (ulong dummy)
688{
James Yanga3e77fa2008-02-08 18:05:08 -0600689 return gd->bus_clk;
wdenk42d1f032003-10-15 23:53:47 +0000690}
Kumar Galad4357932007-12-07 04:59:26 -0600691
692/********************************************
693 * get_ddr_freq
694 * return ddr bus freq in Hz
695 *********************************************/
696ulong get_ddr_freq (ulong dummy)
697{
James Yanga3e77fa2008-02-08 18:05:08 -0600698 return gd->mem_clk;
Kumar Galad4357932007-12-07 04:59:26 -0600699}