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Stefano Babicf9c6fac2011-11-30 23:56:52 +00001/*
2 * Copyright (C) 2011
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * Copyright (C) 2009 TechNexion Ltd.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefano Babicf9c6fac2011-11-30 23:56:52 +00008 */
9
10#ifndef __TAM3517_H
11#define __TAM3517_H
12
13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_OMAP /* in a TI OMAP core */
17#define CONFIG_OMAP34XX /* which is a 34XX */
Marek Vasut308252a2012-07-21 05:02:23 +000018#define CONFIG_OMAP_GPIO
Lokesh Vutla806d2792013-07-30 11:36:30 +053019#define CONFIG_OMAP_COMMON
Stefano Babicf9c6fac2011-11-30 23:56:52 +000020
21#define CONFIG_SYS_TEXT_BASE 0x80008000
22
23#define CONFIG_SYS_CACHELINE_SIZE 64
24
25#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
26
27#include <asm/arch/cpu.h> /* get chip and board defs */
28#include <asm/arch/omap3.h>
29
30/*
31 * Display CPU and Board information
32 */
33#define CONFIG_DISPLAY_CPUINFO
34#define CONFIG_DISPLAY_BOARDINFO
35
36/* Clock Defines */
37#define V_OSCK 26000000 /* Clock output from T2 */
38#define V_SCLK (V_OSCK >> 1)
39
Stefano Babicf9c6fac2011-11-30 23:56:52 +000040#define CONFIG_MISC_INIT_R
41
42#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
43#define CONFIG_SETUP_MEMORY_TAGS
44#define CONFIG_INITRD_TAG
45#define CONFIG_REVISION_TAG
46
47/*
48 * Size of malloc() pool
49 */
50#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
51#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
52 2 * 1024 * 1024)
53/*
54 * DDR related
55 */
56#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
57#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
58
59/*
60 * Hardware drivers
61 */
62
63/*
64 * NS16550 Configuration
65 */
66#define CONFIG_SYS_NS16550
67#define CONFIG_SYS_NS16550_SERIAL
68#define CONFIG_SYS_NS16550_REG_SIZE (-4)
69#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
70
71/*
72 * select serial console configuration
73 */
74#define CONFIG_CONS_INDEX 1
75#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
76#define CONFIG_SERIAL1 /* UART1 */
77
78/* allow to overwrite serial and ethaddr */
79#define CONFIG_ENV_OVERWRITE
80#define CONFIG_BAUDRATE 115200
81#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
82 115200}
83#define CONFIG_MMC
84#define CONFIG_OMAP_HSMMC
85#define CONFIG_GENERIC_MMC
86#define CONFIG_DOS_PARTITION
87
88/* EHCI */
89#define CONFIG_OMAP3_GPIO_5
90#define CONFIG_USB_EHCI
91#define CONFIG_USB_EHCI_OMAP
Stefano Babic8c589d62012-02-07 23:28:58 +000092#define CONFIG_USB_ULPI
93#define CONFIG_USB_ULPI_VIEWPORT_OMAP
Stefano Babicf9c6fac2011-11-30 23:56:52 +000094#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
95#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
96#define CONFIG_USB_STORAGE
97
Stefano Babicf9c6fac2011-11-30 23:56:52 +000098/* commands to include */
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_CACHE
102#define CONFIG_CMD_DHCP
103#define CONFIG_CMD_EXT2 /* EXT2 Support */
104#define CONFIG_CMD_FAT /* FAT support */
105#define CONFIG_CMD_GPIO
106#define CONFIG_CMD_I2C /* I2C serial bus support */
107#define CONFIG_CMD_MII
108#define CONFIG_CMD_MMC /* MMC support */
109#define CONFIG_CMD_NET
110#define CONFIG_CMD_NFS
111#define CONFIG_CMD_NAND /* NAND support */
112#define CONFIG_CMD_PING
113#define CONFIG_CMD_USB
Stefano Babic8103c6f2012-08-29 01:21:59 +0000114#define CONFIG_CMD_EEPROM
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000115
116#undef CONFIG_CMD_FLASH /* only NAND on the SOM */
117#undef CONFIG_CMD_IMLS
118
119#define CONFIG_SYS_NO_FLASH
Heiko Schocher6789e842013-10-22 11:03:18 +0200120#define CONFIG_SYS_I2C
121#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
122#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
123#define CONFIG_SYS_I2C_OMAP34XX
Stefano Babic8103c6f2012-08-29 01:21:59 +0000124#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
125#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
126#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000127
128/*
129 * Board NAND Info.
130 */
131#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
132 /* to access */
133 /* nand at CS0 */
134
135#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
136 /* NAND devices */
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000137
138#define CONFIG_AUTO_COMPLETE
139
140/*
141 * Miscellaneous configurable options
142 */
143#define CONFIG_SYS_LONGHELP /* undef to save memory */
144#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000145#define CONFIG_CMDLINE_EDITING
146#define CONFIG_AUTO_COMPLETE
147#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
148
149/* Print Buffer Size */
150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
151 sizeof(CONFIG_SYS_PROMPT) + 16)
152#define CONFIG_SYS_MAXARGS 32 /* max number of command */
153 /* args */
154/* Boot Argument Buffer Size */
155#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
156/* memtest works on */
157#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
158#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
159 0x01F00000) /* 31MB */
160
161#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
162 /* address */
163
164/*
165 * AM3517 has 12 GP timers, they can be driven by the system clock
166 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
167 * This rate is divided by a local divisor.
168 */
169#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
170#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000171
172/*
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000173 * Physical Memory Map
174 */
175#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
176#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000177#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
178
179/*
180 * FLASH and environment organization
181 */
182
183/* **** PISMO SUPPORT *** */
184
185/* Configure the PISMO */
186#define PISMO1_NAND_SIZE GPMC_SIZE_128M
187
188#define CONFIG_NAND_OMAP_GPMC
189#define GPMC_NAND_ECC_LP_x16_LAYOUT
190#define CONFIG_ENV_IS_IN_NAND
191#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
192
193/* Redundant Environment */
194#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
195#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
196#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
197#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
198 2 * CONFIG_SYS_ENV_SECT_SIZE)
199#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
200
201#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
202#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
203#define CONFIG_SYS_INIT_RAM_SIZE 0x800
204#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
205 CONFIG_SYS_INIT_RAM_SIZE - \
206 GENERATED_GBL_DATA_SIZE)
207
208/*
209 * ethernet support, EMAC
210 *
211 */
212#define CONFIG_DRIVER_TI_EMAC
213#define CONFIG_DRIVER_TI_EMAC_USE_RMII
214#define CONFIG_MII
215#define CONFIG_EMAC_MDIO_PHY_NUM 0
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000216#define CONFIG_BOOTP_DNS
217#define CONFIG_BOOTP_DNS2
218#define CONFIG_BOOTP_SEND_HOSTNAME
219#define CONFIG_NET_RETRY_COUNT 10
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000220
221/* Defines for SPL */
222#define CONFIG_SPL
Tom Rini47f7bca2012-08-13 12:03:19 -0700223#define CONFIG_SPL_FRAMEWORK
Tom Rinid7cb93b2012-08-14 12:26:08 -0700224#define CONFIG_SPL_BOARD_INIT
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000225#define CONFIG_SPL_CONSOLE
226#define CONFIG_SPL_NAND_SIMPLE
227#define CONFIG_SPL_NAND_SOFTECC
228#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
229
230#define CONFIG_SPL_LIBCOMMON_SUPPORT
231#define CONFIG_SPL_LIBDISK_SUPPORT
232#define CONFIG_SPL_I2C_SUPPORT
233#define CONFIG_SPL_LIBGENERIC_SUPPORT
234#define CONFIG_SPL_SERIAL_SUPPORT
Marek Vasut16e41c82012-07-21 05:02:27 +0000235#define CONFIG_SPL_GPIO_SUPPORT
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000236#define CONFIG_SPL_POWER_SUPPORT
237#define CONFIG_SPL_NAND_SUPPORT
Scott Wood6f2f01b2012-09-20 19:09:07 -0500238#define CONFIG_SPL_NAND_BASE
239#define CONFIG_SPL_NAND_DRIVERS
240#define CONFIG_SPL_NAND_ECC
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000241#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
242
243#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
Tom Rinie0820cc2012-05-08 07:29:31 +0000244#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000245#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
246
247#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
248#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
249#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
250#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
251
252/* NAND boot config */
253#define CONFIG_SYS_NAND_PAGE_COUNT 64
254#define CONFIG_SYS_NAND_PAGE_SIZE 2048
255#define CONFIG_SYS_NAND_OOBSIZE 64
256#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
257#define CONFIG_SYS_NAND_5_ADDR_CYCLE
258#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
259#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
260 48, 49, 50, 51, 52, 53, 54, 55,\
261 56, 57, 58, 59, 60, 61, 62, 63}
262#define CONFIG_SYS_NAND_ECCSIZE 256
263#define CONFIG_SYS_NAND_ECCBYTES 3
264
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000265#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
266
267#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
268#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
269
270#define CONFIG_OF_LIBFDT
271#define CONFIG_FIT
272#define CONFIG_CMD_UBI
273#define CONFIG_CMD_UBIFS
274#define CONFIG_RBTREE
275#define CONFIG_LZO
276#define CONFIG_MTD_PARTITIONS
277#define CONFIG_MTD_DEVICE
278#define CONFIG_CMD_MTDPARTS
279
280/* Setup MTD for NAND on the SOM */
281#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
282#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
Stefano Babic1fdabed2012-02-07 23:29:34 +0000283 "1m(u-boot),256k(env1)," \
284 "256k(env2),6m(kernel),-(rootfs)"
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000285
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000286#define CONFIG_TAM3517_SETTINGS \
287 "netdev=eth0\0" \
288 "nandargs=setenv bootargs root=${nandroot} " \
289 "rootfstype=${nandrootfstype}\0" \
290 "nfsargs=setenv bootargs root=/dev/nfs rw " \
291 "nfsroot=${serverip}:${rootpath}\0" \
292 "ramargs=setenv bootargs root=/dev/ram rw\0" \
293 "addip_sta=setenv bootargs ${bootargs} " \
294 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
295 ":${hostname}:${netdev}:off panic=1\0" \
296 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
297 "addip=if test -n ${ipdyn};then run addip_dyn;" \
298 "else run addip_sta;fi\0" \
299 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
300 "addtty=setenv bootargs ${bootargs}" \
301 " console=ttyO0,${baudrate}\0" \
302 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
303 "loadaddr=82000000\0" \
304 "kernel_addr_r=82000000\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200305 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
306 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000307 "flash_self=run ramargs addip addtty addmtd addmisc;" \
308 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
309 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
310 "bootm ${kernel_addr}\0" \
311 "nandboot=run nandargs addip addtty addmtd addmisc;" \
312 "nand read ${kernel_addr_r} kernel\0" \
313 "bootm ${kernel_addr_r}\0" \
314 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
315 "run nfsargs addip addtty addmtd addmisc;" \
316 "bootm ${kernel_addr_r}\0" \
317 "net_self=if run net_self_load;then " \
318 "run ramargs addip addtty addmtd addmisc;" \
319 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
320 "else echo Images not loades;fi\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200321 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000322 "load=tftp ${loadaddr} ${u-boot}\0" \
323 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200324 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000325 "uboot_addr=0x80000\0" \
326 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
327 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
328 "updatemlo=nandecc hw;nand erase 0 20000;" \
329 "nand write ${loadaddr} 0 20000\0" \
330 "upd=if run load;then echo Updating u-boot;if run update;" \
331 "then echo U-Boot updated;" \
332 "else echo Error updating u-boot !;" \
333 "echo Board without bootloader !!;" \
334 "fi;" \
335 "else echo U-Boot not downloaded..exiting;fi\0" \
336
Stefano Babic8103c6f2012-08-29 01:21:59 +0000337
338/*
339 * this is common code for all TAM3517 boards.
340 * MAC address is stored from manufacturer in
341 * I2C EEPROM
342 */
343#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
Stefano Babic8103c6f2012-08-29 01:21:59 +0000344/*
345 * The I2C EEPROM on the TAM3517 contains
346 * mac address and production data
347 */
348struct tam3517_module_info {
349 char customer[48];
350 char product[48];
351
352 /*
353 * bit 0~47 : sequence number
354 * bit 48~55 : week of year, from 0.
355 * bit 56~63 : year
356 */
357 unsigned long long sequence_number;
358
359 /*
360 * bit 0~7 : revision fixed
361 * bit 8~15 : revision major
362 * bit 16~31 : TNxxx
363 */
364 unsigned int revision;
365 unsigned char eth_addr[4][8];
366 unsigned char _rev[100];
367};
368
Stefano Babic31f5b652012-11-23 05:19:25 +0000369#define TAM3517_READ_EEPROM(info, ret) \
370do { \
Heiko Schocher6789e842013-10-22 11:03:18 +0200371 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
Stefano Babic8103c6f2012-08-29 01:21:59 +0000372 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
Stefano Babic31f5b652012-11-23 05:19:25 +0000373 (void *)info, sizeof(*info))) \
374 ret = 1; \
375 else \
376 ret = 0; \
377} while (0)
378
379#define TAM3517_READ_MAC_FROM_EEPROM(info) \
380do { \
381 char buf[80], ethname[20]; \
382 int i; \
Stefano Babic8103c6f2012-08-29 01:21:59 +0000383 memset(buf, 0, sizeof(buf)); \
Stefano Babic31f5b652012-11-23 05:19:25 +0000384 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
Stefano Babic8103c6f2012-08-29 01:21:59 +0000385 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
Stefano Babic31f5b652012-11-23 05:19:25 +0000386 (info)->eth_addr[i][5], \
387 (info)->eth_addr[i][4], \
388 (info)->eth_addr[i][3], \
389 (info)->eth_addr[i][2], \
390 (info)->eth_addr[i][1], \
391 (info)->eth_addr[i][0]); \
Stefano Babic8103c6f2012-08-29 01:21:59 +0000392 \
393 if (i) \
394 sprintf(ethname, "eth%daddr", i); \
395 else \
396 sprintf(ethname, "ethaddr"); \
397 printf("Setting %s from EEPROM with %s\n", ethname, buf);\
398 setenv(ethname, buf); \
399 } \
400} while (0)
Stefano Babic31f5b652012-11-23 05:19:25 +0000401
402/* The following macros are taken from Technexion's documentation */
403#define TAM3517_sequence_number(info) \
404 ((info)->sequence_number % 0x1000000000000LL)
405#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
406#define TAM3517_year(info) ((info)->sequence_number >> 56)
407#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
408#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
409#define TAM3517_revision_tn(info) ((info)->revision >> 16)
410
411#define TAM3517_PRINT_SOM_INFO(info) \
412do { \
413 printf("Vendor:%s\n", (info)->customer); \
414 printf("SOM: %s\n", (info)->product); \
415 printf("SeqNr: %02llu%02llu%012llu\n", \
416 TAM3517_year(info), \
417 TAM3517_week_of_year(info), \
418 TAM3517_sequence_number(info)); \
419 printf("Rev: TN%u %u.%u\n", \
420 TAM3517_revision_tn(info), \
421 TAM3517_revision_major(info), \
422 TAM3517_revision_fixed(info)); \
423} while (0)
424
Stefano Babic8103c6f2012-08-29 01:21:59 +0000425#endif
426
Stefano Babicf9c6fac2011-11-30 23:56:52 +0000427#endif /* __TAM3517_H */