blob: c19f4a03ba07d1ddc93e182d16cf2607ec7bca3b [file] [log] [blame]
Bin Meng5dad97e2014-12-17 15:50:48 +08001#
2# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4#
5# SPDX-License-Identifier: GPL-2.0+
6#
7
8U-Boot on x86
9=============
10
11This document describes the information about U-Boot running on x86 targets,
12including supported boards, build instructions, todo list, etc.
13
14Status
15------
16U-Boot supports running as a coreboot [1] payload on x86. So far only Link
Bin Meng1ae5b782015-05-07 21:34:12 +080017(Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should
18work with minimal adjustments on other x86 boards since coreboot deals with
19most of the low-level details.
Bin Meng5dad97e2014-12-17 15:50:48 +080020
21U-Boot also supports booting directly from x86 reset vector without coreboot,
Bin Meng1ae5b782015-05-07 21:34:12 +080022aka raw support or bare support. Currently Link, QEMU x86 targets and all
23Intel boards support running U-Boot 'bare metal'.
Bin Meng5dad97e2014-12-17 15:50:48 +080024
Simon Glass3a1a18f2015-01-27 22:13:47 -070025As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
26Linux kernel as part of a FIT image. It also supports a compressed zImage.
Bin Meng5dad97e2014-12-17 15:50:48 +080027
28Build Instructions
29------------------
30Building U-Boot as a coreboot payload is just like building U-Boot for targets
31on other architectures, like below:
32
33$ make coreboot-x86_defconfig
34$ make all
35
Bin Meng1ae5b782015-05-07 21:34:12 +080036Note this default configuration will build a U-Boot payload for the QEMU board.
Bin Meng617b8672015-01-06 22:14:24 +080037To build a coreboot payload against another board, you can change the build
38configuration during the 'make menuconfig' process.
39
40x86 architecture --->
41 ...
Bin Meng1ae5b782015-05-07 21:34:12 +080042 (qemu-x86) Board configuration file
Bin Meng683b09d2015-06-03 09:20:04 +080043 (qemu-x86_i440fx) Board Device Tree Source (dts) file
Bin Meng1ae5b782015-05-07 21:34:12 +080044 (0x01920000) Board specific Cache-As-RAM (CAR) address
Bin Meng617b8672015-01-06 22:14:24 +080045 (0x4000) Board specific Cache-As-RAM (CAR) size
46
47Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
48to point to a new board. You can also change the Cache-As-RAM (CAR) related
49settings here if the default values do not fit your new board.
50
Simon Glass3a1a18f2015-01-27 22:13:47 -070051Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
Bin Meng5dad97e2014-12-17 15:50:48 +080052little bit tricky, as generally it requires several binary blobs which are not
53shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
54not turned on by default in the U-Boot source tree. Firstly, you need turn it
Simon Glasseea0f112015-01-27 22:13:32 -070055on by enabling the ROM build:
Bin Meng5dad97e2014-12-17 15:50:48 +080056
Simon Glasseea0f112015-01-27 22:13:32 -070057$ export BUILD_ROM=y
58
59This tells the Makefile to build u-boot.rom as a target.
Bin Meng5dad97e2014-12-17 15:50:48 +080060
61Link-specific instructions:
62
63First, you need the following binary blobs:
64
65* descriptor.bin - Intel flash descriptor
66* me.bin - Intel Management Engine
67* mrc.bin - Memory Reference Code, which sets up SDRAM
68* video ROM - sets up the display
69
70You can get these binary blobs by:
71
72$ git clone http://review.coreboot.org/p/blobs.git
73$ cd blobs
74
75Find the following files:
76
77* ./mainboard/google/link/descriptor.bin
78* ./mainboard/google/link/me.bin
Simon Glass8712af92015-04-19 22:05:37 -060079* ./northbridge/intel/sandybridge/systemagent-r6.bin
Bin Meng5dad97e2014-12-17 15:50:48 +080080
81The 3rd one should be renamed to mrc.bin.
Bin Meng1ae5b782015-05-07 21:34:12 +080082As for the video ROM, you can get it here [3].
Bin Meng5dad97e2014-12-17 15:50:48 +080083Make sure all these binary blobs are put in the board directory.
84
85Now you can build U-Boot and obtain u-boot.rom:
86
87$ make chromebook_link_defconfig
88$ make all
89
90Intel Crown Bay specific instructions:
91
Bin Meng1ae5b782015-05-07 21:34:12 +080092U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
93Firmware Support Package [5] to perform all the necessary initialization steps
Bin Meng5dad97e2014-12-17 15:50:48 +080094as documented in the BIOS Writer Guide, including initialization of the CPU,
95memory controller, chipset and certain bus interfaces.
96
97Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
98install it on your host and locate the FSP binary blob. Note this platform
99also requires a Chipset Micro Code (CMC) state machine binary to be present in
100the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
101in this FSP package too.
102
103* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
104* ./Microcode/C0_22211.BIN
105
106Rename the first one to fsp.bin and second one to cmc.bin and put them in the
107board directory.
108
Bin Meng83d97122015-03-05 11:21:03 +0800109Note the FSP release version 001 has a bug which could cause random endless
110loop during the FspInit call. This bug was published by Intel although Intel
111did not describe any details. We need manually apply the patch to the FSP
112binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
113binary, change the following five bytes values from orginally E8 42 FF FF FF
114to B8 00 80 0B 00.
115
Bin Meng617b8672015-01-06 22:14:24 +0800116Now you can build U-Boot and obtain u-boot.rom
Bin Meng5dad97e2014-12-17 15:50:48 +0800117
118$ make crownbay_defconfig
119$ make all
120
Simon Glass3a1a18f2015-01-27 22:13:47 -0700121Intel Minnowboard Max instructions:
122
123This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
124Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
125the time of writing). Put it in the board directory:
126board/intel/minnowmax/fsp.bin
127
128Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
129directory: board/intel/minnowmax/vga.bin
130
Simon Glass68522482015-04-25 11:46:43 -0600131You still need two more binary blobs. The first comes from the original
132firmware image available from:
133
134http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
135
136Unzip it:
137
138 $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
Simon Glass3a1a18f2015-01-27 22:13:47 -0700139
140Use ifdtool in the U-Boot tools directory to extract the images from that
141file, for example:
142
Simon Glass68522482015-04-25 11:46:43 -0600143 $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
144
145This will provide the descriptor file - copy this into the correct place:
146
147 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
148
149Then do the same with the sample SPI image provided in the FSP (SPI.bin at
150the time of writing) to obtain the last image. Note that this will also
151produce a flash descriptor file, but it does not seem to work, probably
152because it is not designed for the Minnowmax. That is why you need to get
153the flash descriptor from the original firmware as above.
154
Simon Glass3a1a18f2015-01-27 22:13:47 -0700155 $ ./tools/ifdtool -x BayleyBay/SPI.bin
156 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
Simon Glass3a1a18f2015-01-27 22:13:47 -0700157
158Now you can build U-Boot and obtain u-boot.rom
159
160$ make minnowmax_defconfig
161$ make all
162
Bin Meng67582c02015-02-04 16:26:14 +0800163Intel Galileo instructions:
164
165Only one binary blob is needed for Remote Management Unit (RMU) within Intel
166Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
167needed by the Quark SoC itself.
168
169You can get the binary blob from Quark Board Support Package from Intel website:
170
171* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
172
173Rename the file and put it to the board directory by:
174
175 $ cp RMU.bin board/intel/galileo/rmu.bin
176
177Now you can build U-Boot and obtain u-boot.rom
178
179$ make galileo_defconfig
180$ make all
Simon Glass3a1a18f2015-01-27 22:13:47 -0700181
Bin Meng1ae5b782015-05-07 21:34:12 +0800182QEMU x86 target instructions:
183
184To build u-boot.rom for QEMU x86 targets, just simply run
185
186$ make qemu-x86_defconfig
187$ make all
188
Bin Meng683b09d2015-06-03 09:20:04 +0800189Note this default configuration will build a U-Boot for the QEMU x86 i440FX
190board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
191configuration during the 'make menuconfig' process like below:
192
193Device Tree Control --->
194 ...
195 (qemu-x86_q35) Default Device Tree for DT control
196
Bin Meng617b8672015-01-06 22:14:24 +0800197Test with coreboot
198------------------
199For testing U-Boot as the coreboot payload, there are things that need be paid
200attention to. coreboot supports loading an ELF executable and a 32-bit plain
201binary, as well as other supported payloads. With the default configuration,
202U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
203generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
204provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
205this capability yet. The command is as follows:
206
207# in the coreboot root directory
208$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
209 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
210
211Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
212symbol address of _start (in arch/x86/cpu/start.S).
213
214If you want to use ELF as the coreboot payload, change U-Boot configuration to
Simon Glasseea0f112015-01-27 22:13:32 -0700215use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
Bin Meng617b8672015-01-06 22:14:24 +0800216
Simon Glass3a1a18f2015-01-27 22:13:47 -0700217To enable video you must enable these options in coreboot:
218
219 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
220 - Keep VESA framebuffer
221
222At present it seems that for Minnowboard Max, coreboot does not pass through
223the video information correctly (it always says the resolution is 0x0). This
224works correctly for link though.
225
Bin Meng1ae5b782015-05-07 21:34:12 +0800226Test with QEMU
227--------------
228QEMU is a fancy emulator that can enable us to test U-Boot without access to
Bin Meng9c4f5412015-05-11 07:36:30 +0800229a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
230U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows:
Bin Meng1ae5b782015-05-07 21:34:12 +0800231
232$ qemu-system-i386 -nographic -bios path/to/u-boot.rom
233
234This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
235also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
236also supported by U-Boot. To instantiate such a machine, call QEMU with:
237
238$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
239
240Note by default QEMU instantiated boards only have 128 MiB system memory. But
241it is enough to have U-Boot boot and function correctly. You can increase the
242system memory by pass '-m' parameter to QEMU if you want more memory:
243
244$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
245
246This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
247supports 3 GiB maximum system memory and reserves the last 1 GiB address space
248for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
249would be 3072.
Simon Glass3a1a18f2015-01-27 22:13:47 -0700250
Bin Meng9c4f5412015-05-11 07:36:30 +0800251QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
252show QEMU's VGA console window. Note this will disable QEMU's serial output.
253If you want to check both consoles, use '-serial stdio'.
254
Bin Meng5dad97e2014-12-17 15:50:48 +0800255CPU Microcode
256-------------
Bin Meng1ae5b782015-05-07 21:34:12 +0800257Modern CPUs usually require a special bit stream called microcode [6] to be
Bin Meng5dad97e2014-12-17 15:50:48 +0800258loaded on the processor after power up in order to function properly. U-Boot
259has already integrated these as hex dumps in the source tree.
260
261Driver Model
262------------
263x86 has been converted to use driver model for serial and GPIO.
264
265Device Tree
266-----------
267x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
Bin Meng617b8672015-01-06 22:14:24 +0800268be turned on. Not every device on the board is configured via device tree, but
Bin Meng5dad97e2014-12-17 15:50:48 +0800269more and more devices will be added as time goes by. Check out the directory
270arch/x86/dts/ for these device tree source files.
271
Simon Glasscb3b2e62015-01-01 16:18:15 -0700272Useful Commands
273---------------
Simon Glasscb3b2e62015-01-01 16:18:15 -0700274In keeping with the U-Boot philosophy of providing functions to check and
275adjust internal settings, there are several x86-specific commands that may be
276useful:
277
278hob - Display information about Firmware Support Package (FSP) Hand-off
279 Block. This is only available on platforms which use FSP, mostly
280 Atom.
281iod - Display I/O memory
282iow - Write I/O memory
283mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
284 tell the CPU whether memory is cacheable and if so the cache write
285 mode to use. U-Boot sets up some reasonable values but you can
286 adjust then with this command.
287
Simon Glass00bdd952015-01-27 22:13:46 -0700288Development Flow
289----------------
Simon Glass00bdd952015-01-27 22:13:46 -0700290These notes are for those who want to port U-Boot to a new x86 platform.
291
292Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
293The Dediprog em100 can be used on Linux. The em100 tool is available here:
294
295 http://review.coreboot.org/p/em100.git
296
297On Minnowboard Max the following command line can be used:
298
299 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
300
301A suitable clip for connecting over the SPI flash chip is here:
302
303 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
304
305This allows you to override the SPI flash contents for development purposes.
306Typically you can write to the em100 in around 1200ms, considerably faster
307than programming the real flash device each time. The only important
308limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
309This means that images must be set to boot with that speed. This is an
310Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
311speed in the SPI descriptor region.
312
313If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
314easy to fit it in. You can follow the Minnowboard Max implementation, for
315example. Hopefully you will just need to create new files similar to those
316in arch/x86/cpu/baytrail which provide Bay Trail support.
317
318If you are not using an FSP you have more freedom and more responsibility.
319The ivybridge support works this way, although it still uses a ROM for
320graphics and still has binary blobs containing Intel code. You should aim to
321support all important peripherals on your platform including video and storage.
322Use the device tree for configuration where possible.
323
324For the microcode you can create a suitable device tree file using the
325microcode tool:
326
327 ./tools/microcode-tool -d microcode.dat create <model>
328
329or if you only have header files and not the full Intel microcode.dat database:
330
331 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
332 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
333 create all
334
335These are written to arch/x86/dts/microcode/ by default.
336
337Note that it is possible to just add the micrcode for your CPU if you know its
338model. U-Boot prints this information when it starts
339
340 CPU: x86_64, vendor Intel, device 30673h
341
342so here we can use the M0130673322 file.
343
344If you platform can display POST codes on two little 7-segment displays on
345the board, then you can use post_code() calls from C or assembler to monitor
346boot progress. This can be good for debugging.
347
348If not, you can try to get serial working as early as possible. The early
349debug serial port may be useful here. See setup_early_uart() for an example.
350
Bin Meng5dad97e2014-12-17 15:50:48 +0800351TODO List
352---------
Bin Meng5dad97e2014-12-17 15:50:48 +0800353- Audio
354- Chrome OS verified boot
355- SMI and ACPI support, to provide platform info and facilities to Linux
356
357References
358----------
359[1] http://www.coreboot.org
Bin Meng1ae5b782015-05-07 21:34:12 +0800360[2] http://www.qemu.org
361[3] http://www.coreboot.org/~stepan/pci8086,0166.rom
362[4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
363[5] http://www.intel.com/fsp
364[6] http://en.wikipedia.org/wiki/Microcode