blob: 84cc9fa41ea02ce15e736df16c9b1c7e7b2423ff [file] [log] [blame]
Dave Liu8bd522c2008-01-11 18:48:24 +08001/*
Vivek Mahajan6823e9b2009-05-25 17:23:17 +05302 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
Dave Liu8bd522c2008-01-11 18:48:24 +08003 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
Dave Liu8bd522c2008-01-11 18:48:24 +080028/*
29 * High Level Configuration Options
30 */
31#define CONFIG_E300 1 /* E300 family */
Peter Tyser0f898602009-05-22 17:23:24 -050032#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050033#define CONFIG_MPC831x 1 /* MPC831x CPU family */
Dave Liu8bd522c2008-01-11 18:48:24 +080034#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
35#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
36
37/*
38 * System Clock Setup
39 */
40#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
41#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
42
43/*
44 * Hardware Reset Configuration Word
45 * if CLKIN is 66.66MHz, then
46 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
47 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_HRCW_LOW (\
Dave Liu8bd522c2008-01-11 18:48:24 +080049 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
50 HRCWL_DDR_TO_SCB_CLK_2X1 |\
51 HRCWL_SVCOD_DIV_2 |\
52 HRCWL_CSB_TO_CLKIN_2X1 |\
53 HRCWL_CORE_TO_CSB_3X1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu8bd522c2008-01-11 18:48:24 +080055 HRCWH_PCI_HOST |\
56 HRCWH_PCI1_ARBITER_ENABLE |\
57 HRCWH_CORE_ENABLE |\
58 HRCWH_FROM_0X00000100 |\
59 HRCWH_BOOTSEQ_DISABLE |\
60 HRCWH_SW_WATCHDOG_DISABLE |\
61 HRCWH_ROM_LOC_LOCAL_16BIT |\
62 HRCWH_RL_EXT_LEGACY |\
63 HRCWH_TSEC1M_IN_RGMII |\
64 HRCWH_TSEC2M_IN_RGMII |\
65 HRCWH_BIG_ENDIAN |\
66 HRCWH_LALE_NORMAL)
67
68/*
69 * System IO Config
70 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_SICRH 0x00000000
72#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
Dave Liu8bd522c2008-01-11 18:48:24 +080073
74#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Anton Vorontsovb8b71ff2009-06-10 00:25:36 +040075#define CONFIG_HWCONFIG
Dave Liu8bd522c2008-01-11 18:48:24 +080076
77/*
78 * IMMR new address
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu8bd522c2008-01-11 18:48:24 +080081
82/*
83 * Arbiter Setup
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
86#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
87#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
Dave Liu8bd522c2008-01-11 18:48:24 +080088
89/*
90 * DDR Setup
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
93#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
94#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
95#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
96#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
Dave Liu8bd522c2008-01-11 18:48:24 +080097 | DDRCDR_PZ_LOZ \
98 | DDRCDR_NZ_LOZ \
99 | DDRCDR_ODT \
100 | DDRCDR_Q_DRN )
101 /* 0x7b880001 */
102/*
103 * Manually set up DDR parameters
104 * consist of two chips HY5PS12621BFP-C4 from HYNIX
105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_DDR_SIZE 128 /* MB */
107#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
108#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
Dave Liu8bd522c2008-01-11 18:48:24 +0800109 | 0x00010000 /* ODT_WR to CSn */ \
110 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
111 /* 0x80010102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_DDR_TIMING_3 0x00000000
113#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800114 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
115 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
116 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
117 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
118 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
119 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
120 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
121 /* 0x00220802 */
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800122#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
123 | ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
124 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800125 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
126 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
127 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
128 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
129 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800130 /* 0x27256222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800132 | ( 4 << TIMING_CFG2_CPO_SHIFT ) \
133 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
134 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
135 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
136 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800137 | ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
138 /* 0x121048c5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800140 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
141 /* 0x03600100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
Dave Liu8bd522c2008-01-11 18:48:24 +0800143 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
144 | SDRAM_CFG_32_BE )
145 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
147#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800148 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
149 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800151
152/*
153 * Memory test
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
156#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
157#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu8bd522c2008-01-11 18:48:24 +0800158
159/*
160 * The reserved memory
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Dave Liu8bd522c2008-01-11 18:48:24 +0800163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
165#define CONFIG_SYS_RAMBOOT
Dave Liu8bd522c2008-01-11 18:48:24 +0800166#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#undef CONFIG_SYS_RAMBOOT
Dave Liu8bd522c2008-01-11 18:48:24 +0800168#endif
169
Dave Liu1ac57442008-11-04 14:55:06 +0800170#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu8bd522c2008-01-11 18:48:24 +0800172
173/*
174 * Initial RAM Base Address Setup
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_INIT_RAM_LOCK 1
177#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
178#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
179#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
180#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Dave Liu8bd522c2008-01-11 18:48:24 +0800181
182/*
183 * Local Bus Configuration & Clock Setup
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
186#define CONFIG_SYS_LBC_LBCR 0x00040000
Dave Liu8bd522c2008-01-11 18:48:24 +0800187
188/*
189 * FLASH on the Local Bus
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200192#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Dave Liu8bd522c2008-01-11 18:48:24 +0800194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
196#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
197#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu8bd522c2008-01-11 18:48:24 +0800198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
200#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
Dave Liu8bd522c2008-01-11 18:48:24 +0800203 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \
204 | BR_V ) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800206 | OR_UPM_XAM \
207 | OR_GPCM_CSNT \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400208 | OR_GPCM_ACS_DIV2 \
Dave Liu8bd522c2008-01-11 18:48:24 +0800209 | OR_GPCM_XACS \
210 | OR_GPCM_SCY_15 \
211 | OR_GPCM_TRLX \
212 | OR_GPCM_EHTR \
213 | OR_GPCM_EAD )
214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
216#define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */
Dave Liu8bd522c2008-01-11 18:48:24 +0800217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#undef CONFIG_SYS_FLASH_CHECKSUM
219#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
220#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu8bd522c2008-01-11 18:48:24 +0800221
222/*
223 * NAND Flash on the Local Bus
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
226#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dave Liu1ac57442008-11-04 14:55:06 +0800227#define CONFIG_MTD_NAND_VERIFY_WRITE 1
228#define CONFIG_CMD_NAND 1
229#define CONFIG_NAND_FSL_ELBC 1
Kim Phillipsd9ac3d52009-06-15 11:51:47 -0500230#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
Dave Liu8bd522c2008-01-11 18:48:24 +0800231
Dave Liu1ac57442008-11-04 14:55:06 +0800232#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
Dave Liu8bd522c2008-01-11 18:48:24 +0800233 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
234 | BR_PS_8 /* Port Size = 8 bit */ \
235 | BR_MS_FCM /* MSEL = FCM */ \
236 | BR_V ) /* valid */
Dave Liu1ac57442008-11-04 14:55:06 +0800237#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
Dave Liu8bd522c2008-01-11 18:48:24 +0800238 | OR_FCM_CSCT \
239 | OR_FCM_CST \
240 | OR_FCM_CHT \
241 | OR_FCM_SCY_1 \
242 | OR_FCM_TRLX \
243 | OR_FCM_EHTR )
244 /* 0xFFFF8396 */
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
247#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
Dave Liu8bd522c2008-01-11 18:48:24 +0800248
249/*
250 * Serial Port
251 */
252#define CONFIG_CONS_INDEX 1
253#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_NS16550
255#define CONFIG_SYS_NS16550_SERIAL
256#define CONFIG_SYS_NS16550_REG_SIZE 1
257#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu8bd522c2008-01-11 18:48:24 +0800258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_BAUDRATE_TABLE \
Dave Liu8bd522c2008-01-11 18:48:24 +0800260 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
263#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu8bd522c2008-01-11 18:48:24 +0800264
265/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_HUSH_PARSER
267#ifdef CONFIG_SYS_HUSH_PARSER
268#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Dave Liu8bd522c2008-01-11 18:48:24 +0800269#endif
270
271/* Pass open firmware flat tree */
272#define CONFIG_OF_LIBFDT 1
273#define CONFIG_OF_BOARD_SETUP 1
274#define CONFIG_OF_STDOUT_VIA_ALIAS 1
275
276/* I2C */
277#define CONFIG_HARD_I2C /* I2C with hardware support */
278#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
280#define CONFIG_SYS_I2C_SLAVE 0x7F
281#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
282#define CONFIG_SYS_I2C_OFFSET 0x3000
283#define CONFIG_SYS_I2C2_OFFSET 0x3100
Dave Liu8bd522c2008-01-11 18:48:24 +0800284
285/*
286 * Board info - revision and where boot from
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
Dave Liu8bd522c2008-01-11 18:48:24 +0800289
290/*
291 * Config on-board RTC
292 */
293#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu8bd522c2008-01-11 18:48:24 +0800295
296/*
297 * General PCI
298 * Addresses are mapped 1-1.
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
301#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
302#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
303#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
304#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
305#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
306#define CONFIG_SYS_PCI_IO_BASE 0x00000000
307#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
308#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu8bd522c2008-01-11 18:48:24 +0800309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
311#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
312#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800313
Anton Vorontsov8f11e342009-01-08 04:26:17 +0300314#define CONFIG_SYS_PCIE1_BASE 0xA0000000
315#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
316#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
317#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
318#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
319#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
320#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
321#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
322#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
323
324#define CONFIG_SYS_PCIE2_BASE 0xC0000000
325#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
326#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
327#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
328#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
329#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
330#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
331#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
332#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
333
Dave Liu8bd522c2008-01-11 18:48:24 +0800334#define CONFIG_PCI
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500335#define CONFIG_PCIE
Dave Liu8bd522c2008-01-11 18:48:24 +0800336
337#define CONFIG_NET_MULTI
338#define CONFIG_PCI_PNP /* do pci plug-and-play */
339
340#define CONFIG_EEPRO100
341#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu8bd522c2008-01-11 18:48:24 +0800343
344#ifndef CONFIG_NET_MULTI
345#define CONFIG_NET_MULTI 1
346#endif
347
Anton Vorontsov25f5f0d2008-07-08 21:00:04 +0400348#define CONFIG_HAS_FSL_DR_USB
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530349#define CONFIG_SYS_SCCR_USBDRCM 3
350
351#define CONFIG_CMD_USB
352#define CONFIG_USB_STORAGE
353#define CONFIG_USB_EHCI
354#define CONFIG_USB_EHCI_FSL
355#define CONFIG_USB_PHY_TYPE "utmi"
356#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov25f5f0d2008-07-08 21:00:04 +0400357
Dave Liu8bd522c2008-01-11 18:48:24 +0800358/*
359 * TSEC
360 */
361#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_TSEC1_OFFSET 0x24000
363#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
364#define CONFIG_SYS_TSEC2_OFFSET 0x25000
365#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu8bd522c2008-01-11 18:48:24 +0800366
367/*
368 * TSEC ethernet configuration
369 */
370#define CONFIG_MII 1 /* MII PHY management */
371#define CONFIG_TSEC1 1
372#define CONFIG_TSEC1_NAME "eTSEC0"
373#define CONFIG_TSEC2 1
374#define CONFIG_TSEC2_NAME "eTSEC1"
375#define TSEC1_PHY_ADDR 0
376#define TSEC2_PHY_ADDR 1
377#define TSEC1_PHYIDX 0
378#define TSEC2_PHYIDX 0
379#define TSEC1_FLAGS TSEC_GIGABIT
380#define TSEC2_FLAGS TSEC_GIGABIT
381
382/* Options are: eTSEC[0-1] */
383#define CONFIG_ETHPRIME "eTSEC1"
384
385/*
Kim Phillips730e7922008-03-28 14:31:23 -0500386 * SATA
387 */
388#define CONFIG_LIBATA
389#define CONFIG_FSL_SATA
390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips730e7922008-03-28 14:31:23 -0500392#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_SATA1_OFFSET 0x18000
394#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
395#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500396#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_SATA2_OFFSET 0x19000
398#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
399#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500400
401#ifdef CONFIG_FSL_SATA
402#define CONFIG_LBA48
403#define CONFIG_CMD_SATA
404#define CONFIG_DOS_PARTITION
405#define CONFIG_CMD_EXT2
406#endif
407
408/*
Dave Liu8bd522c2008-01-11 18:48:24 +0800409 * Environment
410 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200412 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200414 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
415 #define CONFIG_ENV_SIZE 0x2000
Dave Liu8bd522c2008-01-11 18:48:24 +0800416#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200418 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200420 #define CONFIG_ENV_SIZE 0x2000
Dave Liu8bd522c2008-01-11 18:48:24 +0800421#endif
422
423#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu8bd522c2008-01-11 18:48:24 +0800425
426/*
427 * BOOTP options
428 */
429#define CONFIG_BOOTP_BOOTFILESIZE
430#define CONFIG_BOOTP_BOOTPATH
431#define CONFIG_BOOTP_GATEWAY
432#define CONFIG_BOOTP_HOSTNAME
433
434/*
435 * Command line configuration.
436 */
437#include <config_cmd_default.h>
438
439#define CONFIG_CMD_PING
440#define CONFIG_CMD_I2C
441#define CONFIG_CMD_MII
442#define CONFIG_CMD_DATE
443#define CONFIG_CMD_PCI
444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500446 #undef CONFIG_CMD_SAVEENV
Dave Liu8bd522c2008-01-11 18:48:24 +0800447 #undef CONFIG_CMD_LOADS
448#endif
449
450#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
451
452#undef CONFIG_WATCHDOG /* watchdog disabled */
453
454/*
455 * Miscellaneous configurable options
456 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_LONGHELP /* undef to save memory */
458#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
459#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Dave Liu8bd522c2008-01-11 18:48:24 +0800460
461#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800463#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800465#endif
466
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
468#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
469#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
470#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Dave Liu8bd522c2008-01-11 18:48:24 +0800471
472/*
473 * For booting Linux, the board info and command line data
474 * have to be in the first 8 MB of memory, since this is
475 * the maximum mapped by the Linux kernel during initialization.
476 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Dave Liu8bd522c2008-01-11 18:48:24 +0800478
479/*
480 * Core HID Setup
481 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_HID0_INIT 0x000000000
483#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
Dave Liu8bd522c2008-01-11 18:48:24 +0800484 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu8bd522c2008-01-11 18:48:24 +0800486
487/*
488 * MMU Setup
489 */
Becky Bruce31d82672008-05-08 19:02:12 -0500490#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu8bd522c2008-01-11 18:48:24 +0800491
492/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
494#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
495#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
496#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu8bd522c2008-01-11 18:48:24 +0800497
498/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Dave Liu8bd522c2008-01-11 18:48:24 +0800500 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
502#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
503#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu8bd522c2008-01-11 18:48:24 +0800504
505/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
507#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
508#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Dave Liu8bd522c2008-01-11 18:48:24 +0800509 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu8bd522c2008-01-11 18:48:24 +0800511
512/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
514#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
515#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
516#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu8bd522c2008-01-11 18:48:24 +0800517
518/* PCI MEM space: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
520#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
521#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
522#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu8bd522c2008-01-11 18:48:24 +0800523
524/* PCI MMIO space: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200525#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
Dave Liu8bd522c2008-01-11 18:48:24 +0800526 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
528#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
529#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu8bd522c2008-01-11 18:48:24 +0800530
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200531#define CONFIG_SYS_IBAT6L 0
532#define CONFIG_SYS_IBAT6U 0
533#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
534#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu8bd522c2008-01-11 18:48:24 +0800535
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_IBAT7L 0
537#define CONFIG_SYS_IBAT7U 0
538#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
539#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu8bd522c2008-01-11 18:48:24 +0800540
541/*
542 * Internal Definitions
543 *
544 * Boot Flags
545 */
546#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
547#define BOOTFLAG_WARM 0x02 /* Software reboot */
548
549#if defined(CONFIG_CMD_KGDB)
550#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
551#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
552#endif
553
554/*
555 * Environment Configuration
556 */
557
558#define CONFIG_ENV_OVERWRITE
559
560#if defined(CONFIG_TSEC_ENET)
561#define CONFIG_HAS_ETH0
562#define CONFIG_ETHADDR 04:00:00:00:00:0A
563#define CONFIG_HAS_ETH1
564#define CONFIG_ETH1ADDR 04:00:00:00:00:0B
565#endif
566
567#define CONFIG_BAUDRATE 115200
568
Kim Phillips79f516b2009-08-21 16:34:38 -0500569#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu8bd522c2008-01-11 18:48:24 +0800570
571#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
572#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
573
574#define CONFIG_EXTRA_ENV_SETTINGS \
575 "netdev=eth0\0" \
576 "consoledev=ttyS0\0" \
577 "ramdiskaddr=1000000\0" \
578 "ramdiskfile=ramfs.83xx\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500579 "fdtaddr=780000\0" \
Dave Liu8bd522c2008-01-11 18:48:24 +0800580 "fdtfile=mpc8315erdb.dtb\0" \
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530581 "usb_phy_type=utmi\0" \
Dave Liu8bd522c2008-01-11 18:48:24 +0800582 ""
583
584#define CONFIG_NFSBOOTCOMMAND \
585 "setenv bootargs root=/dev/nfs rw " \
586 "nfsroot=$serverip:$rootpath " \
587 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
588 "console=$consoledev,$baudrate $othbootargs;" \
589 "tftp $loadaddr $bootfile;" \
590 "tftp $fdtaddr $fdtfile;" \
591 "bootm $loadaddr - $fdtaddr"
592
593#define CONFIG_RAMBOOTCOMMAND \
594 "setenv bootargs root=/dev/ram rw " \
595 "console=$consoledev,$baudrate $othbootargs;" \
596 "tftp $ramdiskaddr $ramdiskfile;" \
597 "tftp $loadaddr $bootfile;" \
598 "tftp $fdtaddr $fdtfile;" \
599 "bootm $loadaddr $ramdiskaddr $fdtaddr"
600
601
602#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
603
604#endif /* __CONFIG_H */