blob: dd8ccaad0e7ae32ef25636faa4403c44143047c0 [file] [log] [blame]
wdenk8bde7f72003-06-27 21:31:46 +00001 PowerPC 440
wdenkc6097192002-11-03 00:24:07 +00002
wdenk8bde7f72003-06-27 21:31:46 +00003 Last Update: September 11, 2002
wdenkc6097192002-11-03 00:24:07 +00004=======================================================================
5
6
7OVERVIEW
8============
9
10Support for the ppc440 is contained in the cpu/ppc44x directory
11and enabled via the CONFIG_440 flag. It is largely based on the
12405gp code. A sample board support implementation is contained
13in the board/ebony directory.
14
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020015All testing was performed using the AMCC Ebony board using both
wdenkc6097192002-11-03 00:24:07 +000016Rev B and Rev C silicon. However, since the Rev B. silicon has
17extensive errata, support for Rev B. is minimal (it boots, and
18features such as i2c, pci, tftpboot, etc. seem to work ok).
19The expectation is that all new board designs will be using
20Rev C or later parts -- if not, you may be in for a rough ride ;-)
21
22The ppc440 port does a fair job of keeping "board-specific" code
23out of the "cpu-specific" source. The goal of course was to
24provide mechanisms for each board to customize without having
25to clutter the cpu-specific source with a lot of ifdefs. Most
26of these mechanisms are described in the following sections.
27
28
29MEMORY MANAGEMENT
30=================
31
32The ppc440 doesn't run in "real mode". The MMU must be active
33at all times. Additionally, the 440 implements a 36-bit physical
34memory space that gets mapped into the PowerPC 32-bit virtual
35address space. So things like memory-mapped peripherals, etc must
36all be mapped in. Once this is done, the 32-bit virtual address
37space is then viewed as though it were physical memory.
38
39However, this means that memory, peripherals, etc can be configured
40to appear (mostly) anywhere in the virtual address space. Each board
41must define its own mappings using the tlbtab (see board/ebony/init.S).
42The actual TLB setup is performed by the cpu-specific code.
43
44Although each board is free to define its own mappings, there are
45several definitions to be aware of. These definitions may be used in
46the cpu-specific code (vs. board-specific code), so you should
47at least review these before deciding to make any changes ... it
48will probably save you some headaches ;-)
49
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050CONFIG_SYS_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0)
wdenkc6097192002-11-03 00:24:07 +000051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052CONFIG_SYS_FLASH_BASE - The virtual address where FLASH is mapped.
wdenkc6097192002-11-03 00:24:07 +000053
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054CONFIG_SYS_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped.
wdenkc6097192002-11-03 00:24:07 +000055 This mapping provides access to PCI-bus memory.
56
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057CONFIG_SYS_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped
wdenkc6097192002-11-03 00:24:07 +000058 peripherals are mapped. (e.g. -- UART registers, IIC registers, etc).
59
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060CONFIG_SYS_ISRAM_BASE - The virtual address where the 440 internal SRAM is
wdenkc6097192002-11-03 00:24:07 +000061 mapped. The internal SRAM is equivalent to 405gp OCM and is used
62 for the initial stack.
63
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064CONFIG_SYS_PCI_BASE - The virtual address where the 440 PCI-x bridge config
wdenkc6097192002-11-03 00:24:07 +000065 registers are mapped.
66
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067CONFIG_SYS_PCI_TARGBASE - The PCI address that is mapped to the virtual address
68 defined by CONFIG_SYS_PCI_MEMBASE.
wdenkc6097192002-11-03 00:24:07 +000069
70
71UART / SERIAL
72=================
73
74The UART port works fine when an external serial clock is provided
75(like the one on the Ebony board) and when using internal clocking.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076This is controlled with the CONFIG_SYS_EXT_SERIAL_CLOCK flag. When using
wdenkc6097192002-11-03 00:24:07 +000077internal clocking, the "ideal baud rate" settings in the 440GP
78user manual are automatically calculated.
79
wdenkc6097192002-11-03 00:24:07 +000080
81I2C
82=================
83
84The i2c utilities have been tested on both Rev B. and Rev C. and
Peter Tyser0f89c542009-04-18 22:34:03 -050085look good. The 'i2c probe' command implementation has been updated to
wdenkc6097192002-11-03 00:24:07 +000086allow for 'skipped' addresses. Some i2c slaves are write only and
87cause problems when a probe (read) is performed (for example the
88CDCV850 clock controller at address 0x69 on the ebony board).
89
90To prevent probing certain addresses you can define the
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091CONFIG_SYS_I2C_NOPROBES macro in your board-specific header file. When
wdenkc6097192002-11-03 00:24:07 +000092defined, all specified addresses are skipped during a probe.
93The addresses that are skipped will be displayed in the output
Peter Tyser0f89c542009-04-18 22:34:03 -050094of the 'i2c probe' command.
wdenkc6097192002-11-03 00:24:07 +000095
96For example, to prevent probing address 0x69, define the macro as
97follows:
98
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_I2C_NOPROBES {0x69}
wdenkc6097192002-11-03 00:24:07 +0000100
101Similarly, to prevent probing addresses 0x69 and 0x70, define the
102macro a:
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_I2C_NOPROBES {0x69, 0x70}
wdenkc6097192002-11-03 00:24:07 +0000105
106
107DDR SDRAM CONTROLLER
108====================
109
110SDRAM controller intialization using Serial Presence Detect (SPD) is
111now supported (thanks Jun). It is enabled by defining CONFIG_SPD_EEPROM.
112The i2c eeprom addresses are controlled by the SPD_EEPROM_ADDRESS macro.
113
114NOTE: The SPD_EEPROM_ADDRESS macro is defined differently than for other
115processors. Traditionally, it defined a single address. For the 440 it
116defines an array of addresses to support multiple banks. Address order
117is significant: the addresses are used in order to program the BankN
118registers. For example, two banks with i2c addresses of 0x53 (bank 0)
119and 0x52 (bank 1) would be defined as follows:
120
121#define SPD_EEPROM_ADDRESS {0x53,0x52}
122
123
124PCI-X BRIDGE
125====================
126
127PCI is an area that requires lots of flexibility since every board has
128its own set of constraints and configuration. This section describes the
129440 implementation.
130
131CPC0_STRP1[PISE] -- if the PISE strap bit is not asserted, PCI init
132is aborted and an indication is printed. This is NOT considered an
133error -- only an indication that PCI shouldn't be initialized. This
134gives you a chance to edit the i2c bootstrap eeproms using the i2c
135utilities once you get to the U-Boot command prompt. NOTE: the default
136440 bootstrap options (not using i2c eeprom) negates this bit.
137
138The cpu-specific code sets up a default pci_controller structure
139that maps in a single PCI I/O space and PCI memory space. The I/O
140space begins at PCI I/O address 0 and the PCI memory space is
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141256 MB starting at PCI address CONFIG_SYS_PCI_TARGBASE. After the
wdenkc6097192002-11-03 00:24:07 +0000142pci_controller structure is initialized, the cpu-specific code will
Stefan Roese466fff12007-06-25 15:57:39 +0200143call the routine pci_pre_init(). This routine is implemented by
144board-specific code & is where the board can over-ride/extend the
145default pci_controller structure settings and exspecially provide
146a routine to map the PCI interrupts and do other pre-initialization
147tasks. If pci_pre_init() returns a value of zero, PCI initialization
148is aborted; otherwise the controller structure is registered and
149initialization continues.
wdenkc6097192002-11-03 00:24:07 +0000150
151The default 440GP PCI target configuration is minimal -- it assumes that
152the strapping registers are set as necessary. Since the strapping bits
153provide very limited flexibility, you may want to customize the boards
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154target configuration. If CONFIG_SYS_PCI_TARGET_INIT is defined, the cpu-specific
wdenkc6097192002-11-03 00:24:07 +0000155code will call the routine pci_target_init() which you must implement
156in your board-specific code.
157
158Target initialization is completed by the cpu-specific code by
159initializing the subsystem id and subsystem vendor id, and then ensuring
160that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set.
161
162The default PCI master initialization maps in 256 MB of pci memory
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163starting at PCI address CONFIG_SYS_PCI_MEMBASE. To customize this, define
wdenkc6097192002-11-03 00:24:07 +0000164PCI_MASTER_INIT. This will call the routine pci_master_init() in your
165board-specific code rather than performing the default master
166initialization.
167
168The decision to perform PCI host configuration must often be determined
169at run time. The ppc440 port differs from most other implementations in
170that it requires the board to determine its host configuration at run
171time rather than by using compile-time flags. This shouldn't create a
172large impact on the board-specific code since the board only needs to
173implement a single routine that returns a zero or non-zero value:
174is_pci_host().
175
176Justification for this becomes clear when considering systems running
177in a cPCI environment:
178
1791. Arbiter strapping: Many cPCI boards provide an external arbiter (often
180part of the PCI-to-PCI bridge). Even though the arbiter is external (the
181arbiter strapping is negated), the CPU may still be required to perform
182local PCI bus configuration.
183
1842. Host only: PPMC boards must sample the MONARCH# signal at run-time.
185Depending on the configuration of the carrier boar, the PPMC board must
186determine if it should configure the PCI bus at run-time. And in most
187cases, access to the MONARCH# signal is board-specific (e.g. via
188board-specific FPGA registers, etc).
189
190In any event, the is_pci_host() routine gives each board the opportunity
191to decide at run-time. If your board is always configured a certain way,
192then just hardcode a return of 1 or 0 as appropriate.
193
194
wdenkc6097192002-11-03 00:24:07 +0000195Regards,
196--Scott
197<smcnutt@artesyncp.com>