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Kumar Gala129ba612008-08-12 11:13:08 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala129ba612008-08-12 11:13:08 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8572ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Kumar Gala509c4c42010-05-21 04:05:14 -050030#include "../board/freescale/common/ics307_clk.h"
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_36BIT
Kumar Galaf9edcc12009-09-10 16:23:45 -050033#define CONFIG_PHYS_64BIT
34#endif
35
Kumar Galacb14e932010-11-12 08:22:01 -060036#ifdef CONFIG_NAND
37#define CONFIG_NAND_U_BOOT
38#define CONFIG_RAMBOOT_NAND
39#ifdef CONFIG_NAND_SPL
40#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
42#else
Kumar Gala00203c62011-01-31 15:57:01 -060043#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
Kumar Galacb14e932010-11-12 08:22:01 -060044#define CONFIG_SYS_TEXT_BASE 0xf8f82000
45#endif /* CONFIG_NAND_SPL */
46#endif
47
48#ifndef CONFIG_SYS_TEXT_BASE
49#define CONFIG_SYS_TEXT_BASE 0xeff80000
50#endif
51
Kumar Gala7a577fd2011-01-12 02:48:53 -060052#ifndef CONFIG_RESET_VECTOR_ADDRESS
53#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
54#endif
55
Kumar Galacb14e932010-11-12 08:22:01 -060056#ifndef CONFIG_SYS_MONITOR_BASE
57#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
58#endif
59
Kumar Gala129ba612008-08-12 11:13:08 -050060/* High Level Configuration Options */
61#define CONFIG_BOOKE 1 /* BOOKE */
62#define CONFIG_E500 1 /* BOOKE e500 family */
63#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
64#define CONFIG_MPC8572 1
65#define CONFIG_MPC8572DS 1
66#define CONFIG_MP 1 /* support multiple processors */
Kumar Gala129ba612008-08-12 11:13:08 -050067
Kumar Galac51fc5d2009-01-23 14:22:13 -060068#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala129ba612008-08-12 11:13:08 -050069#define CONFIG_PCI 1 /* Enable PCI/PCIE */
70#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
71#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
72#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
73#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
74#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050075#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala129ba612008-08-12 11:13:08 -050076
77#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
78
79#define CONFIG_TSEC_ENET /* tsec ethernet support */
80#define CONFIG_ENV_OVERWRITE
81
Kumar Gala509c4c42010-05-21 04:05:14 -050082#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
83#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Haiying Wang4ca06602008-10-03 12:37:41 -040084#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala129ba612008-08-12 11:13:08 -050085
86/*
87 * These can be toggled for performance analysis, otherwise use default.
88 */
89#define CONFIG_L2_CACHE /* toggle L2 cache */
90#define CONFIG_BTB /* toggle branch predition */
Kumar Gala129ba612008-08-12 11:13:08 -050091
92#define CONFIG_ENABLE_36BIT_PHYS 1
93
Kumar Gala18af1c52009-01-23 14:22:14 -060094#ifdef CONFIG_PHYS_64BIT
95#define CONFIG_ADDR_MAP 1
96#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
97#endif
98
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
100#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala129ba612008-08-12 11:13:08 -0500101#define CONFIG_PANIC_HANG /* do not reset board on panic */
102
103/*
Kumar Galacb14e932010-11-12 08:22:01 -0600104 * Config the L2 Cache as L2 SRAM
105 */
106#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
107#ifdef CONFIG_PHYS_64BIT
108#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
109#else
110#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
111#endif
112#define CONFIG_SYS_L2_SIZE (512 << 10)
113#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
114
Timur Tabie46fedf2011-08-04 18:03:41 -0500115#define CONFIG_SYS_CCSRBAR 0xffe00000
116#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala129ba612008-08-12 11:13:08 -0500117
Kumar Gala8d22ddc2011-11-09 09:10:49 -0600118#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -0500119#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Kumar Galacb14e932010-11-12 08:22:01 -0600120#endif
121
Kumar Gala129ba612008-08-12 11:13:08 -0500122/* DDR Setup */
Kumar Galaf8523cb2009-02-06 09:56:35 -0600123#define CONFIG_VERY_BIG_RAM
Kumar Gala129ba612008-08-12 11:13:08 -0500124#define CONFIG_FSL_DDR2
125#undef CONFIG_FSL_DDR_INTERACTIVE
126#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
127#define CONFIG_DDR_SPD
Kumar Gala129ba612008-08-12 11:13:08 -0500128
York Sund34897d2011-01-25 21:51:29 -0800129#define CONFIG_DDR_ECC
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800130#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala129ba612008-08-12 11:13:08 -0500131#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
134#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala129ba612008-08-12 11:13:08 -0500135
136#define CONFIG_NUM_DDR_CONTROLLERS 2
137#define CONFIG_DIMM_SLOTS_PER_CTLR 1
138#define CONFIG_CHIP_SELECTS_PER_CTRL 2
139
140/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500142#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
143#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
144
145/* These are used when DDR doesn't use SPD. */
Dave Liudc889e82008-11-28 20:16:58 +0800146#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
147#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
148#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
149#define CONFIG_SYS_DDR_TIMING_3 0x00020000
150#define CONFIG_SYS_DDR_TIMING_0 0x00260802
151#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
152#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
153#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800155#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liudc889e82008-11-28 20:16:58 +0800157#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
158#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800160#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
161#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala129ba612008-08-12 11:13:08 -0500162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
164#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
165#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala129ba612008-08-12 11:13:08 -0500166
167/*
Kumar Gala129ba612008-08-12 11:13:08 -0500168 * Make sure required options are set
169 */
170#ifndef CONFIG_SPD_EEPROM
171#error ("CONFIG_SPD_EEPROM is required")
172#endif
173
174#undef CONFIG_CLOCKS_IN_MHZ
175
176/*
177 * Memory map
178 *
179 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
180 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
181 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
182 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
183 *
184 * Localbus cacheable (TBD)
185 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
186 *
187 * Localbus non-cacheable
188 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
189 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100190 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala129ba612008-08-12 11:13:08 -0500191 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
192 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
193 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
194 */
195
196/*
197 * Local Bus Definitions
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala18af1c52009-01-23 14:22:14 -0600200#ifdef CONFIG_PHYS_64BIT
201#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
202#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600203#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600204#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500205
Kumar Galacb14e932010-11-12 08:22:01 -0600206
207#define CONFIG_FLASH_BR_PRELIM \
208 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
209 | BR_PS_16 | BR_V)
210#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500211
Kumar Galac953ddf2008-12-02 14:19:34 -0600212#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
213#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500214
Kumar Gala18af1c52009-01-23 14:22:14 -0600215#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala129ba612008-08-12 11:13:08 -0500217#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
220#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
221#undef CONFIG_SYS_FLASH_CHECKSUM
222#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
223#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala129ba612008-08-12 11:13:08 -0500224
Kumar Galacb14e932010-11-12 08:22:01 -0600225#if defined(CONFIG_RAMBOOT_NAND)
226#define CONFIG_SYS_RAMBOOT
227#define CONFIG_SYS_EXTRA_ENV_RELOC
228#else
229#undef CONFIG_SYS_RAMBOOT
230#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500231
232#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_FLASH_CFI
234#define CONFIG_SYS_FLASH_EMPTY_INFO
235#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala129ba612008-08-12 11:13:08 -0500236
237#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
238
Kumar Gala558710b2010-11-19 08:53:25 -0600239#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala129ba612008-08-12 11:13:08 -0500240#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
241#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala18af1c52009-01-23 14:22:14 -0600242#ifdef CONFIG_PHYS_64BIT
243#define PIXIS_BASE_PHYS 0xfffdf0000ull
244#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600245#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600246#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500247
Kumar Gala52b565f2008-12-02 14:19:33 -0600248#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala129ba612008-08-12 11:13:08 -0500250
251#define PIXIS_ID 0x0 /* Board ID at offset 0 */
252#define PIXIS_VER 0x1 /* Board version at offset 1 */
253#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
254#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
255#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
256#define PIXIS_PWR 0x5 /* PIXIS Power status register */
257#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
258#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
259#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
260#define PIXIS_VCTL 0x10 /* VELA Control Register */
261#define PIXIS_VSTAT 0x11 /* VELA Status Register */
262#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
263#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
264#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
265#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500266#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
267#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
268#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
269#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
270#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500271#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
272#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
273#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
274#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
275#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
276#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
277#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
278#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
279#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
280#define PIXIS_VWATCH 0x24 /* Watchdog Register */
281#define PIXIS_LED 0x25 /* LED Register */
282
Kumar Galacb14e932010-11-12 08:22:01 -0600283#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
284
Kumar Gala129ba612008-08-12 11:13:08 -0500285/* old pixis referenced names */
286#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
287#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yu7e183ca2008-10-10 11:40:59 +0800289#define PIXIS_VSPEED2_TSEC1SER 0x8
290#define PIXIS_VSPEED2_TSEC2SER 0x4
291#define PIXIS_VSPEED2_TSEC3SER 0x2
292#define PIXIS_VSPEED2_TSEC4SER 0x1
293#define PIXIS_VCFGEN1_TSEC1SER 0x20
294#define PIXIS_VCFGEN1_TSEC2SER 0x20
295#define PIXIS_VCFGEN1_TSEC3SER 0x20
296#define PIXIS_VCFGEN1_TSEC4SER 0x20
297#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
298 | PIXIS_VSPEED2_TSEC2SER \
299 | PIXIS_VSPEED2_TSEC3SER \
300 | PIXIS_VSPEED2_TSEC4SER)
301#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
302 | PIXIS_VCFGEN1_TSEC2SER \
303 | PIXIS_VCFGEN1_TSEC3SER \
304 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala129ba612008-08-12 11:13:08 -0500305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_INIT_RAM_LOCK 1
307#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200308#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala129ba612008-08-12 11:13:08 -0500309
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200310#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
314#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala129ba612008-08-12 11:13:08 -0500315
Kumar Galacb14e932010-11-12 08:22:01 -0600316#ifndef CONFIG_NAND_SPL
Haiying Wangc013b742008-10-29 13:32:59 -0400317#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600318#ifdef CONFIG_PHYS_64BIT
319#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
320#else
Haiying Wangc013b742008-10-29 13:32:59 -0400321#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600322#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600323#else
324#define CONFIG_SYS_NAND_BASE 0xfff00000
325#ifdef CONFIG_PHYS_64BIT
326#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
327#else
328#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
329#endif
330#endif
331
Haiying Wangc013b742008-10-29 13:32:59 -0400332#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
333 CONFIG_SYS_NAND_BASE + 0x40000, \
334 CONFIG_SYS_NAND_BASE + 0x80000,\
335 CONFIG_SYS_NAND_BASE + 0xC0000}
336#define CONFIG_SYS_MAX_NAND_DEVICE 4
Haiying Wangc013b742008-10-29 13:32:59 -0400337#define CONFIG_MTD_NAND_VERIFY_WRITE
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100338#define CONFIG_CMD_NAND 1
339#define CONFIG_NAND_FSL_ELBC 1
Haiying Wangc013b742008-10-29 13:32:59 -0400340#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
341
Kumar Galacb14e932010-11-12 08:22:01 -0600342/* NAND boot: 4K NAND loader config */
343#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
344#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
345#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
346#define CONFIG_SYS_NAND_U_BOOT_START \
347 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
348#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
349#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
350#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
351
352
Haiying Wangc013b742008-10-29 13:32:59 -0400353/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500354#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100355 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
356 | BR_PS_8 /* Port Size = 8 bit */ \
357 | BR_MS_FCM /* MSEL = FCM */ \
358 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500359#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100360 | OR_FCM_PGS /* Large Page*/ \
361 | OR_FCM_CSCT \
362 | OR_FCM_CST \
363 | OR_FCM_CHT \
364 | OR_FCM_SCY_1 \
365 | OR_FCM_TRLX \
366 | OR_FCM_EHTR)
Haiying Wangc013b742008-10-29 13:32:59 -0400367
Kumar Galacb14e932010-11-12 08:22:01 -0600368#ifdef CONFIG_RAMBOOT_NAND
Matthew McClintocka3055c52011-04-05 14:39:33 -0500369#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
370#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Kumar Galacb14e932010-11-12 08:22:01 -0600371#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
372#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
373#else
374#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
375#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500376#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
377#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Kumar Galacb14e932010-11-12 08:22:01 -0600378#endif
Kumar Gala72a9414a2009-01-23 14:22:12 -0600379#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100380 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
381 | BR_PS_8 /* Port Size = 8 bit */ \
382 | BR_MS_FCM /* MSEL = FCM */ \
383 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500384#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Kumar Gala72a9414a2009-01-23 14:22:12 -0600385#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100386 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
387 | BR_PS_8 /* Port Size = 8 bit */ \
388 | BR_MS_FCM /* MSEL = FCM */ \
389 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500390#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400391
Kumar Gala72a9414a2009-01-23 14:22:12 -0600392#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100393 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
394 | BR_PS_8 /* Port Size = 8 bit */ \
395 | BR_MS_FCM /* MSEL = FCM */ \
396 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500397#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400398
399
Kumar Gala129ba612008-08-12 11:13:08 -0500400/* Serial Port - controlled on board with jumper J8
401 * open - index 2
402 * shorted - index 1
403 */
404#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_NS16550
406#define CONFIG_SYS_NS16550_SERIAL
407#define CONFIG_SYS_NS16550_REG_SIZE 1
408#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Galacb14e932010-11-12 08:22:01 -0600409#ifdef CONFIG_NAND_SPL
410#define CONFIG_NS16550_MIN_FUNCTIONS
411#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala129ba612008-08-12 11:13:08 -0500414 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
417#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala129ba612008-08-12 11:13:08 -0500418
419/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_HUSH_PARSER
421#ifdef CONFIG_SYS_HUSH_PARSER
422#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kumar Gala129ba612008-08-12 11:13:08 -0500423#endif
424
425/*
426 * Pass open firmware flat tree
427 */
428#define CONFIG_OF_LIBFDT 1
429#define CONFIG_OF_BOARD_SETUP 1
430#define CONFIG_OF_STDOUT_VIA_ALIAS 1
431
Kumar Gala129ba612008-08-12 11:13:08 -0500432/* new uImage format support */
433#define CONFIG_FIT 1
434#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
435
436/* I2C */
437#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
438#define CONFIG_HARD_I2C /* I2C with hardware support */
439#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Haiying Wang1f3ba312008-10-03 11:46:59 -0400440#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
442#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
443#define CONFIG_SYS_I2C_SLAVE 0x7F
444#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
445#define CONFIG_SYS_I2C_OFFSET 0x3000
446#define CONFIG_SYS_I2C2_OFFSET 0x3100
Kumar Gala129ba612008-08-12 11:13:08 -0500447
448/*
Haiying Wang445a7b32008-10-03 11:47:30 -0400449 * I2C2 EEPROM
450 */
451#define CONFIG_ID_EEPROM
452#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang445a7b32008-10-03 11:47:30 -0400454#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
456#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
457#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang445a7b32008-10-03 11:47:30 -0400458
459/*
Kumar Gala129ba612008-08-12 11:13:08 -0500460 * General PCI
461 * Memory space is mapped 1-1, but I/O space must start from 0.
462 */
463
Kumar Gala129ba612008-08-12 11:13:08 -0500464/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600465#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600466#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600467#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500468#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600469#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
470#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600471#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600472#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600473#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600475#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600476#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600477#ifdef CONFIG_PHYS_64BIT
478#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
479#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600481#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500483
484/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600485#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600486#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600487#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500488#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600489#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
490#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600491#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600492#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600493#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600495#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600496#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600497#ifdef CONFIG_PHYS_64BIT
498#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
499#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Gala18af1c52009-01-23 14:22:14 -0600501#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200502#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500503
504/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600505#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600506#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600507#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500508#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600509#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
510#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600511#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600512#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600513#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600515#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600516#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600517#ifdef CONFIG_PHYS_64BIT
518#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
519#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Gala18af1c52009-01-23 14:22:14 -0600521#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500523
524#if defined(CONFIG_PCI)
525
526/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600527#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala129ba612008-08-12 11:13:08 -0500528
529/* video */
530#define CONFIG_VIDEO
531
532#if defined(CONFIG_VIDEO)
533#define CONFIG_BIOSEMU
534#define CONFIG_CFB_CONSOLE
535#define CONFIG_VIDEO_SW_CURSOR
536#define CONFIG_VGA_AS_SINGLE_DEVICE
537#define CONFIG_ATI_RADEON_FB
538#define CONFIG_VIDEO_LOGO
539/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500541#endif
542
Kumar Gala129ba612008-08-12 11:13:08 -0500543#define CONFIG_PCI_PNP /* do pci plug-and-play */
544
545#undef CONFIG_EEPRO100
546#undef CONFIG_TULIP
547#undef CONFIG_RTL8139
Kumar Gala16855ec2010-11-09 23:19:50 -0600548#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Kumar Gala129ba612008-08-12 11:13:08 -0500549
Kumar Gala129ba612008-08-12 11:13:08 -0500550#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600551 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
552 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala129ba612008-08-12 11:13:08 -0500553 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
554#endif
555
556#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
557#define CONFIG_DOS_PARTITION
558#define CONFIG_SCSI_AHCI
559
560#ifdef CONFIG_SCSI_AHCI
561#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
563#define CONFIG_SYS_SCSI_MAX_LUN 1
564#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
565#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Kumar Gala129ba612008-08-12 11:13:08 -0500566#endif /* SCSI */
567
568#endif /* CONFIG_PCI */
569
570
571#if defined(CONFIG_TSEC_ENET)
572
Kumar Gala129ba612008-08-12 11:13:08 -0500573#define CONFIG_MII 1 /* MII PHY management */
574#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
575#define CONFIG_TSEC1 1
576#define CONFIG_TSEC1_NAME "eTSEC1"
577#define CONFIG_TSEC2 1
578#define CONFIG_TSEC2_NAME "eTSEC2"
579#define CONFIG_TSEC3 1
580#define CONFIG_TSEC3_NAME "eTSEC3"
581#define CONFIG_TSEC4 1
582#define CONFIG_TSEC4_NAME "eTSEC4"
583
Liu Yu7e183ca2008-10-10 11:40:59 +0800584#define CONFIG_PIXIS_SGMII_CMD
585#define CONFIG_FSL_SGMII_RISER 1
586#define SGMII_RISER_PHY_OFFSET 0x1c
587
588#ifdef CONFIG_FSL_SGMII_RISER
589#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
590#endif
591
Kumar Gala129ba612008-08-12 11:13:08 -0500592#define TSEC1_PHY_ADDR 0
593#define TSEC2_PHY_ADDR 1
594#define TSEC3_PHY_ADDR 2
595#define TSEC4_PHY_ADDR 3
596
597#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
598#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
599#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
600#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
601
602#define TSEC1_PHYIDX 0
603#define TSEC2_PHYIDX 0
604#define TSEC3_PHYIDX 0
605#define TSEC4_PHYIDX 0
606
607#define CONFIG_ETHPRIME "eTSEC1"
608
609#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
610#endif /* CONFIG_TSEC_ENET */
611
612/*
613 * Environment
614 */
Kumar Galacb14e932010-11-12 08:22:01 -0600615
616#if defined(CONFIG_SYS_RAMBOOT)
617#if defined(CONFIG_RAMBOOT_NAND)
618#define CONFIG_ENV_IS_IN_NAND 1
619#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
620#define CONFIG_ENV_OFFSET ((512 * 1024)\
621 + CONFIG_SYS_NAND_BLOCK_SIZE)
Kumar Gala129ba612008-08-12 11:13:08 -0500622#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600623
624#else
625 #define CONFIG_ENV_IS_IN_FLASH 1
626 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
627 #define CONFIG_ENV_ADDR 0xfff80000
628 #else
629 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
630 #endif
631 #define CONFIG_ENV_SIZE 0x2000
632 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
633#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500634
635#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200636#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala129ba612008-08-12 11:13:08 -0500637
638/*
639 * Command line configuration.
640 */
641#include <config_cmd_default.h>
642
York Sun67f94472011-01-26 00:14:57 -0600643#define CONFIG_CMD_ERRATA
Kumar Gala129ba612008-08-12 11:13:08 -0500644#define CONFIG_CMD_IRQ
645#define CONFIG_CMD_PING
646#define CONFIG_CMD_I2C
647#define CONFIG_CMD_MII
648#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500649#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500650#define CONFIG_CMD_REGINFO
Kumar Gala129ba612008-08-12 11:13:08 -0500651
652#if defined(CONFIG_PCI)
653#define CONFIG_CMD_PCI
Kumar Gala129ba612008-08-12 11:13:08 -0500654#define CONFIG_CMD_NET
655#define CONFIG_CMD_SCSI
656#define CONFIG_CMD_EXT2
657#endif
658
Zhao Chenhui863a3ea2011-03-04 16:31:41 +0800659/*
660 * USB
661 */
662#define CONFIG_USB_EHCI
663
664#ifdef CONFIG_USB_EHCI
665#define CONFIG_CMD_USB
666#define CONFIG_USB_EHCI_PCI
667#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
668#define CONFIG_USB_STORAGE
669#define CONFIG_PCI_EHCI_DEVICE 0
670#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
671#endif
672
Kumar Gala129ba612008-08-12 11:13:08 -0500673#undef CONFIG_WATCHDOG /* watchdog disabled */
674
675/*
676 * Miscellaneous configurable options
677 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200678#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500679#define CONFIG_CMDLINE_EDITING /* Command-line editing */
680#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200681#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
682#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kumar Gala129ba612008-08-12 11:13:08 -0500683#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200684#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500685#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200686#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500687#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200688#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
689#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
690#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
691#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kumar Gala129ba612008-08-12 11:13:08 -0500692
693/*
694 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500695 * have to be in the first 64 MB of memory, since this is
Kumar Gala129ba612008-08-12 11:13:08 -0500696 * the maximum mapped by the Linux kernel during initialization.
697 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500698#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
699#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala129ba612008-08-12 11:13:08 -0500700
Kumar Gala129ba612008-08-12 11:13:08 -0500701#if defined(CONFIG_CMD_KGDB)
702#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
703#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
704#endif
705
706/*
707 * Environment Configuration
708 */
709
710/* The mac addresses for all ethernet interface */
711#if defined(CONFIG_TSEC_ENET)
712#define CONFIG_HAS_ETH0
713#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
714#define CONFIG_HAS_ETH1
715#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
716#define CONFIG_HAS_ETH2
717#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
718#define CONFIG_HAS_ETH3
719#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
720#endif
721
722#define CONFIG_IPADDR 192.168.1.254
723
724#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000725#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000726#define CONFIG_BOOTFILE "uImage"
Kumar Gala129ba612008-08-12 11:13:08 -0500727#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
728
729#define CONFIG_SERVERIP 192.168.1.1
730#define CONFIG_GATEWAYIP 192.168.1.1
731#define CONFIG_NETMASK 255.255.255.0
732
733/* default location for tftp and bootm */
734#define CONFIG_LOADADDR 1000000
735
736#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
737#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
738
739#define CONFIG_BAUDRATE 115200
740
741#define CONFIG_EXTRA_ENV_SETTINGS \
Zhao Chenhui5103d7a2011-03-02 16:44:52 +0800742 "hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \
Kumar Gala129ba612008-08-12 11:13:08 -0500743 "netdev=eth0\0" \
744 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
745 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200746 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
747 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
748 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
749 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
750 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Kumar Gala129ba612008-08-12 11:13:08 -0500751 "consoledev=ttyS0\0" \
752 "ramdiskaddr=2000000\0" \
753 "ramdiskfile=8572ds/ramdisk.uboot\0" \
754 "fdtaddr=c00000\0" \
755 "fdtfile=8572ds/mpc8572ds.dtb\0" \
756 "bdev=sda3\0"
757
758#define CONFIG_HDBOOT \
759 "setenv bootargs root=/dev/$bdev rw " \
760 "console=$consoledev,$baudrate $othbootargs;" \
761 "tftp $loadaddr $bootfile;" \
762 "tftp $fdtaddr $fdtfile;" \
763 "bootm $loadaddr - $fdtaddr"
764
765#define CONFIG_NFSBOOTCOMMAND \
766 "setenv bootargs root=/dev/nfs rw " \
767 "nfsroot=$serverip:$rootpath " \
768 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
769 "console=$consoledev,$baudrate $othbootargs;" \
770 "tftp $loadaddr $bootfile;" \
771 "tftp $fdtaddr $fdtfile;" \
772 "bootm $loadaddr - $fdtaddr"
773
774#define CONFIG_RAMBOOTCOMMAND \
775 "setenv bootargs root=/dev/ram rw " \
776 "console=$consoledev,$baudrate $othbootargs;" \
777 "tftp $ramdiskaddr $ramdiskfile;" \
778 "tftp $loadaddr $bootfile;" \
779 "tftp $fdtaddr $fdtfile;" \
780 "bootm $loadaddr $ramdiskaddr $fdtaddr"
781
782#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
783
784#endif /* __CONFIG_H */