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wdenk2d39b712000-12-14 10:04:19 +00001/*
wdenk180d3f72004-01-04 16:28:35 +00002 * (C) Copyright 2000-2004
wdenk2d39b712000-12-14 10:04:19 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
wdenk180d3f72004-01-04 16:28:35 +00005 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
6 * and Dan Malek
7 *
8 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
9 *
10 * This header file contains values common to all FADS family boards.
11 *
wdenk2d39b712000-12-14 10:04:19 +000012 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31/****************************************************************************
wdenk180d3f72004-01-04 16:28:35 +000032 * Flash Memory Map as used by U-Boot:
wdenk2d39b712000-12-14 10:04:19 +000033 *
34 * Start Address Length
35 * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
wdenk180d3f72004-01-04 16:28:35 +000036 * | | 0xFE00_0100 Reset Vector
37 * + + 0xFE0?_????
38 * | U-Boot code |
39 * | |
40 * +-----------------------+ 0xFE04_0000 (sector border)
41 * | |
42 * | |
43 * | U-Boot environment |
44 * | | ^
45 * | | | U-Boot
46 * +=======================+ 0xFE08_0000 (sector border) -----------------
47 * | Available | | Applications
wdenk2d39b712000-12-14 10:04:19 +000048 * | ... | v
49 *
50 *****************************************************************************/
wdenk180d3f72004-01-04 16:28:35 +000051
52#if 0
53#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
54#else
55#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56#endif
57
Wolfgang Denk8ff02082006-03-12 01:55:43 +010058#define CONFIG_ENV_OVERWRITE
59
60#define CONFIG_NFSBOOTCOMMAND \
wdenk180d3f72004-01-04 16:28:35 +000061 "dhcp;" \
Wolfgang Denk8ff02082006-03-12 01:55:43 +010062 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
63 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
wdenk180d3f72004-01-04 16:28:35 +000064 "bootm"
65
Wolfgang Denk8ff02082006-03-12 01:55:43 +010066#define CONFIG_BOOTCOMMAND \
67 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
68 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
69 "bootm fe080000"
70
71#undef CONFIG_BOOTARGS
72
wdenk180d3f72004-01-04 16:28:35 +000073#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk11142572004-06-06 21:35:06 +000074#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
wdenk180d3f72004-01-04 16:28:35 +000075
76/*
Wolfgang Denk8ff02082006-03-12 01:55:43 +010077 * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
wdenk180d3f72004-01-04 16:28:35 +000078 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
79 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
80 * got FEC so FEC is the default.
81 */
82#ifndef CONFIG_ADS
83#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
84#define CONFIG_FEC_ENET /* Use FEC ethernet */
85#else /* Old ADS has not got FEC option */
86#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
87#undef CONFIG_FEC_ENET /* No FEC ethernet */
88#endif /* !CONFIG_ADS */
89
90#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
91#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
92#endif
93
94#ifdef CONFIG_FEC_ENET
95#define CFG_DISCOVER_PHY
96#endif
97
98#ifndef CONFIG_COMMANDS
wdenk11142572004-06-06 21:35:06 +000099#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100100 | CFG_CMD_ASKENV \
wdenk11142572004-06-06 21:35:06 +0000101 | CFG_CMD_DHCP \
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100102 | CFG_CMD_ECHO \
wdenk11142572004-06-06 21:35:06 +0000103 | CFG_CMD_IMMAP \
wdenk99edcfb2004-06-09 21:54:22 +0000104 | CFG_CMD_JFFS2 \
wdenk11142572004-06-06 21:35:06 +0000105 | CFG_CMD_MII \
106 | CFG_CMD_PCMCIA \
107 | CFG_CMD_PING \
wdenk180d3f72004-01-04 16:28:35 +0000108 )
109#endif /* !CONFIG_COMMANDS */
110
111/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
112#include <cmd_confdefs.h>
113
114/*
115 * Miscellaneous configurable options
116 */
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100117#define CFG_PROMPT "=>" /* Monitor Command Prompt */
118#define CFG_HUSH_PARSER
119#define CFG_PROMPT_HUSH_PS2 "> "
120#define CFG_LONGHELP /* #undef to save memory */
wdenk180d3f72004-01-04 16:28:35 +0000121#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100122#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk180d3f72004-01-04 16:28:35 +0000123#else
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100124#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk180d3f72004-01-04 16:28:35 +0000125#endif
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100126#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
127#define CFG_MAXARGS 16 /* max number of command args */
128#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
wdenk180d3f72004-01-04 16:28:35 +0000129
130#define CFG_LOAD_ADDR 0x00100000
131
132#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
133
134#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
135
136/*
137 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here.
140 */
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100141
wdenk180d3f72004-01-04 16:28:35 +0000142/*-----------------------------------------------------------------------
143 * Internal Memory Mapped Register
144 */
145#define CFG_IMMR 0xFF000000
146
147/*-----------------------------------------------------------------------
148 * Definitions for initial stack pointer and data area (in DPRAM)
149 */
150#define CFG_INIT_RAM_ADDR CFG_IMMR
151#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
152#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
153#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
154#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
155
156/*-----------------------------------------------------------------------
157 * Start addresses for the final memory configuration
158 * (Set up by the startup code)
159 * Please note that CFG_SDRAM_BASE _must_ start at 0
160 */
161#define CFG_SDRAM_BASE 0x00000000
wdenk11142572004-06-06 21:35:06 +0000162#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
wdenk180d3f72004-01-04 16:28:35 +0000163#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100164/*
165 * 2048 SDRAM rows
166 * 1000 factor s -> ms
167 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
168 * 4 Number of refresh cycles per period
169 * 64 Refresh cycle in ms per number of rows
170 */
171#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
wdenk180d3f72004-01-04 16:28:35 +0000172#elif defined(CONFIG_FADS) /* Old/new FADS */
173#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
174#else /* Old ADS */
175#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
176#endif
177
178#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
179#if (CFG_SDRAM_SIZE)
180#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
181#else
182#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
183#endif /* CFG_SDRAM_SIZE */
184
185/*
186 * For booting Linux, the board info and command line data
187 * have to be in the first 8 MB of memory, since this is
188 * the maximum mapped by the Linux kernel during initialization.
189 */
190#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk99edcfb2004-06-09 21:54:22 +0000191
192#define CFG_MONITOR_BASE TEXT_BASE
193#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
194
195#ifdef CONFIG_BZIP2
196#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
197#else
198#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
199#endif /* CONFIG_BZIP2 */
200
wdenk180d3f72004-01-04 16:28:35 +0000201/*-----------------------------------------------------------------------
202 * Flash organization
203 */
wdenk99edcfb2004-06-09 21:54:22 +0000204#define CFG_FLASH_BASE CFG_MONITOR_BASE
205#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
wdenk180d3f72004-01-04 16:28:35 +0000206
wdenk99edcfb2004-06-09 21:54:22 +0000207#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
208#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk180d3f72004-01-04 16:28:35 +0000209
210#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
211#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
212
213#define CFG_ENV_IS_IN_FLASH 1
214#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
215#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
216#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
217
wdenk99edcfb2004-06-09 21:54:22 +0000218#define CFG_DIRECT_FLASH_TFTP
wdenk11142572004-06-06 21:35:06 +0000219
wdenk99edcfb2004-06-09 21:54:22 +0000220#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200221
222/*
223 * JFFS2 partitions
224 *
225 */
226/* No command line, one static partition, whole device */
227#undef CONFIG_JFFS2_CMDLINE
228#define CONFIG_JFFS2_DEV "nor0"
229#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
230#define CONFIG_JFFS2_PART_OFFSET 0x00000000
231
232/* mtdparts command line support */
233/* Note: fake mtd_id used, no linux mtd map file */
234/*
235#define CONFIG_JFFS2_CMDLINE
236#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
237#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
238*/
239
wdenk99edcfb2004-06-09 21:54:22 +0000240#define CFG_JFFS2_SORT_FRAGMENTS
241#endif /* CFG_CMD_JFFS2 */
wdenk180d3f72004-01-04 16:28:35 +0000242
243/*-----------------------------------------------------------------------
244 * Cache Configuration
245 */
246#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
wdenk180d3f72004-01-04 16:28:35 +0000247#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk180d3f72004-01-04 16:28:35 +0000248
249/*-----------------------------------------------------------------------
250 * I2C configuration
251 */
252#if (CONFIG_COMMANDS & CFG_CMD_I2C)
253#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
254#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
255#define CFG_I2C_SLAVE 0x7F
256#endif
257
258/*-----------------------------------------------------------------------
259 * SYPCR - System Protection Control 11-9
260 * SYPCR can only be written once after reset!
261 *-----------------------------------------------------------------------
262 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
263 */
264#if defined(CONFIG_WATCHDOG)
265#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
266 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
267#else
268#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
269#endif
270
271/*-----------------------------------------------------------------------
272 * SIUMCR - SIU Module Configuration 11-6
273 *-----------------------------------------------------------------------
274 * PCMCIA config., multi-function pin tri-state
275 */
276#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
277
278/*-----------------------------------------------------------------------
279 * TBSCR - Time Base Status and Control 11-26
280 *-----------------------------------------------------------------------
281 * Clear Reference Interrupt Status, Timebase freezing enabled
282 */
283#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
284
285/*-----------------------------------------------------------------------
286 * PISCR - Periodic Interrupt Status and Control 11-31
287 *-----------------------------------------------------------------------
288 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
289 */
290#define CFG_PISCR (PISCR_PS | PISCR_PITF)
291
292/*-----------------------------------------------------------------------
293 * SCCR - System Clock and reset Control Register 15-27
294 *-----------------------------------------------------------------------
295 * Set clock output, timebase and RTC source and divider,
296 * power management and some other internal clocks
297 */
298#define SCCR_MASK SCCR_EBDF11
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100299#define CFG_SCCR SCCR_TBS
wdenk180d3f72004-01-04 16:28:35 +0000300
wdenk11142572004-06-06 21:35:06 +0000301/*-----------------------------------------------------------------------
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100302 * DER - Debug Enable Register
wdenk11142572004-06-06 21:35:06 +0000303 *-----------------------------------------------------------------------
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100304 * Set to zero to prevent the processor from entering debug mode
wdenk180d3f72004-01-04 16:28:35 +0000305 */
306#define CFG_DER 0
307
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100308/* Because of the way the 860 starts up and assigns CS0 the entire
309 * address space, we have to set the memory controller differently.
310 * Normally, you write the option register first, and then enable the
311 * chip select by writing the base register. For CS0, you must write
312 * the base register first, followed by the option register.
313 */
wdenk180d3f72004-01-04 16:28:35 +0000314
315/*
316 * Init Memory Controller:
317 *
318 * BR0/OR0 (Flash)
319 * BR1/OR1 (BCSR)
320 */
321/* the other CS:s are determined by looking at parameters in BCSRx */
322
323#define BCSR_ADDR ((uint) 0xFF080000)
324
325#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
326
327/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
328#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
329
330#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
331#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
332
333/* BCSRx - Board Control and Status Registers */
334#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
335#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V)
336
337/*
338 * Internal Definitions
339 *
340 * Boot Flags
341 */
342#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
343#define BOOTFLAG_WARM 0x02 /* Software reboot */
344
345/* values according to the manual */
346
wdenk180d3f72004-01-04 16:28:35 +0000347#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
348#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
349#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
350#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
351#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
352
353/*
354 * (F)ADS bitvalues by Helmut Buchsbaum
355 *
356 * See User's Manual for a proper
357 * description of the following structures
358 */
359
360#define BCSR0_ERB ((uint)0x80000000)
361#define BCSR0_IP ((uint)0x40000000)
362#define BCSR0_BDIS ((uint)0x10000000)
363#define BCSR0_BPS_MASK ((uint)0x0C000000)
364#define BCSR0_ISB_MASK ((uint)0x01800000)
365#define BCSR0_DBGC_MASK ((uint)0x00600000)
366#define BCSR0_DBPC_MASK ((uint)0x00180000)
367#define BCSR0_EBDF_MASK ((uint)0x00060000)
368
369#define BCSR1_FLASH_EN ((uint)0x80000000)
370#define BCSR1_DRAM_EN ((uint)0x40000000)
371#define BCSR1_ETHEN ((uint)0x20000000)
372#define BCSR1_IRDEN ((uint)0x10000000)
373#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
374#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
375#define BCSR1_BCSR_EN ((uint)0x02000000)
376#define BCSR1_RS232EN_1 ((uint)0x01000000)
377#define BCSR1_PCCEN ((uint)0x00800000)
378#define BCSR1_PCCVCC0 ((uint)0x00400000)
379#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
380#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
381#define BCSR1_RS232EN_2 ((uint)0x00040000)
382#define BCSR1_SDRAM_EN ((uint)0x00020000)
383#define BCSR1_PCCVCC1 ((uint)0x00010000)
384
385#define BCSR1_PCCVCCON BCSR1_PCCVCC0
386
387#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenk99edcfb2004-06-09 21:54:22 +0000388#define BCSR2_FLASH_PD_SHIFT 28
wdenk180d3f72004-01-04 16:28:35 +0000389#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
390#define BCSR2_DRAM_PD_SHIFT 23
391#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
392#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
393
394#define BCSR3_DBID_MASK ((ushort)0x3800)
395#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
396#define BCSR3_BREVNR0 ((ushort)0x0080)
397#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
398#define BCSR3_BREVN1 ((ushort)0x0008)
399#define BCSR3_BREVN2_MASK ((ushort)0x0003)
400
401#define BCSR4_ETHLOOP ((uint)0x80000000)
402#define BCSR4_TFPLDL ((uint)0x40000000)
403#define BCSR4_TPSQEL ((uint)0x20000000)
404#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100405#if defined(CONFIG_MPC823)
wdenk180d3f72004-01-04 16:28:35 +0000406#define BCSR4_USB_EN ((uint)0x08000000)
wdenk180d3f72004-01-04 16:28:35 +0000407#define BCSR4_USB_SPEED ((uint)0x04000000)
wdenk180d3f72004-01-04 16:28:35 +0000408#define BCSR4_VCCO ((uint)0x02000000)
wdenk180d3f72004-01-04 16:28:35 +0000409#define BCSR4_VIDEO_ON ((uint)0x00800000)
wdenk180d3f72004-01-04 16:28:35 +0000410#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
wdenk180d3f72004-01-04 16:28:35 +0000411#define BCSR4_VIDEO_RST ((uint)0x00200000)
wdenk180d3f72004-01-04 16:28:35 +0000412#define BCSR4_MODEM_EN ((uint)0x00100000)
wdenk180d3f72004-01-04 16:28:35 +0000413#define BCSR4_DATA_VOICE ((uint)0x00080000)
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100414#elif defined(CONFIG_MPC850)
wdenk180d3f72004-01-04 16:28:35 +0000415#define BCSR4_DATA_VOICE ((uint)0x00080000)
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100416#elif defined(CONFIG_MPC860SAR)
417#define BCSR4_UTOPIA_EN ((uint)0x08000000)
418#else /* MPC860T and other chips with FEC */
419#define BCSR4_FETH_EN ((uint)0x08000000)
420#define BCSR4_FETHCFG0 ((uint)0x04000000)
421#define BCSR4_FETHFDE ((uint)0x02000000)
422#define BCSR4_FETHCFG1 ((uint)0x00400000)
423#define BCSR4_FETHRST ((uint)0x00200000)
424#endif
wdenk180d3f72004-01-04 16:28:35 +0000425
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100426/* BSCR5 exists on MPC86xADS and MPC885ADS only */
wdenk11142572004-06-06 21:35:06 +0000427
428#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
429
430#define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
431
432#define BCSR5_MII2_EN 0x40
433#define BCSR5_MII2_RST 0x20
434#define BCSR5_T1_RST 0x10
435#define BCSR5_ATM155_RST 0x08
436#define BCSR5_ATM25_RST 0x04
437#define BCSR5_MII1_EN 0x02
438#define BCSR5_MII1_RST 0x01
439
wdenk180d3f72004-01-04 16:28:35 +0000440/* We don't use the 8259.
441*/
442#define NR_8259_INTS 0
443
444/* Machine type
445*/
446#define _MACH_8xx (_MACH_fads)
447
448/*-----------------------------------------------------------------------
449 * PCMCIA stuff
450 *-----------------------------------------------------------------------
451 */
wdenk180d3f72004-01-04 16:28:35 +0000452#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
453#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
454#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
455#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
456#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
457#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
458#define CFG_PCMCIA_IO_ADDR (0xEC000000)
459#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
460
461/*-----------------------------------------------------------------------
462 * IDE/ATA stuff
463 *-----------------------------------------------------------------------
464 */
465#define CONFIG_MAC_PARTITION 1
466#define CONFIG_DOS_PARTITION 1
467#define CONFIG_ISO_PARTITION 1
468
469#undef CONFIG_ATAPI
470#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
471#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
472#undef CONFIG_IDE_LED /* LED for ide not supported */
473#undef CONFIG_IDE_RESET /* reset for ide not supported */
474
475#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
476#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
477
478#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
479#define CFG_ATA_IDE0_OFFSET 0x0000
480
481/* Offset for data I/O */
482#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
483/* Offset for normal register accesses */
484#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
485/* Offset for alternate registers */
486#define CFG_ATA_ALT_OFFSET 0x0000
487
488#define CONFIG_DISK_SPINUP_TIME 1000000
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100489/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */