blob: b5a19e4a864c5be908a566349b157f929bd529a0 [file] [log] [blame]
Ilya Yanokbc8f8c22010-09-17 23:41:50 +02001/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4 *
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/*
29 * High Level Configuration Options
30 */
31#define CONFIG_E300 1 /* E300 family */
32#define CONFIG_MPC83xx 1 /* MPC83xx family */
33#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
34#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */
35
36/*
37 * On-board devices
38 *
39 * TSECs
40 */
41#define CONFIG_TSEC1
42#define CONFIG_TSEC2
43
44/*
45 * System Clock Setup
46 */
47#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
48#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
49
50/*
51 * Hardware Reset Configuration Word
52 * if CLKIN is 66.66MHz, then
53 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
54 * We choose the A type silicon as default, so the core is 400Mhz.
55 */
56#define CONFIG_SYS_HRCW_LOW (\
57 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
58 HRCWL_DDR_TO_SCB_CLK_2X1 |\
59 HRCWL_SVCOD_DIV_2 |\
60 HRCWL_CSB_TO_CLKIN_4X1 |\
61 HRCWL_CORE_TO_CSB_3X1)
62/*
63 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
64 * in 8308's HRCWH according to the manual, but original Freescale's
65 * code has them and I've expirienced some problems using the board
66 * with BDI3000 attached when I've tried to set these bits to zero
67 * (UART doesn't work after the 'reset run' command).
68 */
69#define CONFIG_SYS_HRCW_HIGH (\
70 HRCWH_PCI_HOST |\
71 HRCWH_PCI1_ARBITER_ENABLE |\
72 HRCWH_CORE_ENABLE |\
73 HRCWH_FROM_0X00000100 |\
74 HRCWH_BOOTSEQ_DISABLE |\
75 HRCWH_SW_WATCHDOG_DISABLE |\
76 HRCWH_ROM_LOC_LOCAL_16BIT |\
77 HRCWH_RL_EXT_LEGACY |\
78 HRCWH_TSEC1M_IN_MII |\
79 HRCWH_TSEC2M_IN_MII |\
80 HRCWH_BIG_ENDIAN)
81
82/*
83 * System IO Config
84 */
85#define CONFIG_SYS_SICRH (\
86 SICRH_ESDHC_A_GPIO |\
87 SICRH_ESDHC_B_GPIO |\
88 SICRH_ESDHC_C_GTM |\
89 SICRH_GPIO_A_TSEC2 |\
90 SICRH_GPIO_B_TSEC2_TX_CLK |\
91 SICRH_IEEE1588_A_GPIO |\
92 SICRH_USB |\
93 SICRH_GTM_GPIO |\
94 SICRH_IEEE1588_B_GPIO |\
95 SICRH_ETSEC2_CRS |\
96 SICRH_GPIOSEL_1 |\
97 SICRH_TMROBI_V3P3 |\
98 SICRH_TSOBI1_V3P3 |\
99 SICRH_TSOBI2_V3P3) /* 0xf577d100 */
100#define CONFIG_SYS_SICRL (\
101 SICRL_SPI_PF0 |\
102 SICRL_UART_PF0 |\
103 SICRL_IRQ_PF0 |\
104 SICRL_I2C2_PF0 |\
105 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
106
107#define CONFIG_SYS_GPIO1_PRELIM
108/* GPIO Default input/output settings */
109#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
110/*
111 * Default GPIO values:
112 * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
113 */
114#define CONFIG_SYS_GPIO1_DAT 0x08008C00
115
116/*
117 * IMMR new address
118 */
119#define CONFIG_SYS_IMMR 0xE0000000
120
121/*
122 * SERDES
123 */
124#define CONFIG_FSL_SERDES
125#define CONFIG_FSL_SERDES1 0xe3000
126
127/*
128 * Arbiter Setup
129 */
130#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
131#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
132#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
133
134/*
135 * DDR Setup
136 */
137#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
138#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
139#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
140#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
141#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
142 | DDRCDR_PZ_LOZ \
143 | DDRCDR_NZ_LOZ \
144 | DDRCDR_ODT \
145 | DDRCDR_Q_DRN)
146 /* 0x7b880001 */
147/*
148 * Manually set up DDR parameters
149 * consist of two chips HY5PS12621BFP-C4 from HYNIX
150 */
151
152#define CONFIG_SYS_DDR_SIZE 128 /* MB */
153
154#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
155#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
156 | 0x00010000 /* ODT_WR to CSn */ \
157 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
158 /* 0x80010102 */
159#define CONFIG_SYS_DDR_TIMING_3 0x00000000
160#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
161 | (0 << TIMING_CFG0_WRT_SHIFT) \
162 | (0 << TIMING_CFG0_RRT_SHIFT) \
163 | (0 << TIMING_CFG0_WWT_SHIFT) \
164 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
165 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
166 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
167 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
168 /* 0x00220802 */
169#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
170 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
171 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
172 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
173 | (6 << TIMING_CFG1_REFREC_SHIFT) \
174 | (2 << TIMING_CFG1_WRREC_SHIFT) \
175 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
176 | (2 << TIMING_CFG1_WRTORD_SHIFT))
177 /* 0x27256222 */
178#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
179 | (4 << TIMING_CFG2_CPO_SHIFT) \
180 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
181 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
182 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
183 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
184 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
185 /* 0x121048c5 */
186#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
187 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
188 /* 0x03600100 */
189#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
190 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
191 | SDRAM_CFG_32_BE)
192 /* 0x43080000 */
193
194#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
195#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
196 | (0x0232 << SDRAM_MODE_SD_SHIFT))
197 /* ODT 150ohm CL=3, AL=1 on SDRAM */
198#define CONFIG_SYS_DDR_MODE2 0x00000000
199
200/*
201 * Memory test
202 */
203#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
204#define CONFIG_SYS_MEMTEST_END 0x07f00000
205
206/*
207 * The reserved memory
208 */
209#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
210
211#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
212#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
213
214/*
215 * Initial RAM Base Address Setup
216 */
217#define CONFIG_SYS_INIT_RAM_LOCK 1
218#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
219#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
220#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
221#define CONFIG_SYS_GBL_DATA_OFFSET \
222 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
223
224/*
225 * Local Bus Configuration & Clock Setup
226 */
227#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
228#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
229#define CONFIG_SYS_LBC_LBCR 0x00040000
230
231/*
232 * FLASH on the Local Bus
233 */
234#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
235#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
236#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
237
238#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
239#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
240#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
241
242/* Window base at flash base */
243#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
244#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
245
246#define CONFIG_SYS_BR0_PRELIM (\
247 CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
248 (2 << BR_PS_SHIFT) /* 16 bit port size */ |\
249 BR_V) /* valid */
250#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
251 | OR_UPM_XAM \
252 | OR_GPCM_CSNT \
253 | OR_GPCM_ACS_DIV2 \
254 | OR_GPCM_XACS \
255 | OR_GPCM_SCY_4 \
256 | OR_GPCM_TRLX \
257 | OR_GPCM_EHTR \
258 | OR_GPCM_EAD)
259
260#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
261#define CONFIG_SYS_MAX_FLASH_SECT 512
262
263/* Flash Erase Timeout (ms) */
264#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024)
265/* Flash Write Timeout (ms) */
266#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
267
268/*
269 * SJA1000 CAN controller on Local Bus
270 */
271#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
272#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_SJA1000_BASE \
273 | (1 << BR_PS_SHIFT) /* 8 bit port size */ \
274 | BR_V ) /* valid */
275#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
276 | OR_GPCM_SCY_5 \
277 | OR_GPCM_EHTR)
278 /* 0xFFFF8052 */
279
280#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
281#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
282
283/*
284 * CPLD on Local Bus
285 */
286#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
287#define CONFIG_SYS_BR2_PRELIM ( CONFIG_SYS_CPLD_BASE \
288 | (1 << BR_PS_SHIFT) /* 8 bit port size */ \
289 | BR_V ) /* valid */
290#define CONFIG_SYS_OR2_PRELIM ( 0xFFFF8000 /* length 32K */ \
291 | OR_GPCM_SCY_4 \
292 | OR_GPCM_EHTR)
293 /* 0xFFFF8042 */
294
295#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
296#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
297
298/*
299 * Serial Port
300 */
301#define CONFIG_CONS_INDEX 1
302#undef CONFIG_SERIAL_SOFTWARE_FIFO
303#define CONFIG_SYS_NS16550
304#define CONFIG_SYS_NS16550_SERIAL
305#define CONFIG_SYS_NS16550_REG_SIZE 1
306#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
307
308#define CONFIG_SYS_BAUDRATE_TABLE \
309 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
310
311#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
312#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
313
314/* Use the HUSH parser */
315#define CONFIG_SYS_HUSH_PARSER
316#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
317
318/* Pass open firmware flat tree */
319#define CONFIG_OF_LIBFDT 1
320#define CONFIG_OF_BOARD_SETUP 1
321#define CONFIG_OF_STDOUT_VIA_ALIAS 1
322
323/* I2C */
324#define CONFIG_HARD_I2C /* I2C with hardware support */
325#define CONFIG_FSL_I2C
326#define CONFIG_I2C_MULTI_BUS
327#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
328#define CONFIG_SYS_I2C_SLAVE 0x7F
329#define CONFIG_SYS_I2C_OFFSET 0x3000
330#define CONFIG_SYS_I2C2_OFFSET 0x3100
331
332/*
333 * General PCI
334 * Addresses are mapped 1-1.
335 */
336#define CONFIG_SYS_PCIE1_BASE 0xA0000000
337#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
338#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
339#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
340#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
341#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
342#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
343#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
344#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
345
346/* enable PCIE clock */
347#define CONFIG_SYS_SCCR_PCIEXP1CM 1
348
349#define CONFIG_PCI
350#define CONFIG_PCIE
351
352#define CONFIG_PCI_PNP /* do pci plug-and-play */
353
354#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
355#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
356
357/*
358 * TSEC
359 */
360#define CONFIG_NET_MULTI
361#define CONFIG_TSEC_ENET /* TSEC ethernet support */
362#define CONFIG_SYS_TSEC1_OFFSET 0x24000
363#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
364#define CONFIG_SYS_TSEC2_OFFSET 0x25000
365#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
366
367/*
368 * TSEC ethernet configuration
369 */
370#define CONFIG_MII 1 /* MII PHY management */
371#define CONFIG_TSEC1_NAME "eTSEC0"
372#define CONFIG_TSEC2_NAME "eTSEC1"
373#define TSEC1_PHY_ADDR 1
374#define TSEC2_PHY_ADDR 2
375#define TSEC1_PHYIDX 0
376#define TSEC2_PHYIDX 0
377#define TSEC1_FLAGS 0
378#define TSEC2_FLAGS 0
379
380/* Options are: eTSEC[0-1] */
381#define CONFIG_ETHPRIME "eTSEC0"
382
383/*
384 * Environment
385 */
386#define CONFIG_ENV_IS_IN_FLASH 1
387#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
388 CONFIG_SYS_MONITOR_LEN)
389#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
390#define CONFIG_ENV_SIZE 0x2000
391#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
392#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
393
394#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
395#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
396
397/*
398 * BOOTP options
399 */
400#define CONFIG_BOOTP_BOOTFILESIZE
401#define CONFIG_BOOTP_BOOTPATH
402#define CONFIG_BOOTP_GATEWAY
403#define CONFIG_BOOTP_HOSTNAME
404
405/*
406 * Command line configuration.
407 */
408#include <config_cmd_default.h>
409
410#define CONFIG_CMD_DHCP
411#define CONFIG_CMD_I2C
412#define CONFIG_CMD_MII
413#define CONFIG_CMD_NET
414#define CONFIG_CMD_PCI
415#define CONFIG_CMD_PING
416
417#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
418
419/*
420 * Miscellaneous configurable options
421 */
422#define CONFIG_SYS_LONGHELP /* undef to save memory */
423#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
424#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
425
426#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
427
428/* Print Buffer Size */
429#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
430#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
431/* Boot Argument Buffer Size */
432#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
433#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
434
435/*
436 * For booting Linux, the board info and command line data
437 * have to be in the first 8 MB of memory, since this is
438 * the maximum mapped by the Linux kernel during initialization.
439 */
Kim Phillips9eda7702010-09-22 15:36:27 -0500440#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Ilya Yanokbc8f8c22010-09-17 23:41:50 +0200441
442/*
443 * Core HID Setup
444 */
445#define CONFIG_SYS_HID0_INIT 0x000000000
446#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
447 HID0_ENABLE_INSTRUCTION_CACHE | \
448 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
449#define CONFIG_SYS_HID2 HID2_HBE
450
451/*
452 * MMU Setup
453 */
454
455/* DDR: cache cacheable */
456#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
457 BATL_MEMCOHERENCE)
458#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
459 BATU_VS | BATU_VP)
460#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
461#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
462
463/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
464#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
465 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
466#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
467 BATU_VP)
468#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
469#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
470
471/* FLASH: icache cacheable, but dcache-inhibit and guarded */
472#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
473 BATL_MEMCOHERENCE)
474#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
475 BATU_VS | BATU_VP)
476#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
477 BATL_CACHEINHIBIT | \
478 BATL_GUARDEDSTORAGE)
479#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
480
481/* Stack in dcache: cacheable, no memory coherence */
482#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
483#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
484 BATU_VS | BATU_VP)
485#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
486#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
487
488/*
489 * Internal Definitions
490 *
491 * Boot Flags
492 */
493#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
494#define BOOTFLAG_WARM 0x02 /* Software reboot */
495
496/*
497 * Environment Configuration
498 */
499
500#define CONFIG_ENV_OVERWRITE
501
502#if defined(CONFIG_TSEC_ENET)
503#define CONFIG_HAS_ETH0
504#define CONFIG_HAS_ETH1
505#endif
506
507#define CONFIG_BAUDRATE 115200
508
509#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
510
511#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
512
513#define xstr(s) str(s)
514#define str(s) #s
515
516#define CONFIG_EXTRA_ENV_SETTINGS \
517 "netdev=eth0\0" \
518 "consoledev=ttyS0\0" \
519 "nfsargs=setenv bootargs root=/dev/nfs rw " \
520 "nfsroot=${serverip}:${rootpath}\0" \
521 "ramargs=setenv bootargs root=/dev/ram rw\0" \
522 "addip=setenv bootargs ${bootargs} " \
523 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
524 ":${hostname}:${netdev}:off panic=1\0" \
525 "addtty=setenv bootargs ${bootargs}" \
526 " console=${consoledev},${baudrate}\0" \
527 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
528 "addmisc=setenv bootargs ${bootargs}\0" \
529 "kernel_addr=FC0A0000\0" \
530 "fdt_addr=FC2A0000\0" \
531 "ramdisk_addr=FC2C0000\0" \
532 "u-boot=mpc8308_p1m/u-boot.bin\0" \
533 "kernel_addr_r=1000000\0" \
534 "fdt_addr_r=C00000\0" \
535 "hostname=mpc8308_p1m\0" \
536 "bootfile=mpc8308_p1m/uImage\0" \
537 "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \
538 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
539 "flash_self=run ramargs addip addtty addmtd addmisc;" \
540 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
541 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
542 "bootm ${kernel_addr} - ${fdt_addr}\0" \
543 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
544 "tftp ${fdt_addr_r} ${fdtfile};" \
545 "run nfsargs addip addtty addmtd addmisc;" \
546 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
547 "bootcmd=run flash_self\0" \
548 "load=tftp ${loadaddr} ${u-boot}\0" \
549 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
550 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
551 " +${filesize};cp.b ${fileaddr} " \
552 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
553 "upd=run load update\0" \
554
555#endif /* __CONFIG_H */