blob: 68a91a6b5a38264d3e58f4ab7acc77352573651a [file] [log] [blame]
Mike Frysinger7577aab2010-12-17 15:28:43 -05001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for BF506F EZ-Kit board
Mike Frysinger7577aab2010-12-17 15:28:43 -05003 */
4
5#ifndef __CONFIG_BF506F_EZKIT_H__
6#define __CONFIG_BF506F_EZKIT_H__
7
8#include <asm/config-pre.h>
9
10
11/*
12 * Processor Settings
13 */
14#define CONFIG_BFIN_CPU bf506-0.0
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 16
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_SIZE 0
46
47#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
48#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
49#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
50
51#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END)
52#define CONFIG_SYS_MONITOR_LEN (4 * 1024)
53#define CONFIG_SYS_MALLOC_LEN (4 * 1024)
54
55
56/*
57 * Flash Settings
58 */
Sonic Zhangc49eabe2014-07-17 19:00:29 +080059/*
Mike Frysinger7577aab2010-12-17 15:28:43 -050060#define CONFIG_FLASH_CFI_DRIVER
61#define CONFIG_SYS_FLASH_BASE 0x20000000
62#define CONFIG_SYS_FLASH_CFI
63#define CONFIG_SYS_MAX_FLASH_BANKS 1
64#define CONFIG_SYS_MAX_FLASH_SECT 71
Mike Frysingera91eb2c2011-01-10 00:19:47 -050065#define CONFIG_MONITOR_IS_IN_RAM
Sonic Zhanga2d16902013-12-09 12:38:56 +080066*/
Sonic Zhangc49eabe2014-07-17 19:00:29 +080067#define CONFIG_SYS_NO_FLASH
Mike Frysinger7577aab2010-12-17 15:28:43 -050068
69/*
70 * SPI Settings
71 */
72#define CONFIG_BFIN_SPI
73#define CONFIG_ENV_SPI_MAX_HZ 30000000
74#define CONFIG_SF_DEFAULT_SPEED 30000000
Sonic Zhanga2d16902013-12-09 12:38:56 +080075/*
Mike Frysinger7577aab2010-12-17 15:28:43 -050076#define CONFIG_CMD_SF
77#define CONFIG_CMD_SPI
Sonic Zhanga2d16902013-12-09 12:38:56 +080078*/
Mike Frysinger7577aab2010-12-17 15:28:43 -050079
80/*
81 * Env Storage Settings
82 */
83#define CONFIG_ENV_IS_NOWHERE
84#define CONFIG_ENV_SIZE 0x400
Mike Frysinger7577aab2010-12-17 15:28:43 -050085
86
87/*
88 * Misc Settings
89 */
90#define CONFIG_BOARD_EARLY_INIT_F
91#define CONFIG_ICACHE_OFF
92#define CONFIG_DCACHE_OFF
93#define CONFIG_UART_CONSOLE 0
94#define CONFIG_BAUDRATE 115200
Sonic Zhang7a58eb92013-11-18 14:50:19 +080095#define CONFIG_BFIN_SERIAL
Mike Frysinger7577aab2010-12-17 15:28:43 -050096
Mike Frysinger7577aab2010-12-17 15:28:43 -050097#undef CONFIG_GZIP
98#undef CONFIG_ZLIB
Mike Frysinger7577aab2010-12-17 15:28:43 -050099#undef CONFIG_BOOTM_RTEMS
100#undef CONFIG_BOOTM_LINUX
101
102#endif