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Mingkai Huf3a8e2b2015-10-26 19:47:52 +08001/*
2 * Copyright (C) 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1043A_COMMON_H
8#define __LS1043A_COMMON_H
9
10#define CONFIG_REMAKE_ELF
11#define CONFIG_FSL_LAYERSCAPE
12#define CONFIG_FSL_LSCH2
13#define CONFIG_LS1043A
Hou Zhiqiang831c0682015-10-26 19:47:57 +080014#define CONFIG_MP
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080015#define CONFIG_SYS_FSL_CLK
16#define CONFIG_GICV2
17
18#include <asm/arch/config.h>
19#ifdef CONFIG_SYS_FSL_SRDS_1
20#define CONFIG_SYS_HAS_SERDES
21#endif
22
23/* Link Definitions */
24#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
25
26#define CONFIG_SUPPORT_RAW_INITRD
27
28#define CONFIG_SKIP_LOWLEVEL_INIT
29#define CONFIG_BOARD_EARLY_INIT_F 1
30
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080031#ifndef CONFIG_SYS_FSL_DDR4
32#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
33#endif
34
35#define CONFIG_VERY_BIG_RAM
36#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
37#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
38#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shaohui Xiee994ddd2015-11-23 15:23:48 +080039#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080040
Hou Zhiqiang831c0682015-10-26 19:47:57 +080041#define CPU_RELEASE_ADDR secondary_boot_func
42
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080043/* Generic Timer Definitions */
44#define COUNTER_FREQUENCY 25000000 /* 25MHz */
45
46/* Size of malloc() pool */
47#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
48
49/* Serial Port */
50#define CONFIG_CONS_INDEX 1
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080051#define CONFIG_SYS_NS16550_SERIAL
52#define CONFIG_SYS_NS16550_REG_SIZE 1
53#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
54
55#define CONFIG_BAUDRATE 115200
56#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
57
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080058/* SD boot SPL */
59#ifdef CONFIG_SD_BOOT
60#define CONFIG_SPL_FRAMEWORK
61#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
62#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
63#define CONFIG_SPL_LIBCOMMON_SUPPORT
64#define CONFIG_SPL_LIBGENERIC_SUPPORT
65#define CONFIG_SPL_ENV_SUPPORT
66#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
67#define CONFIG_SPL_WATCHDOG_SUPPORT
68#define CONFIG_SPL_I2C_SUPPORT
69#define CONFIG_SPL_SERIAL_SUPPORT
70#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
71#define CONFIG_SPL_MMC_SUPPORT
72#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0
73#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500
74
75#define CONFIG_SPL_TEXT_BASE 0x10000000
76#define CONFIG_SPL_MAX_SIZE 0x1d000
77#define CONFIG_SPL_STACK 0x1001e000
78#define CONFIG_SPL_PAD_TO 0x1d000
79
80#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
81 CONFIG_SYS_MONITOR_LEN)
82#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
83#define CONFIG_SPL_BSS_START_ADDR 0x80100000
84#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
85#define CONFIG_SYS_MONITOR_LEN 0xa0000
86#endif
87
Gong Qianyu3ad44722015-10-26 19:47:53 +080088/* NAND SPL */
89#ifdef CONFIG_NAND_BOOT
90#define CONFIG_SPL_PBL_PAD
91#define CONFIG_SPL_FRAMEWORK
92#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
93#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
94#define CONFIG_SPL_LIBCOMMON_SUPPORT
95#define CONFIG_SPL_LIBGENERIC_SUPPORT
96#define CONFIG_SPL_ENV_SUPPORT
97#define CONFIG_SPL_WATCHDOG_SUPPORT
98#define CONFIG_SPL_I2C_SUPPORT
99#define CONFIG_SPL_SERIAL_SUPPORT
100#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
101#define CONFIG_SPL_NAND_SUPPORT
102#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
103#define CONFIG_SPL_TEXT_BASE 0x10000000
104#define CONFIG_SPL_MAX_SIZE 0x1a000
105#define CONFIG_SPL_STACK 0x1001d000
106#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
107#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
108#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
109#define CONFIG_SPL_BSS_START_ADDR 0x80100000
110#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
111#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
112#define CONFIG_SYS_MONITOR_LEN 0xa0000
113#endif
114
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800115/* IFC */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800116#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800117#define CONFIG_FSL_IFC
118/*
119 * CONFIG_SYS_FLASH_BASE has the final address (core view)
120 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
121 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
122 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
123 */
124#define CONFIG_SYS_FLASH_BASE 0x60000000
125#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
126#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
127
128#ifndef CONFIG_SYS_NO_FLASH
129#define CONFIG_FLASH_CFI_DRIVER
130#define CONFIG_SYS_FLASH_CFI
131#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
132#define CONFIG_SYS_FLASH_QUIET_TEST
133#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
134#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800135#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800136
137/* I2C */
138#define CONFIG_CMD_I2C
139#define CONFIG_SYS_I2C
140#define CONFIG_SYS_I2C_MXC
141#define CONFIG_SYS_I2C_MXC_I2C1
142#define CONFIG_SYS_I2C_MXC_I2C2
143#define CONFIG_SYS_I2C_MXC_I2C3
144#define CONFIG_SYS_I2C_MXC_I2C4
145
146/* PCIe */
147#define CONFIG_PCI /* Enable PCI/PCIE */
148#define CONFIG_PCIE1 /* PCIE controller 1 */
149#define CONFIG_PCIE2 /* PCIE controller 2 */
150#define CONFIG_PCIE3 /* PCIE controller 3 */
151#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
152#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
153
154#define CONFIG_SYS_PCI_64BIT
155
156#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
157#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
158#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
159#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
160
161#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
162#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
163#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
164
165#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
166#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
167#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
168
169#ifdef CONFIG_PCI
170#define CONFIG_NET_MULTI
171#define CONFIG_PCI_PNP
172#define CONFIG_E1000
173#define CONFIG_PCI_SCAN_SHOW
174#define CONFIG_CMD_PCI
175#endif
176
177/* Command line configuration */
178#define CONFIG_CMD_CACHE
179#define CONFIG_CMD_DHCP
180#define CONFIG_CMD_ENV
181#define CONFIG_CMD_PING
182
Yangbo Lu8ef0d5c2015-10-26 19:47:55 +0800183/* MMC */
184#define CONFIG_MMC
185#ifdef CONFIG_MMC
186#define CONFIG_CMD_MMC
187#define CONFIG_CMD_FAT
188#define CONFIG_FSL_ESDHC
189#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
190#define CONFIG_GENERIC_MMC
191#define CONFIG_DOS_PARTITION
192#endif
193
Gong Qianyue0579a52016-01-25 15:16:05 +0800194/* DSPI */
195#define CONFIG_FSL_DSPI
196#ifdef CONFIG_FSL_DSPI
197#define CONFIG_CMD_SF
198#define CONFIG_DM_SPI_FLASH
199#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
200#define CONFIG_SPI_FLASH_SST /* cs1 */
201#define CONFIG_SPI_FLASH_EON /* cs2 */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800202#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyue0579a52016-01-25 15:16:05 +0800203#define CONFIG_SF_DEFAULT_BUS 1
204#define CONFIG_SF_DEFAULT_CS 0
205#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800206#endif
Gong Qianyue0579a52016-01-25 15:16:05 +0800207
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530208#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
209
Shaohui Xiee8297342015-10-26 19:47:54 +0800210/* FMan ucode */
211#define CONFIG_SYS_DPAA_FMAN
212#ifdef CONFIG_SYS_DPAA_FMAN
213#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
214
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800215#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800216#define CONFIG_SYS_QE_FW_IN_SPIFLASH
217#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
218#define CONFIG_ENV_SPI_BUS 0
219#define CONFIG_ENV_SPI_CS 0
220#define CONFIG_ENV_SPI_MAX_HZ 1000000
221#define CONFIG_ENV_SPI_MODE 0x03
222#else
Shaohui Xiee8297342015-10-26 19:47:54 +0800223#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
224/* FMan fireware Pre-load address */
225#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800226#endif
Shaohui Xiee8297342015-10-26 19:47:54 +0800227#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
228#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
229#endif
230
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800231/* Miscellaneous configurable options */
232#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
233#define CONFIG_ARCH_EARLY_INIT_R
234#define CONFIG_BOARD_LATE_INIT
235
236#define CONFIG_HWCONFIG
237#define HWCONFIG_BUFFER_SIZE 128
238
239/* Initial environment variables */
240#define CONFIG_EXTRA_ENV_SETTINGS \
241 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
242 "loadaddr=0x80100000\0" \
243 "kernel_addr=0x100000\0" \
244 "ramdisk_addr=0x800000\0" \
245 "ramdisk_size=0x2000000\0" \
246 "fdt_high=0xffffffffffffffff\0" \
247 "initrd_high=0xffffffffffffffff\0" \
Qianyu Gongad6767b2016-03-15 16:35:57 +0800248 "kernel_start=0x61100000\0" \
249 "kernel_load=0xa0000000\0" \
250 "kernel_size=0x2800000\0" \
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800251 "console=ttyAMA0,38400n8\0"
252
253#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
Qianyu Gongad6767b2016-03-15 16:35:57 +0800254 "earlycon=uart8250,mmio,0x21c0500"
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800255#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
256 "$kernel_size && bootm $kernel_load"
257#define CONFIG_BOOTDELAY 10
258
259/* Monitor Command Prompt */
260#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
261#define CONFIG_SYS_PROMPT "=> "
262#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
263 sizeof(CONFIG_SYS_PROMPT) + 16)
264#define CONFIG_SYS_HUSH_PARSER
265#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
266#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
267#define CONFIG_SYS_LONGHELP
268#define CONFIG_CMDLINE_EDITING 1
269#define CONFIG_AUTO_COMPLETE
270#define CONFIG_SYS_MAXARGS 64 /* max command args */
271
272#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
273
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530274/* Hash command with SHA acceleration supported in hardware */
275#ifdef CONFIG_FSL_CAAM
276#define CONFIG_CMD_HASH
277#define CONFIG_SHA_HW_ACCEL
278#endif
279
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800280#endif /* __LS1043A_COMMON_H */