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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc6097192002-11-03 00:24:07 +000020#define CONFIG_PIP405 1 /* ...on a PIP405 board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021
22#define CONFIG_SYS_TEXT_BASE 0xFFF80000
23
wdenkc6097192002-11-03 00:24:07 +000024/***********************************************************
25 * Clock
26 ***********************************************************/
27#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
28
Jon Loeligeracf02692007-07-08 14:49:44 -050029/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050030 * BOOTP options
31 */
32#define CONFIG_BOOTP_BOOTFILESIZE
33#define CONFIG_BOOTP_BOOTPATH
34#define CONFIG_BOOTP_GATEWAY
35#define CONFIG_BOOTP_HOSTNAME
36
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050037/*
Jon Loeligeracf02692007-07-08 14:49:44 -050038 * Command line configuration.
39 */
Jon Loeligeracf02692007-07-08 14:49:44 -050040#define CONFIG_CMD_IDE
Jon Loeligeracf02692007-07-08 14:49:44 -050041#define CONFIG_CMD_PCI
Jon Loeligeracf02692007-07-08 14:49:44 -050042#define CONFIG_CMD_IRQ
43#define CONFIG_CMD_EEPROM
Jon Loeligeracf02692007-07-08 14:49:44 -050044#define CONFIG_CMD_REGINFO
45#define CONFIG_CMD_FDC
Simon Glassc649e3c2016-05-01 11:36:02 -060046#define CONFIG_SCSI
Jon Loeligeracf02692007-07-08 14:49:44 -050047#define CONFIG_CMD_DATE
Jon Loeligeracf02692007-07-08 14:49:44 -050048#define CONFIG_CMD_SDRAM
Jon Loeligeracf02692007-07-08 14:49:44 -050049#define CONFIG_CMD_SAVES
50#define CONFIG_CMD_BSP
51
wdenkc6097192002-11-03 00:24:07 +000052/**************************************************************
53 * I2C Stuff:
54 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
55 * 0x53.
56 * Caution: on the same bus is the SPD (Serial Presens Detect
57 * EEPROM of the SDRAM
58 * The Atmel EEPROM uses 16Bit addressing.
59 ***************************************************************/
Dirk Eibach880540d2013-04-25 02:40:01 +000060#define CONFIG_SYS_I2C
61#define CONFIG_SYS_I2C_PPC4XX
62#define CONFIG_SYS_I2C_PPC4XX_CH0
63#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
64#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenkc6097192002-11-03 00:24:07 +000065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
67#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020068#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020069#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
70#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
wdenkc6097192002-11-03 00:24:07 +000071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
73#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenkc6097192002-11-03 00:24:07 +000074 /* 64 byte page write mode using*/
75 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +000077
wdenkc6097192002-11-03 00:24:07 +000078/***************************************************************
79 * Definitions for Serial Presence Detect EEPROM address
80 * (to get SDRAM settings)
81 ***************************************************************/
82#define SPD_EEPROM_ADDRESS 0x50
83
wdenkc837dcb2004-01-20 23:12:12 +000084#define CONFIG_BOARD_EARLY_INIT_F
David Müller21be3092011-12-22 13:38:20 +010085#define CONFIG_BOARD_EARLY_INIT_R
86
wdenkc6097192002-11-03 00:24:07 +000087/**************************************************************
88 * Environment definitions
89 **************************************************************/
90#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
91
wdenkc6097192002-11-03 00:24:07 +000092#define CONFIG_BOOTDELAY 5
93/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk2afbe4e2005-08-13 02:04:37 +020094/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020095#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenkc6097192002-11-03 00:24:07 +000096
wdenk3e386912003-04-05 00:53:31 +000097#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +000098#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
99
100#define CONFIG_IPADDR 10.0.0.100
101#define CONFIG_SERVERIP 10.0.0.1
102#define CONFIG_PREBOOT
103/***************************************************************
104 * defines if the console is stored in the environment
105 ***************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenkc6097192002-11-03 00:24:07 +0000107/***************************************************************
108 * defines if an overwrite_console function exists
109 *************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
111#define CONFIG_SYS_CONSOLE_INFO_QUIET
wdenkc6097192002-11-03 00:24:07 +0000112/***************************************************************
113 * defines if the overwrite_console should be stored in the
114 * environment
115 **************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
wdenkc6097192002-11-03 00:24:07 +0000117
118/**************************************************************
119 * loads config
120 *************************************************************/
121#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +0000123
wdenk7205e402003-09-10 22:30:53 +0000124#define CONFIG_MISC_INIT_R
wdenkc6097192002-11-03 00:24:07 +0000125/***********************************************************
126 * Miscellaneous configurable options
127 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligeracf02692007-07-08 14:49:44 -0500129#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000131#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000133#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
135#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000140
Stefan Roese550650d2010-09-20 16:05:31 +0200141#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese550650d2010-09-20 16:05:31 +0200142#define CONFIG_SYS_NS16550_SERIAL
143#define CONFIG_SYS_NS16550_REG_SIZE 1
144#define CONFIG_SYS_NS16550_CLK get_serial_clock()
145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
147#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000148
149/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc6097192002-11-03 00:24:07 +0000151 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
152 57600, 115200, 230400, 460800, 921600 }
153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
155#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000156
wdenkc6097192002-11-03 00:24:07 +0000157/*-----------------------------------------------------------------------
158 * PCI stuff
159 *-----------------------------------------------------------------------
160 */
161#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
162#define PCI_HOST_FORCE 1 /* configure as pci host */
163#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
164
165#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000166#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc6097192002-11-03 00:24:07 +0000167#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
168#define CONFIG_PCI_PNP /* pci plug-and-play */
169 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
171#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
172#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
173#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
174#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
175#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
176#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
177#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000178
179/*-----------------------------------------------------------------------
180 * Start addresses for the final memory configuration
181 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_SDRAM_BASE 0x00000000
185#define CONFIG_SYS_FLASH_BASE 0xFFF80000
186#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
187#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
188#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000189
190/*
191 * For booting Linux, the board info and command line data
192 * have to be in the first 8 MB of memory, since this is
193 * the maximum mapped by the Linux kernel during initialization.
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000196/*-----------------------------------------------------------------------
197 * FLASH organization
198 */
David Müller21be3092011-12-22 13:38:20 +0100199#define CONFIG_SYS_UPDATE_FLASH_SIZE
200#define CONFIG_SYS_FLASH_PROTECTION
201#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenkc6097192002-11-03 00:24:07 +0000202
David Müller21be3092011-12-22 13:38:20 +0100203#define CONFIG_SYS_FLASH_CFI
204#define CONFIG_FLASH_CFI_DRIVER
205
206#define CONFIG_FLASH_SHOW_PROGRESS 45
207
208#define CONFIG_SYS_MAX_FLASH_BANKS 1
209#define CONFIG_SYS_MAX_FLASH_SECT 256
wdenkc6097192002-11-03 00:24:07 +0000210
wdenkc6097192002-11-03 00:24:07 +0000211/*
212 * Init Memory Controller:
213 */
wdenk7205e402003-09-10 22:30:53 +0000214#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
215#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
216/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
217#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000218
wdenkc837dcb2004-01-20 23:12:12 +0000219#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000220
221/* Configuration Port location */
222#define CONFIG_PORT_ADDR 0xF4000000
223#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
224
wdenkc6097192002-11-03 00:24:07 +0000225/*-----------------------------------------------------------------------
226 * Definitions for initial stack pointer and data area (in On Chip SRAM)
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_TEMP_STACK_OCM 1
229#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
230#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
231#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200232#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200233#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000235
wdenkc6097192002-11-03 00:24:07 +0000236/***********************************************************************
237 * External peripheral base address
238 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenkc6097192002-11-03 00:24:07 +0000240
241/***********************************************************************
242 * Last Stage Init
243 ***********************************************************************/
244#define CONFIG_LAST_STAGE_INIT
245/************************************************************
246 * Ethernet Stuff
247 ***********************************************************/
Ben Warren96e21f82008-10-27 23:50:15 -0700248#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +0000249#define CONFIG_MII 1 /* MII PHY management */
250#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenkc6097192002-11-03 00:24:07 +0000251/************************************************************
252 * RTC
253 ***********************************************************/
254#define CONFIG_RTC_MC146818
255#undef CONFIG_WATCHDOG /* watchdog disabled */
256
257/************************************************************
258 * IDE/ATA stuff
259 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
261#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
264#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
265#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
266#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
267#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
268#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenkc6097192002-11-03 00:24:07 +0000269
270#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
271#undef CONFIG_IDE_LED /* no led for ide supported */
272#define CONFIG_IDE_RESET /* reset for ide supported... */
273#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk7205e402003-09-10 22:30:53 +0000274#define CONFIG_SUPPORT_VFAT
wdenkc6097192002-11-03 00:24:07 +0000275
276/************************************************************
277 * ATAPI support (experimental)
278 ************************************************************/
279#define CONFIG_ATAPI /* enable ATAPI Support */
280
281/************************************************************
282 * SCSI support (experimental) only SYM53C8xx supported
283 ************************************************************/
284#define CONFIG_SCSI_SYM53C8XX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
286#define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
287#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
288#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
wdenkc6097192002-11-03 00:24:07 +0000289
290/************************************************************
291 * Disk-On-Chip configuration
292 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
294#define CONFIG_SYS_DOC_SHORT_TIMEOUT
295#define CONFIG_SYS_DOC_SUPPORT_2000
296#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
wdenkc6097192002-11-03 00:24:07 +0000297
298/************************************************************
299 * DISK Partition support
300 ************************************************************/
301#define CONFIG_DOS_PARTITION
302#define CONFIG_MAC_PARTITION
303#define CONFIG_ISO_PARTITION /* Experimental */
304
305/************************************************************
wdenkc6097192002-11-03 00:24:07 +0000306 * Video support
307 ************************************************************/
308#define CONFIG_VIDEO /*To enable video controller support */
309#define CONFIG_VIDEO_CT69000
310#define CONFIG_CFB_CONSOLE
311#define CONFIG_VIDEO_LOGO
312#define CONFIG_CONSOLE_EXTRA_INFO
313#define CONFIG_VGA_AS_SINGLE_DEVICE
314#define CONFIG_VIDEO_SW_CURSOR
315#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
316
317/************************************************************
318 * USB support
319 ************************************************************/
320#define CONFIG_USB_UHCI
321#define CONFIG_USB_KEYBOARD
322#define CONFIG_USB_STORAGE
323
324/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200325#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
wdenkc6097192002-11-03 00:24:07 +0000326
327/************************************************************
328 * Debug support
329 ************************************************************/
Jon Loeligeracf02692007-07-08 14:49:44 -0500330#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000331#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenkc6097192002-11-03 00:24:07 +0000332#endif
333
334/************************************************************
wdenka2663ea2003-12-07 18:32:37 +0000335 * support BZIP2 compression
336 ************************************************************/
337#define CONFIG_BZIP2 1
338
339/************************************************************
wdenkc6097192002-11-03 00:24:07 +0000340 * Ident
341 ************************************************************/
342#define VERSION_TAG "released"
wdenkf3e0de62003-06-04 15:05:30 +0000343#define CONFIG_ISO_STRING "MEV-10066-001"
344#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
wdenkc6097192002-11-03 00:24:07 +0000345
wdenkc6097192002-11-03 00:24:07 +0000346#endif /* __CONFIG_H */