blob: f870cdbddf6464a675767ad35ce2910278d32b23 [file] [log] [blame]
Tom Warren4e5ae092011-06-17 06:27:28 +00001/*
Allen Martin00a27492012-08-31 08:30:00 +00002 * NVIDIA Tegra20 GPIO handling.
Tom Warren52a8b822012-05-22 12:19:25 +00003 * (C) Copyright 2010-2012
Tom Warren4e5ae092011-06-17 06:27:28 +00004 * NVIDIA Corporation <www.nvidia.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Tom Warren4e5ae092011-06-17 06:27:28 +00007 */
8
9/*
10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
11 * Tom Warren (twarren@nvidia.com)
12 */
13
14#include <common.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060015#include <dm.h>
16#include <malloc.h>
17#include <errno.h>
18#include <fdtdec.h>
Tom Warren4e5ae092011-06-17 06:27:28 +000019#include <asm/io.h>
20#include <asm/bitops.h>
Tom Warren150c2492012-09-19 15:50:56 -070021#include <asm/arch/tegra.h>
Tom Warren4e5ae092011-06-17 06:27:28 +000022#include <asm/gpio.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060023#include <dm/device-internal.h>
Simon Glass838aa5c2015-01-05 20:05:33 -070024#include <dt-bindings/gpio/gpio.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060025
26DECLARE_GLOBAL_DATA_PTR;
Tom Warren4e5ae092011-06-17 06:27:28 +000027
28enum {
Tom Warren29f3e3f2012-09-04 17:00:24 -070029 TEGRA_CMD_INFO,
30 TEGRA_CMD_PORT,
31 TEGRA_CMD_OUTPUT,
32 TEGRA_CMD_INPUT,
Tom Warren4e5ae092011-06-17 06:27:28 +000033};
34
Simon Glass2fccd2d2014-09-03 17:37:03 -060035struct tegra_gpio_platdata {
36 struct gpio_ctlr_bank *bank;
37 const char *port_name; /* Name of port, e.g. "B" */
38 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
39};
Tom Warren4e5ae092011-06-17 06:27:28 +000040
Simon Glass2fccd2d2014-09-03 17:37:03 -060041/* Information about each port at run-time */
42struct tegra_port_info {
Simon Glass2fccd2d2014-09-03 17:37:03 -060043 struct gpio_ctlr_bank *bank;
44 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
45};
Tom Warren4e5ae092011-06-17 06:27:28 +000046
Joe Hershberger365d6072011-11-11 15:55:36 -060047/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
48static int get_config(unsigned gpio)
Tom Warren4e5ae092011-06-17 06:27:28 +000049{
Joe Hershberger365d6072011-11-11 15:55:36 -060050 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
51 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000052 u32 u;
53 int type;
54
Joe Hershberger365d6072011-11-11 15:55:36 -060055 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
56 type = (u >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +000057
58 debug("get_config: port = %d, bit = %d is %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060059 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
Tom Warren4e5ae092011-06-17 06:27:28 +000060
61 return type;
62}
63
Joe Hershberger365d6072011-11-11 15:55:36 -060064/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
65static void set_config(unsigned gpio, int type)
Tom Warren4e5ae092011-06-17 06:27:28 +000066{
Joe Hershberger365d6072011-11-11 15:55:36 -060067 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
68 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000069 u32 u;
70
71 debug("set_config: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060072 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
Tom Warren4e5ae092011-06-17 06:27:28 +000073
Joe Hershberger365d6072011-11-11 15:55:36 -060074 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +000075 if (type) /* GPIO */
Joe Hershberger365d6072011-11-11 15:55:36 -060076 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +000077 else
Joe Hershberger365d6072011-11-11 15:55:36 -060078 u &= ~(1 << GPIO_BIT(gpio));
79 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +000080}
81
Joe Hershberger365d6072011-11-11 15:55:36 -060082/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
83static int get_direction(unsigned gpio)
Tom Warren4e5ae092011-06-17 06:27:28 +000084{
Joe Hershberger365d6072011-11-11 15:55:36 -060085 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
86 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000087 u32 u;
88 int dir;
89
Joe Hershberger365d6072011-11-11 15:55:36 -060090 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
91 dir = (u >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +000092
93 debug("get_direction: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060094 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
Tom Warren4e5ae092011-06-17 06:27:28 +000095
96 return dir;
97}
98
Joe Hershberger365d6072011-11-11 15:55:36 -060099/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
100static void set_direction(unsigned gpio, int output)
Tom Warren4e5ae092011-06-17 06:27:28 +0000101{
Joe Hershberger365d6072011-11-11 15:55:36 -0600102 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
103 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +0000104 u32 u;
105
106 debug("set_direction: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -0600107 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
Tom Warren4e5ae092011-06-17 06:27:28 +0000108
Joe Hershberger365d6072011-11-11 15:55:36 -0600109 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000110 if (output)
Joe Hershberger365d6072011-11-11 15:55:36 -0600111 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +0000112 else
Joe Hershberger365d6072011-11-11 15:55:36 -0600113 u &= ~(1 << GPIO_BIT(gpio));
114 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000115}
116
Joe Hershberger365d6072011-11-11 15:55:36 -0600117/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
118static void set_level(unsigned gpio, int high)
Tom Warren4e5ae092011-06-17 06:27:28 +0000119{
Joe Hershberger365d6072011-11-11 15:55:36 -0600120 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
121 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +0000122 u32 u;
123
124 debug("set_level: port = %d, bit %d == %d\n",
Joe Hershberger365d6072011-11-11 15:55:36 -0600125 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
Tom Warren4e5ae092011-06-17 06:27:28 +0000126
Joe Hershberger365d6072011-11-11 15:55:36 -0600127 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000128 if (high)
Joe Hershberger365d6072011-11-11 15:55:36 -0600129 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +0000130 else
Joe Hershberger365d6072011-11-11 15:55:36 -0600131 u &= ~(1 << GPIO_BIT(gpio));
132 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000133}
134
135/*
136 * Generic_GPIO primitives.
137 */
138
Simon Glass2fccd2d2014-09-03 17:37:03 -0600139static int tegra_gpio_request(struct udevice *dev, unsigned offset,
140 const char *label)
Tom Warren4e5ae092011-06-17 06:27:28 +0000141{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600142 struct tegra_port_info *state = dev_get_priv(dev);
Tom Warren4e5ae092011-06-17 06:27:28 +0000143
Tom Warren4e5ae092011-06-17 06:27:28 +0000144 /* Configure as a GPIO */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600145 set_config(state->base_gpio + offset, 1);
Tom Warren4e5ae092011-06-17 06:27:28 +0000146
147 return 0;
148}
149
Joe Hershberger365d6072011-11-11 15:55:36 -0600150/* set GPIO pin 'gpio' as an input */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600151static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000152{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600153 struct tegra_port_info *state = dev_get_priv(dev);
Tom Warren4e5ae092011-06-17 06:27:28 +0000154
155 /* Configure GPIO direction as input. */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600156 set_direction(state->base_gpio + offset, 0);
Tom Warren4e5ae092011-06-17 06:27:28 +0000157
158 return 0;
159}
160
Joe Hershberger365d6072011-11-11 15:55:36 -0600161/* set GPIO pin 'gpio' as an output, with polarity 'value' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600162static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
163 int value)
Tom Warren4e5ae092011-06-17 06:27:28 +0000164{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600165 struct tegra_port_info *state = dev_get_priv(dev);
166 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000167
168 /* Configure GPIO output value. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600169 set_level(gpio, value);
Tom Warren4e5ae092011-06-17 06:27:28 +0000170
171 /* Configure GPIO direction as output. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600172 set_direction(gpio, 1);
Tom Warren4e5ae092011-06-17 06:27:28 +0000173
174 return 0;
175}
176
Joe Hershberger365d6072011-11-11 15:55:36 -0600177/* read GPIO IN value of pin 'gpio' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600178static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000179{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600180 struct tegra_port_info *state = dev_get_priv(dev);
181 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000182 int val;
183
Simon Glass2fccd2d2014-09-03 17:37:03 -0600184 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
185 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
186
187 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000188
Joe Hershberger365d6072011-11-11 15:55:36 -0600189 return (val >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +0000190}
191
Joe Hershberger365d6072011-11-11 15:55:36 -0600192/* write GPIO OUT value to pin 'gpio' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600193static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
Tom Warren4e5ae092011-06-17 06:27:28 +0000194{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600195 struct tegra_port_info *state = dev_get_priv(dev);
196 int gpio = state->base_gpio + offset;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600197
Tom Warren4e5ae092011-06-17 06:27:28 +0000198 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
Simon Glass2fccd2d2014-09-03 17:37:03 -0600199 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
Tom Warren4e5ae092011-06-17 06:27:28 +0000200
201 /* Configure GPIO output value. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600202 set_level(gpio, value);
203
204 return 0;
Tom Warren4e5ae092011-06-17 06:27:28 +0000205}
206
Stephen Warreneceb3f22014-04-22 14:37:53 -0600207void gpio_config_table(const struct tegra_gpio_config *config, int len)
208{
209 int i;
210
211 for (i = 0; i < len; i++) {
212 switch (config[i].init) {
213 case TEGRA_GPIO_INIT_IN:
214 gpio_direction_input(config[i].gpio);
215 break;
216 case TEGRA_GPIO_INIT_OUT0:
217 gpio_direction_output(config[i].gpio, 0);
218 break;
219 case TEGRA_GPIO_INIT_OUT1:
220 gpio_direction_output(config[i].gpio, 1);
221 break;
222 }
223 set_config(config[i].gpio, 1);
224 }
225}
226
Simon Glass2fccd2d2014-09-03 17:37:03 -0600227static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000228{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600229 struct tegra_port_info *state = dev_get_priv(dev);
230 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000231
Simon Glass2fccd2d2014-09-03 17:37:03 -0600232 if (!get_config(gpio))
233 return GPIOF_FUNC;
234 else if (get_direction(gpio))
235 return GPIOF_OUTPUT;
236 else
237 return GPIOF_INPUT;
Tom Warren4e5ae092011-06-17 06:27:28 +0000238}
Simon Glass2fccd2d2014-09-03 17:37:03 -0600239
Simon Glass838aa5c2015-01-05 20:05:33 -0700240static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
241 struct fdtdec_phandle_args *args)
242{
243 int gpio, port, ret;
244
245 gpio = args->args[0];
246 port = gpio / TEGRA_GPIOS_PER_PORT;
247 ret = device_get_child(dev, port, &desc->dev);
248 if (ret)
249 return ret;
250 desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
251 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
252
253 return 0;
254}
255
Simon Glass2fccd2d2014-09-03 17:37:03 -0600256static const struct dm_gpio_ops gpio_tegra_ops = {
257 .request = tegra_gpio_request,
Simon Glass2fccd2d2014-09-03 17:37:03 -0600258 .direction_input = tegra_gpio_direction_input,
259 .direction_output = tegra_gpio_direction_output,
260 .get_value = tegra_gpio_get_value,
261 .set_value = tegra_gpio_set_value,
262 .get_function = tegra_gpio_get_function,
Simon Glass838aa5c2015-01-05 20:05:33 -0700263 .xlate = tegra_gpio_xlate,
Simon Glass2fccd2d2014-09-03 17:37:03 -0600264};
265
266/**
267 * Returns the name of a GPIO port
268 *
269 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
270 *
271 * @base_port: Base port number (0, 1..n-1)
272 * @return allocated string containing the name
273 */
274static char *gpio_port_name(int base_port)
275{
276 char *name, *s;
277
278 name = malloc(3);
279 if (name) {
280 s = name;
281 *s++ = 'A' + (base_port % 26);
282 if (base_port >= 26)
283 *s++ = *name;
284 *s = '\0';
285 }
286
287 return name;
288}
289
290static const struct udevice_id tegra_gpio_ids[] = {
291 { .compatible = "nvidia,tegra30-gpio" },
292 { .compatible = "nvidia,tegra20-gpio" },
293 { }
294};
295
296static int gpio_tegra_probe(struct udevice *dev)
297{
298 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
299 struct tegra_port_info *priv = dev->priv;
300 struct tegra_gpio_platdata *plat = dev->platdata;
301
302 /* Only child devices have ports */
303 if (!plat)
304 return 0;
305
306 priv->bank = plat->bank;
307 priv->base_gpio = plat->base_gpio;
308
309 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
310 uc_priv->bank_name = plat->port_name;
311
312 return 0;
313}
314
315/**
316 * We have a top-level GPIO device with no actual GPIOs. It has a child
317 * device for each Tegra port.
318 */
319static int gpio_tegra_bind(struct udevice *parent)
320{
321 struct tegra_gpio_platdata *plat = parent->platdata;
322 struct gpio_ctlr *ctlr;
323 int bank_count;
324 int bank;
325 int ret;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600326
327 /* If this is a child device, there is nothing to do here */
328 if (plat)
329 return 0;
330
Simon Glassbdfb3412015-03-03 08:02:59 -0700331 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
332#ifdef CONFIG_SPL_BUILD
333 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
334 bank_count = TEGRA_GPIO_BANKS;
335#else
336 {
337 int len;
338
Simon Glass2fccd2d2014-09-03 17:37:03 -0600339 /*
340 * This driver does not make use of interrupts, other than to figure
341 * out the number of GPIO banks
342 */
343 if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
344 return -EINVAL;
345 bank_count = len / 3 / sizeof(u32);
346 ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
347 parent->of_offset, "reg");
Simon Glassbdfb3412015-03-03 08:02:59 -0700348 }
349#endif
Simon Glass2fccd2d2014-09-03 17:37:03 -0600350 for (bank = 0; bank < bank_count; bank++) {
351 int port;
352
353 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
354 struct tegra_gpio_platdata *plat;
355 struct udevice *dev;
356 int base_port;
357
358 plat = calloc(1, sizeof(*plat));
359 if (!plat)
360 return -ENOMEM;
361 plat->bank = &ctlr->gpio_bank[bank];
362 base_port = bank * TEGRA_PORTS_PER_BANK + port;
363 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
364 plat->port_name = gpio_port_name(base_port);
365
366 ret = device_bind(parent, parent->driver,
367 plat->port_name, plat, -1, &dev);
368 if (ret)
369 return ret;
370 dev->of_offset = parent->of_offset;
371 }
372 }
373
374 return 0;
375}
376
377U_BOOT_DRIVER(gpio_tegra) = {
378 .name = "gpio_tegra",
379 .id = UCLASS_GPIO,
380 .of_match = tegra_gpio_ids,
381 .bind = gpio_tegra_bind,
382 .probe = gpio_tegra_probe,
383 .priv_auto_alloc_size = sizeof(struct tegra_port_info),
384 .ops = &gpio_tegra_ops,
Simon Glassbdfb3412015-03-03 08:02:59 -0700385 .flags = DM_FLAG_PRE_RELOC,
Simon Glass2fccd2d2014-09-03 17:37:03 -0600386};