blob: deff617ed4685deb547588892a3cf91e8b80d1be [file] [log] [blame]
Shengzhou Liu48c6f322014-11-24 17:11:56 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T1024/T1023 RDB board configuration file
9 */
10
11#ifndef __T1024RDB_H
12#define __T1024RDB_H
13
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080014#if defined(CONFIG_T1023RDB)
15#ifdef CONFIG_SPL
16#define CONFIG_SYS_NO_FLASH
17#endif
18#endif
19
Shengzhou Liu48c6f322014-11-24 17:11:56 +080020/* High Level Configuration Options */
21#define CONFIG_SYS_GENERIC_BOARD
22#define CONFIG_DISPLAY_BOARDINFO
23#define CONFIG_BOOKE
24#define CONFIG_E500 /* BOOKE e500 family */
25#define CONFIG_E500MC /* BOOKE e500mc family */
26#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
27#define CONFIG_MP /* support multiple processors */
28#define CONFIG_PHYS_64BIT
29#define CONFIG_ENABLE_36BIT_PHYS
30
31#ifdef CONFIG_PHYS_64BIT
32#define CONFIG_ADDR_MAP 1
33#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
34#endif
35
36#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
37#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
38#define CONFIG_FSL_IFC /* Enable IFC Support */
39
40#define CONFIG_FSL_LAW /* Use common FSL init code */
41#define CONFIG_ENV_OVERWRITE
42
43/* support deep sleep */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080044#ifdef CONFIG_PPC_T1024
Shengzhou Liu48c6f322014-11-24 17:11:56 +080045#define CONFIG_DEEP_SLEEP
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080046#endif
tang yuantianf49b8c12014-12-17 15:42:54 +080047#if defined(CONFIG_DEEP_SLEEP)
Shengzhou Liu48c6f322014-11-24 17:11:56 +080048#define CONFIG_SILENT_CONSOLE
tang yuantianf49b8c12014-12-17 15:42:54 +080049#define CONFIG_BOARD_EARLY_INIT_F
50#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +080051
52#ifdef CONFIG_RAMBOOT_PBL
53#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080054#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +080055#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080056#elif defined(CONFIG_T1023RDB)
57#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
58#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +080059#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
60#define CONFIG_SPL_ENV_SUPPORT
61#define CONFIG_SPL_SERIAL_SUPPORT
62#define CONFIG_SPL_FLUSH_IMAGE
63#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
64#define CONFIG_SPL_LIBGENERIC_SUPPORT
65#define CONFIG_SPL_LIBCOMMON_SUPPORT
66#define CONFIG_SPL_I2C_SUPPORT
67#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
68#define CONFIG_FSL_LAW /* Use common FSL init code */
tang yuantianf49b8c12014-12-17 15:42:54 +080069#define CONFIG_SYS_TEXT_BASE 0x30001000
Shengzhou Liu48c6f322014-11-24 17:11:56 +080070#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
71#define CONFIG_SPL_PAD_TO 0x40000
72#define CONFIG_SPL_MAX_SIZE 0x28000
73#define RESET_VECTOR_OFFSET 0x27FFC
74#define BOOT_PAGE_OFFSET 0x27000
75#ifdef CONFIG_SPL_BUILD
76#define CONFIG_SPL_SKIP_RELOCATE
77#define CONFIG_SPL_COMMON_INIT_DDR
78#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
79#define CONFIG_SYS_NO_FLASH
80#endif
81
82#ifdef CONFIG_NAND
83#define CONFIG_SPL_NAND_SUPPORT
84#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +080085#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
86#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
Shengzhou Liu48c6f322014-11-24 17:11:56 +080087#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
88#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
89#define CONFIG_SPL_NAND_BOOT
90#endif
91
92#ifdef CONFIG_SPIFLASH
tang yuantianf49b8c12014-12-17 15:42:54 +080093#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu48c6f322014-11-24 17:11:56 +080094#define CONFIG_SPL_SPI_SUPPORT
95#define CONFIG_SPL_SPI_FLASH_SUPPORT
96#define CONFIG_SPL_SPI_FLASH_MINIMAL
97#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +080098#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
99#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800100#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
101#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
102#ifndef CONFIG_SPL_BUILD
103#define CONFIG_SYS_MPC85XX_NO_RESETVEC
104#endif
105#define CONFIG_SPL_SPI_BOOT
106#endif
107
108#ifdef CONFIG_SDCARD
tang yuantianf49b8c12014-12-17 15:42:54 +0800109#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800110#define CONFIG_SPL_MMC_SUPPORT
111#define CONFIG_SPL_MMC_MINIMAL
112#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +0800113#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
114#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800115#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
116#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
117#ifndef CONFIG_SPL_BUILD
118#define CONFIG_SYS_MPC85XX_NO_RESETVEC
119#endif
120#define CONFIG_SPL_MMC_BOOT
121#endif
122
123#endif /* CONFIG_RAMBOOT_PBL */
124
125#ifndef CONFIG_SYS_TEXT_BASE
126#define CONFIG_SYS_TEXT_BASE 0xeff40000
127#endif
128
129#ifndef CONFIG_RESET_VECTOR_ADDRESS
130#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
131#endif
132
133#ifndef CONFIG_SYS_NO_FLASH
134#define CONFIG_FLASH_CFI_DRIVER
135#define CONFIG_SYS_FLASH_CFI
136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
137#endif
138
139/* PCIe Boot - Master */
140#define CONFIG_SRIO_PCIE_BOOT_MASTER
141/*
142 * for slave u-boot IMAGE instored in master memory space,
143 * PHYS must be aligned based on the SIZE
144 */
145#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
146#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
147#ifdef CONFIG_PHYS_64BIT
148#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
149#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
150#else
151#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
152#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
153#endif
154/*
155 * for slave UCODE and ENV instored in master memory space,
156 * PHYS must be aligned based on the SIZE
157 */
158#ifdef CONFIG_PHYS_64BIT
159#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
160#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
161#else
162#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
163#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
164#endif
165#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
166/* slave core release by master*/
167#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
168#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
169
170/* PCIe Boot - Slave */
171#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
172#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
173#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
174 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
175/* Set 1M boot space for PCIe boot */
176#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
177#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
178 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
179#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
180#define CONFIG_SYS_NO_FLASH
181#endif
182
183#if defined(CONFIG_SPIFLASH)
184#define CONFIG_SYS_EXTRA_ENV_RELOC
185#define CONFIG_ENV_IS_IN_SPI_FLASH
186#define CONFIG_ENV_SPI_BUS 0
187#define CONFIG_ENV_SPI_CS 0
188#define CONFIG_ENV_SPI_MAX_HZ 10000000
189#define CONFIG_ENV_SPI_MODE 0
190#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
191#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800192#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800193#define CONFIG_ENV_SECT_SIZE 0x10000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800194#elif defined(CONFIG_T1023RDB)
195#define CONFIG_ENV_SECT_SIZE 0x40000
196#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800197#elif defined(CONFIG_SDCARD)
198#define CONFIG_SYS_EXTRA_ENV_RELOC
199#define CONFIG_ENV_IS_IN_MMC
200#define CONFIG_SYS_MMC_ENV_DEV 0
201#define CONFIG_ENV_SIZE 0x2000
202#define CONFIG_ENV_OFFSET (512 * 0x800)
203#elif defined(CONFIG_NAND)
204#define CONFIG_SYS_EXTRA_ENV_RELOC
205#define CONFIG_ENV_IS_IN_NAND
206#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800207#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800208#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800209#elif defined(CONFIG_T1023RDB)
210#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
211#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800212#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
213#define CONFIG_ENV_IS_IN_REMOTE
214#define CONFIG_ENV_ADDR 0xffe20000
215#define CONFIG_ENV_SIZE 0x2000
216#elif defined(CONFIG_ENV_IS_NOWHERE)
217#define CONFIG_ENV_SIZE 0x2000
218#else
219#define CONFIG_ENV_IS_IN_FLASH
220#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
221#define CONFIG_ENV_SIZE 0x2000
222#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
223#endif
224
225
226#ifndef __ASSEMBLY__
227unsigned long get_board_sys_clk(void);
228unsigned long get_board_ddr_clk(void);
229#endif
230
231#define CONFIG_SYS_CLK_FREQ 100000000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800232#define CONFIG_DDR_CLK_FREQ 100000000
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800233
234/*
235 * These can be toggled for performance analysis, otherwise use default.
236 */
237#define CONFIG_SYS_CACHE_STASHING
238#define CONFIG_BACKSIDE_L2_CACHE
239#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
240#define CONFIG_BTB /* toggle branch predition */
241#define CONFIG_DDR_ECC
242#ifdef CONFIG_DDR_ECC
243#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
244#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
245#endif
246
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800247#define CONFIG_CMD_MEMTEST
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800248#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
249#define CONFIG_SYS_MEMTEST_END 0x00400000
250#define CONFIG_SYS_ALT_MEMTEST
251#define CONFIG_PANIC_HANG /* do not reset board on panic */
252
253/*
254 * Config the L3 Cache as L3 SRAM
255 */
256#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
257#define CONFIG_SYS_L3_SIZE (256 << 10)
258#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
259#ifdef CONFIG_RAMBOOT_PBL
260#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
261#endif
262#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
263#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
264#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
265#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
266
267#ifdef CONFIG_PHYS_64BIT
268#define CONFIG_SYS_DCSRBAR 0xf0000000
269#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
270#endif
271
272/* EEPROM */
273#define CONFIG_ID_EEPROM
274#define CONFIG_SYS_I2C_EEPROM_NXID
275#define CONFIG_SYS_EEPROM_BUS_NUM 0
276#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
277#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
278#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
279#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
280
281/*
282 * DDR Setup
283 */
284#define CONFIG_VERY_BIG_RAM
285#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
286#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
287#define CONFIG_DIMM_SLOTS_PER_CTLR 1
288#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800289#define CONFIG_FSL_DDR_INTERACTIVE
290#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800291#define CONFIG_DDR_SPD
292#define CONFIG_SYS_FSL_DDR3
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800293#define CONFIG_SYS_SPD_BUS_NUM 0
294#define SPD_EEPROM_ADDRESS 0x51
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800295#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800296#elif defined(CONFIG_T1023RDB)
297#define CONFIG_SYS_FSL_DDR4
298#define CONFIG_SYS_DDR_RAW_TIMING
299#define CONFIG_SYS_SDRAM_SIZE 2048
300#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800301
302/*
303 * IFC Definitions
304 */
305#define CONFIG_SYS_FLASH_BASE 0xe8000000
306#ifdef CONFIG_PHYS_64BIT
307#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
308#else
309#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
310#endif
311
312#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
313#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
314 CSPR_PORT_SIZE_16 | \
315 CSPR_MSEL_NOR | \
316 CSPR_V)
317#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
318
319/* NOR Flash Timing Params */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800320#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800321#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800322#elif defined(CONFIG_T1023RDB)
323#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
324 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
325#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800326#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
327 FTIM0_NOR_TEADC(0x5) | \
328 FTIM0_NOR_TEAHC(0x5))
329#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
330 FTIM1_NOR_TRAD_NOR(0x1A) |\
331 FTIM1_NOR_TSEQRAD_NOR(0x13))
332#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
333 FTIM2_NOR_TCH(0x4) | \
334 FTIM2_NOR_TWPH(0x0E) | \
335 FTIM2_NOR_TWP(0x1c))
336#define CONFIG_SYS_NOR_FTIM3 0x0
337
338#define CONFIG_SYS_FLASH_QUIET_TEST
339#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
340
341#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
342#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
343#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
344#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
345
346#define CONFIG_SYS_FLASH_EMPTY_INFO
347#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
348
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800349#ifdef CONFIG_T1024RDB
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800350/* CPLD on IFC */
351#define CONFIG_SYS_CPLD_BASE 0xffdf0000
352#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
353#define CONFIG_SYS_CSPR2_EXT (0xf)
354#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
355 | CSPR_PORT_SIZE_8 \
356 | CSPR_MSEL_GPCM \
357 | CSPR_V)
358#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
359#define CONFIG_SYS_CSOR2 0x0
360
361/* CPLD Timing parameters for IFC CS2 */
362#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
363 FTIM0_GPCM_TEADC(0x0e) | \
364 FTIM0_GPCM_TEAHC(0x0e))
365#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
366 FTIM1_GPCM_TRAD(0x1f))
367#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
368 FTIM2_GPCM_TCH(0x8) | \
369 FTIM2_GPCM_TWP(0x1f))
370#define CONFIG_SYS_CS2_FTIM3 0x0
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800371#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800372
373/* NAND Flash on IFC */
374#define CONFIG_NAND_FSL_IFC
375#define CONFIG_SYS_NAND_BASE 0xff800000
376#ifdef CONFIG_PHYS_64BIT
377#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
378#else
379#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
380#endif
381#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
382#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
383 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
384 | CSPR_MSEL_NAND /* MSEL = NAND */ \
385 | CSPR_V)
386#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
387
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800388#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800389#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
390 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
391 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
392 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
393 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
394 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
395 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800396#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
397#elif defined(CONFIG_T1023RDB)
398#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
399 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
400 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
401 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
402 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
403#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
404#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800405
406#define CONFIG_SYS_NAND_ONFI_DETECTION
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800407/* ONFI NAND Flash mode0 Timing Params */
408#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
409 FTIM0_NAND_TWP(0x18) | \
410 FTIM0_NAND_TWCHT(0x07) | \
411 FTIM0_NAND_TWH(0x0a))
412#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
413 FTIM1_NAND_TWBE(0x39) | \
414 FTIM1_NAND_TRR(0x0e) | \
415 FTIM1_NAND_TRP(0x18))
416#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
417 FTIM2_NAND_TREH(0x0a) | \
418 FTIM2_NAND_TWHRE(0x1e))
419#define CONFIG_SYS_NAND_FTIM3 0x0
420
421#define CONFIG_SYS_NAND_DDR_LAW 11
422#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
423#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800424#define CONFIG_CMD_NAND
425
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800426#if defined(CONFIG_NAND)
427#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
428#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
429#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
430#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
431#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
432#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
433#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
434#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
435#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
436#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
437#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
438#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
439#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
440#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
441#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
442#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
443#else
444#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
445#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
446#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
447#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
448#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
449#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
450#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
451#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
452#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
453#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
454#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
455#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
456#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
457#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
458#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
459#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
460#endif
461
462#ifdef CONFIG_SPL_BUILD
463#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
464#else
465#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
466#endif
467
468#if defined(CONFIG_RAMBOOT_PBL)
469#define CONFIG_SYS_RAMBOOT
470#endif
471
472#define CONFIG_BOARD_EARLY_INIT_R
473#define CONFIG_MISC_INIT_R
474
475#define CONFIG_HWCONFIG
476
477/* define to use L1 as initial stack */
478#define CONFIG_L1_INIT_RAM
479#define CONFIG_SYS_INIT_RAM_LOCK
480#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
481#ifdef CONFIG_PHYS_64BIT
482#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
483#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
484/* The assembler doesn't like typecast */
485#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
486 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
487 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
488#else
489#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
490#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
491#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
492#endif
493#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
494
495#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
496 GENERATED_GBL_DATA_SIZE)
497#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
498
499#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
500#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
501
502/* Serial Port */
503#define CONFIG_CONS_INDEX 1
504#define CONFIG_SYS_NS16550
505#define CONFIG_SYS_NS16550_SERIAL
506#define CONFIG_SYS_NS16550_REG_SIZE 1
507#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
508
509#define CONFIG_SYS_BAUDRATE_TABLE \
510 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
511
512#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
513#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
514#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
515#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
516#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
517
518/* Use the HUSH parser */
519#define CONFIG_SYS_HUSH_PARSER
520#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
521
522/* Video */
523#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
524#ifdef CONFIG_FSL_DIU_FB
525#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
526#define CONFIG_VIDEO
527#define CONFIG_CMD_BMP
528#define CONFIG_CFB_CONSOLE
529#define CONFIG_VIDEO_SW_CURSOR
530#define CONFIG_VGA_AS_SINGLE_DEVICE
531#define CONFIG_VIDEO_LOGO
532#define CONFIG_VIDEO_BMP_LOGO
533#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
534/*
535 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
536 * disable empty flash sector detection, which is I/O-intensive.
537 */
538#undef CONFIG_SYS_FLASH_EMPTY_INFO
539#endif
540
541/* pass open firmware flat tree */
542#define CONFIG_OF_LIBFDT
543#define CONFIG_OF_BOARD_SETUP
544#define CONFIG_OF_STDOUT_VIA_ALIAS
545
546/* new uImage format support */
547#define CONFIG_FIT
548#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
549
550/* I2C */
551#define CONFIG_SYS_I2C
552#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
553#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
554#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
555#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
556#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
557#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
558#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
559
560#define I2C_MUX_PCA_ADDR 0x77
561#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
562
563
564/* I2C bus multiplexer */
565#define I2C_MUX_CH_DEFAULT 0x8
566
567/*
568 * RTC configuration
569 */
570#define RTC
571#define CONFIG_RTC_DS1337 1
572#define CONFIG_SYS_I2C_RTC_ADDR 0x68
573
574/*
575 * eSPI - Enhanced SPI
576 */
577#define CONFIG_FSL_ESPI
578#define CONFIG_SPI_FLASH
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800579#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800580#define CONFIG_SPI_FLASH_STMICRO
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800581#elif defined(CONFIG_T1023RDB)
582#define CONFIG_SPI_FLASH_SPANSION
583#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800584#define CONFIG_CMD_SF
585#define CONFIG_SPI_FLASH_BAR
586#define CONFIG_SF_DEFAULT_SPEED 10000000
587#define CONFIG_SF_DEFAULT_MODE 0
588
589/*
590 * General PCIe
591 * Memory space is mapped 1-1, but I/O space must start from 0.
592 */
593#define CONFIG_PCI /* Enable PCI/PCIE */
594#define CONFIG_PCIE1 /* PCIE controler 1 */
595#define CONFIG_PCIE2 /* PCIE controler 2 */
596#define CONFIG_PCIE3 /* PCIE controler 3 */
597#ifdef CONFIG_PPC_T1040
598#define CONFIG_PCIE4 /* PCIE controler 4 */
599#endif
600#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
601#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
602#define CONFIG_PCI_INDIRECT_BRIDGE
603
604#ifdef CONFIG_PCI
605/* controller 1, direct to uli, tgtid 3, Base address 20000 */
606#ifdef CONFIG_PCIE1
607#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
608#ifdef CONFIG_PHYS_64BIT
609#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
610#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
611#else
612#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
613#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
614#endif
615#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
616#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
617#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
618#ifdef CONFIG_PHYS_64BIT
619#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
620#else
621#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
622#endif
623#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
624#endif
625
626/* controller 2, Slot 2, tgtid 2, Base address 201000 */
627#ifdef CONFIG_PCIE2
628#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
629#ifdef CONFIG_PHYS_64BIT
630#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
631#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
632#else
633#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
634#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
635#endif
636#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
637#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
638#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
639#ifdef CONFIG_PHYS_64BIT
640#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
641#else
642#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
643#endif
644#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
645#endif
646
647/* controller 3, Slot 1, tgtid 1, Base address 202000 */
648#ifdef CONFIG_PCIE3
649#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
650#ifdef CONFIG_PHYS_64BIT
651#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
652#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
653#else
654#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
655#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
656#endif
657#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
658#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
659#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
660#ifdef CONFIG_PHYS_64BIT
661#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
662#else
663#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
664#endif
665#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
666#endif
667
668/* controller 4, Base address 203000, to be removed */
669#ifdef CONFIG_PCIE4
670#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
671#ifdef CONFIG_PHYS_64BIT
672#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
673#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
674#else
675#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
676#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
677#endif
678#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
679#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
680#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
681#ifdef CONFIG_PHYS_64BIT
682#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
683#else
684#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
685#endif
686#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
687#endif
688
689#define CONFIG_PCI_PNP /* do pci plug-and-play */
690#define CONFIG_E1000
691#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
692#define CONFIG_DOS_PARTITION
693#endif /* CONFIG_PCI */
694
695/*
696 * USB
697 */
698#define CONFIG_HAS_FSL_DR_USB
699
700#ifdef CONFIG_HAS_FSL_DR_USB
701#define CONFIG_USB_EHCI
702#define CONFIG_CMD_USB
703#define CONFIG_USB_STORAGE
704#define CONFIG_USB_EHCI_FSL
705#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
706#define CONFIG_CMD_EXT2
707#endif
708
709/*
710 * SDHC
711 */
712#define CONFIG_MMC
713#ifdef CONFIG_MMC
714#define CONFIG_FSL_ESDHC
715#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
716#define CONFIG_CMD_MMC
717#define CONFIG_GENERIC_MMC
718#define CONFIG_CMD_EXT2
719#define CONFIG_CMD_FAT
720#define CONFIG_DOS_PARTITION
721#endif
722
723/* Qman/Bman */
724#ifndef CONFIG_NOBQFMAN
725#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500726#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800727#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
728#ifdef CONFIG_PHYS_64BIT
729#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
730#else
731#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
732#endif
733#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500734#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
735#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
736#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
737#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
738#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
739 CONFIG_SYS_BMAN_CENA_SIZE)
740#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
741#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500742#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800743#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
744#ifdef CONFIG_PHYS_64BIT
745#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
746#else
747#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
748#endif
749#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500750#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
751#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
752#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
753#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
754#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
755 CONFIG_SYS_QMAN_CENA_SIZE)
756#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
757#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800758
759#define CONFIG_SYS_DPAA_FMAN
760
761#define CONFIG_QE
762#define CONFIG_U_QE
763/* Default address of microcode for the Linux FMan driver */
764#if defined(CONFIG_SPIFLASH)
765/*
766 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
767 * env, so we got 0x110000.
768 */
769#define CONFIG_SYS_QE_FW_IN_SPIFLASH
770#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
771#define CONFIG_SYS_QE_FW_ADDR 0x130000
772#elif defined(CONFIG_SDCARD)
773/*
774 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
775 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
776 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
777 */
778#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
779#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
780#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
781#elif defined(CONFIG_NAND)
782#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800783#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800784#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
785#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800786#elif defined(CONFIG_T1023RDB)
787#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
788#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
789#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800790#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
791/*
792 * Slave has no ucode locally, it can fetch this from remote. When implementing
793 * in two corenet boards, slave's ucode could be stored in master's memory
794 * space, the address can be mapped from slave TLB->slave LAW->
795 * slave SRIO or PCIE outbound window->master inbound window->
796 * master LAW->the ucode address in master's memory space.
797 */
798#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
799#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
800#else
801#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
802#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
803#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
804#endif
805#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
806#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
807#endif /* CONFIG_NOBQFMAN */
808
809#ifdef CONFIG_SYS_DPAA_FMAN
810#define CONFIG_FMAN_ENET
811#define CONFIG_PHYLIB_10G
812#define CONFIG_PHY_REALTEK
Shengzhou Liue26416a2014-12-17 16:51:08 +0800813#define CONFIG_PHY_AQUANTIA
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800814#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800815#define RGMII_PHY1_ADDR 0x2
816#define RGMII_PHY2_ADDR 0x6
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800817#define SGMII_AQR_PHY_ADDR 0x2
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800818#define FM1_10GEC1_PHY_ADDR 0x1
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800819#elif defined(CONFIG_T1023RDB)
820#define RGMII_PHY1_ADDR 0x1
821#define SGMII_RTK_PHY_ADDR 0x3
822#define SGMII_AQR_PHY_ADDR 0x2
823#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800824#endif
825
826#ifdef CONFIG_FMAN_ENET
827#define CONFIG_MII /* MII PHY management */
828#define CONFIG_ETHPRIME "FM1@DTSEC4"
829#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
830#endif
831
832/*
833 * Dynamic MTD Partition support with mtdparts
834 */
835#ifndef CONFIG_SYS_NO_FLASH
836#define CONFIG_MTD_DEVICE
837#define CONFIG_MTD_PARTITIONS
838#define CONFIG_CMD_MTDPARTS
839#define CONFIG_FLASH_CFI_MTD
840#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
841 "spi0=spife110000.1"
842#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
843 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
844 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
845 "1m(uboot),5m(kernel),128k(dtb),-(user)"
846#endif
847
848/*
849 * Environment
850 */
851#define CONFIG_LOADS_ECHO /* echo on for serial download */
852#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
853
854/*
855 * Command line configuration.
856 */
857#include <config_cmd_default.h>
858
859#define CONFIG_CMD_DATE
860#define CONFIG_CMD_DHCP
861#define CONFIG_CMD_EEPROM
862#define CONFIG_CMD_ELF
863#define CONFIG_CMD_ERRATA
864#define CONFIG_CMD_GREPENV
865#define CONFIG_CMD_IRQ
866#define CONFIG_CMD_I2C
867#define CONFIG_CMD_MII
868#define CONFIG_CMD_PING
869#define CONFIG_CMD_ECHO
870#define CONFIG_CMD_REGINFO
871#define CONFIG_CMD_SETEXPR
872#define CONFIG_CMD_BDI
873
874#ifdef CONFIG_PCI
875#define CONFIG_CMD_PCI
876#define CONFIG_CMD_NET
877#endif
878
879/*
880 * Miscellaneous configurable options
881 */
882#define CONFIG_SYS_LONGHELP /* undef to save memory */
883#define CONFIG_CMDLINE_EDITING /* Command-line editing */
884#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
885#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
886#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
887#ifdef CONFIG_CMD_KGDB
888#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
889#else
890#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
891#endif
892#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
893#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
894#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
895
896/*
897 * For booting Linux, the board info and command line data
898 * have to be in the first 64 MB of memory, since this is
899 * the maximum mapped by the Linux kernel during initialization.
900 */
901#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
902#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
903
904#ifdef CONFIG_CMD_KGDB
905#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
906#endif
907
908/*
909 * Environment Configuration
910 */
911#define CONFIG_ROOTPATH "/opt/nfsroot"
912#define CONFIG_BOOTFILE "uImage"
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800913#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800914#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
915#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
916#define CONFIG_BAUDRATE 115200
917#define __USB_PHY_TYPE utmi
918
919#ifdef CONFIG_PPC_T1024
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800920#define CONFIG_BOARDNAME t1024rdb
921#define BANK_INTLV cs0_cs1
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800922#else
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800923#define CONFIG_BOARDNAME t1023rdb
924#define BANK_INTLV null
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800925#endif
926
927#define CONFIG_EXTRA_ENV_SETTINGS \
928 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800929 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800930 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
931 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
932 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
933 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
934 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
935 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
936 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
937 "netdev=eth0\0" \
938 "tftpflash=tftpboot $loadaddr $uboot && " \
939 "protect off $ubootaddr +$filesize && " \
940 "erase $ubootaddr +$filesize && " \
941 "cp.b $loadaddr $ubootaddr $filesize && " \
942 "protect on $ubootaddr +$filesize && " \
943 "cmp.b $loadaddr $ubootaddr $filesize\0" \
944 "consoledev=ttyS0\0" \
945 "ramdiskaddr=2000000\0" \
946 "fdtaddr=c00000\0" \
947 "bdev=sda3\0"
948
949#define CONFIG_LINUX \
950 "setenv bootargs root=/dev/ram rw " \
951 "console=$consoledev,$baudrate $othbootargs;" \
952 "setenv ramdiskaddr 0x02000000;" \
953 "setenv fdtaddr 0x00c00000;" \
954 "setenv loadaddr 0x1000000;" \
955 "bootm $loadaddr $ramdiskaddr $fdtaddr"
956
957
958#define CONFIG_NFSBOOTCOMMAND \
959 "setenv bootargs root=/dev/nfs rw " \
960 "nfsroot=$serverip:$rootpath " \
961 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
962 "console=$consoledev,$baudrate $othbootargs;" \
963 "tftp $loadaddr $bootfile;" \
964 "tftp $fdtaddr $fdtfile;" \
965 "bootm $loadaddr - $fdtaddr"
966
967#define CONFIG_BOOTCOMMAND CONFIG_LINUX
968
969#ifdef CONFIG_SECURE_BOOT
970#include <asm/fsl_secure_boot.h>
971#endif
972
973#endif /* __T1024RDB_H */