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Joe Hamman11c45eb2007-12-13 06:45:08 -06001/*
2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 *
5 * Copyright 2004, 2007 Freescale Semiconductor.
6 *
7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <pci.h>
30#include <asm/processor.h>
31#include <asm/immap_85xx.h>
32#include <asm/immap_fsl_pci.h>
Kumar Gala33b90792008-08-26 23:15:28 -050033#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060034#include <spd_sdram.h>
Joe Hamman11c45eb2007-12-13 06:45:08 -060035#include <miiphy.h>
36#include <libfdt.h>
37#include <fdt_support.h>
38
39#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
40extern void ddr_enable_ecc(unsigned int dram_size);
41#endif
42
43DECLARE_GLOBAL_DATA_PTR;
44
Joe Hamman11c45eb2007-12-13 06:45:08 -060045void local_bus_init(void);
46void sdram_init(void);
47long int fixed_sdram (void);
48
49int board_early_init_f (void)
50{
51 return 0;
52}
53
54int checkboard (void)
55{
56 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
57 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
Jean-Christophe PLAGNIOL-VILLARD347b7932008-02-17 22:56:17 +010058 volatile u_char *rev= (void *)CFG_BD_REV;
Joe Hamman11c45eb2007-12-13 06:45:08 -060059
60 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
Jean-Christophe PLAGNIOL-VILLARD347b7932008-02-17 22:56:17 +010061 (*rev) >> 4);
Joe Hamman11c45eb2007-12-13 06:45:08 -060062
63 /*
64 * Initialize local bus.
65 */
66 local_bus_init ();
67
68 /*
69 * Fix CPU2 errata: A core hang possible while executing a
70 * msync instruction and a snoopable transaction from an I/O
71 * master tagged to make quick forward progress is present.
72 */
73 ecm->eebpcr |= (1 << 16);
74
75 /*
76 * Hack TSEC 3 and 4 IO voltages.
77 */
78 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
79
80 ecm->eedr = 0xffffffff; /* clear ecm errors */
81 ecm->eeer = 0xffffffff; /* enable ecm errors */
82 return 0;
83}
84
Becky Bruce9973e3c2008-06-09 16:03:40 -050085phys_size_t
Joe Hamman11c45eb2007-12-13 06:45:08 -060086initdram(int board_type)
87{
88 long dram_size = 0;
89
90 puts("Initializing\n");
91
92#if defined(CONFIG_DDR_DLL)
93 {
94 /*
95 * Work around to stabilize DDR DLL MSYNC_IN.
96 * Errata DDR9 seems to have been fixed.
97 * This is now the workaround for Errata DDR11:
98 * Override DLL = 1, Course Adj = 1, Tap Select = 0
99 */
100
101 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
102
103 gur->ddrdllcr = 0x81000000;
104 asm("sync;isync;msync");
105 udelay(200);
106 }
107#endif
108
109#if defined(CONFIG_SPD_EEPROM)
Kumar Gala33b90792008-08-26 23:15:28 -0500110 dram_size = fsl_ddr_sdram();
111 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
112 dram_size *= 0x100000;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600113#else
114 dram_size = fixed_sdram ();
115#endif
116
117#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
118 /*
119 * Initialize and enable DDR ECC.
120 */
121 ddr_enable_ecc(dram_size);
122#endif
123 /*
124 * SDRAM Initialization
125 */
126 sdram_init();
127
128 puts(" DDR: ");
129 return dram_size;
130}
131
132/*
133 * Initialize Local Bus
134 */
135void
136local_bus_init(void)
137{
138 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
139 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
140
141 uint clkdiv;
142 uint lbc_hz;
143 sys_info_t sysinfo;
144
145 get_sys_info(&sysinfo);
146 clkdiv = (lbc->lcrr & 0x0f) * 2;
147 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
148
149 gur->lbiuiplldcr1 = 0x00078080;
150 if (clkdiv == 16) {
151 gur->lbiuiplldcr0 = 0x7c0f1bf0;
152 } else if (clkdiv == 8) {
153 gur->lbiuiplldcr0 = 0x6c0f1bf0;
154 } else if (clkdiv == 4) {
155 gur->lbiuiplldcr0 = 0x5c0f1bf0;
156 }
157
158 lbc->lcrr |= 0x00030000;
159
160 asm("sync;isync;msync");
161
162 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
163 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
164}
165
166/*
167 * Initialize SDRAM memory on the Local Bus.
168 */
169void
170sdram_init(void)
171{
172#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
173
174 uint idx;
175 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
176 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
177 uint lsdmr_common;
178
179 puts(" SDRAM: ");
180
181 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
182
183 /*
184 * Setup SDRAM Base and Option Registers
185 */
186 lbc->or3 = CFG_OR3_PRELIM;
187 asm("msync");
188
189 lbc->br3 = CFG_BR3_PRELIM;
190 asm("msync");
191
192 lbc->lbcr = CFG_LBC_LBCR;
193 asm("msync");
194
195
196 lbc->lsrt = CFG_LBC_LSRT;
197 lbc->mrtpr = CFG_LBC_MRTPR;
198 asm("msync");
199
200 /*
201 * MPC8548 uses "new" 15-16 style addressing.
202 */
203 lsdmr_common = CFG_LBC_LSDMR_COMMON;
204 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
205
206 /*
207 * Issue PRECHARGE ALL command.
208 */
209 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
210 asm("sync;msync");
211 *sdram_addr = 0xff;
212 ppcDcbf((unsigned long) sdram_addr);
213 udelay(100);
214
215 /*
216 * Issue 8 AUTO REFRESH commands.
217 */
218 for (idx = 0; idx < 8; idx++) {
219 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
220 asm("sync;msync");
221 *sdram_addr = 0xff;
222 ppcDcbf((unsigned long) sdram_addr);
223 udelay(100);
224 }
225
226 /*
227 * Issue 8 MODE-set command.
228 */
229 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
230 asm("sync;msync");
231 *sdram_addr = 0xff;
232 ppcDcbf((unsigned long) sdram_addr);
233 udelay(100);
234
235 /*
236 * Issue NORMAL OP command.
237 */
238 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
239 asm("sync;msync");
240 *sdram_addr = 0xff;
241 ppcDcbf((unsigned long) sdram_addr);
242 udelay(200); /* Overkill. Must wait > 200 bus cycles */
243
244#endif /* enable SDRAM init */
245}
246
247#if defined(CFG_DRAM_TEST)
248int
249testdram(void)
250{
251 uint *pstart = (uint *) CFG_MEMTEST_START;
252 uint *pend = (uint *) CFG_MEMTEST_END;
253 uint *p;
254
255 printf("Testing DRAM from 0x%08x to 0x%08x\n",
256 CFG_MEMTEST_START,
257 CFG_MEMTEST_END);
258
259 printf("DRAM test phase 1:\n");
260 for (p = pstart; p < pend; p++)
261 *p = 0xaaaaaaaa;
262
263 for (p = pstart; p < pend; p++) {
264 if (*p != 0xaaaaaaaa) {
265 printf ("DRAM test fails at: %08x\n", (uint) p);
266 return 1;
267 }
268 }
269
270 printf("DRAM test phase 2:\n");
271 for (p = pstart; p < pend; p++)
272 *p = 0x55555555;
273
274 for (p = pstart; p < pend; p++) {
275 if (*p != 0x55555555) {
276 printf ("DRAM test fails at: %08x\n", (uint) p);
277 return 1;
278 }
279 }
280
281 printf("DRAM test passed.\n");
282 return 0;
283}
284#endif
285
286#if !defined(CONFIG_SPD_EEPROM)
287/*************************************************************************
288 * fixed_sdram init -- doesn't use serial presence detect.
289 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
290 ************************************************************************/
291long int fixed_sdram (void)
292{
293 #define CFG_DDR_CONTROL 0xc300c000
294
295 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
296
297 ddr->cs0_bnds = 0x0000007f;
298 ddr->cs1_bnds = 0x008000ff;
299 ddr->cs2_bnds = 0x00000000;
300 ddr->cs3_bnds = 0x00000000;
301 ddr->cs0_config = 0x80010101;
302 ddr->cs1_config = 0x80010101;
303 ddr->cs2_config = 0x00000000;
304 ddr->cs3_config = 0x00000000;
Kumar Gala45239cf2008-04-29 10:27:08 -0500305 ddr->timing_cfg_3 = 0x00000000;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600306 ddr->timing_cfg_0 = 0x00220802;
307 ddr->timing_cfg_1 = 0x38377322;
308 ddr->timing_cfg_2 = 0x0fa044C7;
309 ddr->sdram_cfg = 0x4300C000;
310 ddr->sdram_cfg_2 = 0x24401000;
311 ddr->sdram_mode = 0x23C00542;
312 ddr->sdram_mode_2 = 0x00000000;
313 ddr->sdram_interval = 0x05080100;
314 ddr->sdram_md_cntl = 0x00000000;
315 ddr->sdram_data_init = 0x00000000;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200316 ddr->sdram_clk_cntl = 0x03800000;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600317 asm("sync;isync;msync");
318 udelay(500);
319
320 #if defined (CONFIG_DDR_ECC)
321 /* Enable ECC checking */
322 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
323 #else
324 ddr->sdram_cfg = CFG_DDR_CONTROL;
325 #endif
326
327 return CFG_SDRAM_SIZE * 1024 * 1024;
328}
329#endif
330
331#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
332/* For some reason the Tundra PCI bridge shows up on itself as a
333 * different device. Work around that by refusing to configure it.
334 */
335void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
336
337static struct pci_config_table pci_sbc8548_config_table[] = {
338 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
339 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
340 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
341 mpc85xx_config_via_usbide, {0,0,0}},
342 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
343 mpc85xx_config_via_usb, {0,0,0}},
344 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
345 mpc85xx_config_via_usb2, {0,0,0}},
346 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
347 mpc85xx_config_via_power, {0,0,0}},
348 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
349 mpc85xx_config_via_ac97, {0,0,0}},
350 {},
351};
352
353static struct pci_controller pci1_hose = {
354 config_table: pci_sbc8548_config_table};
355#endif /* CONFIG_PCI */
356
357#ifdef CONFIG_PCI2
358static struct pci_controller pci2_hose;
359#endif /* CONFIG_PCI2 */
360
361#ifdef CONFIG_PCIE1
362static struct pci_controller pcie1_hose;
363#endif /* CONFIG_PCIE1 */
364
365int first_free_busno=0;
366
367void
368pci_init_board(void)
369{
370 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
371
372#ifdef CONFIG_PCI1
373{
374 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
375 extern void fsl_pci_init(struct pci_controller *hose);
376 struct pci_controller *hose = &pci1_hose;
377 struct pci_config_table *table;
378
379 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
380 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
381 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
382
383 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
384
385 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
386
387 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
388 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
389 (pci_32) ? 32 : 64,
390 (pci_speed == 33333000) ? "33" :
391 (pci_speed == 66666000) ? "66" : "unknown",
392 pci_clk_sel ? "sync" : "async",
393 pci_agent ? "agent" : "host",
394 pci_arb ? "arbiter" : "external-arbiter"
395 );
396
397
398 /* inbound */
399 pci_set_region(hose->regions + 0,
400 CFG_PCI_MEMORY_BUS,
401 CFG_PCI_MEMORY_PHYS,
402 CFG_PCI_MEMORY_SIZE,
403 PCI_REGION_MEM | PCI_REGION_MEMORY);
404
405
406 /* outbound memory */
407 pci_set_region(hose->regions + 1,
408 CFG_PCI1_MEM_BASE,
409 CFG_PCI1_MEM_PHYS,
410 CFG_PCI1_MEM_SIZE,
411 PCI_REGION_MEM);
412
413 /* outbound io */
414 pci_set_region(hose->regions + 2,
415 CFG_PCI1_IO_BASE,
416 CFG_PCI1_IO_PHYS,
417 CFG_PCI1_IO_SIZE,
418 PCI_REGION_IO);
419 hose->region_count = 3;
420
421 /* relocate config table pointers */
422 hose->config_table = \
423 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
424 for (table = hose->config_table; table && table->vendor; table++)
425 table->config_device += gd->reloc_off;
426
427 hose->first_busno=first_free_busno;
428 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
429
430 fsl_pci_init(hose);
431 first_free_busno=hose->last_busno+1;
432 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
433#ifdef CONFIG_PCIX_CHECK
434 if (!(gur->pordevsr & PORDEVSR_PCI)) {
435 /* PCI-X init */
436 if (CONFIG_SYS_CLK_FREQ < 66000000)
437 printf("PCI-X will only work at 66 MHz\n");
438
439 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
440 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
441 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
442 }
443#endif
444 } else {
445 printf (" PCI: disabled\n");
446 }
447}
448#else
449 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
450#endif
451
452#ifdef CONFIG_PCI2
453{
454 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
455 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
456 if (pci_dual) {
457 printf (" PCI2: 32 bit, 66 MHz, %s\n",
458 pci2_clk_sel ? "sync" : "async");
459 } else {
460 printf (" PCI2: disabled\n");
461 }
462}
463#else
464 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
465#endif /* CONFIG_PCI2 */
466
467#ifdef CONFIG_PCIE1
468{
469 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
470 extern void fsl_pci_init(struct pci_controller *hose);
471 struct pci_controller *hose = &pcie1_hose;
472 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
473
474 int pcie_configured = io_sel >= 1;
475
476 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
477 printf ("\n PCIE connected to slot as %s (base address %x)",
478 pcie_ep ? "End Point" : "Root Complex",
479 (uint)pci);
480
481 if (pci->pme_msg_det) {
482 pci->pme_msg_det = 0xffffffff;
483 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
484 }
485 printf ("\n");
486
487 /* inbound */
488 pci_set_region(hose->regions + 0,
489 CFG_PCI_MEMORY_BUS,
490 CFG_PCI_MEMORY_PHYS,
491 CFG_PCI_MEMORY_SIZE,
492 PCI_REGION_MEM | PCI_REGION_MEMORY);
493
494 /* outbound memory */
495 pci_set_region(hose->regions + 1,
496 CFG_PCIE1_MEM_BASE,
497 CFG_PCIE1_MEM_PHYS,
498 CFG_PCIE1_MEM_SIZE,
499 PCI_REGION_MEM);
500
501 /* outbound io */
502 pci_set_region(hose->regions + 2,
503 CFG_PCIE1_IO_BASE,
504 CFG_PCIE1_IO_PHYS,
505 CFG_PCIE1_IO_SIZE,
506 PCI_REGION_IO);
507
508 hose->region_count = 3;
509
510 hose->first_busno=first_free_busno;
511 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
512
513 fsl_pci_init(hose);
514 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
515
516 first_free_busno=hose->last_busno+1;
517
518 } else {
519 printf (" PCIE: disabled\n");
520 }
521 }
522#else
523 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
524#endif
525
526}
527
528int last_stage_init(void)
529{
530 return 0;
531}
532
533#if defined(CONFIG_OF_BOARD_SETUP)
534void
535ft_pci_setup(void *blob, bd_t *bd)
536{
537 int node, tmp[2];
Joe Hamman11c45eb2007-12-13 06:45:08 -0600538
539 node = fdt_path_offset(blob, "/aliases");
540 tmp[0] = 0;
541 if (node >= 0) {
542#ifdef CONFIG_PCI1
Jean-Christophe PLAGNIOL-VILLARD347b7932008-02-17 22:56:17 +0100543 const char *path;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600544 path = fdt_getprop(blob, node, "pci0", NULL);
545 if (path) {
546 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
547 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
548 }
549#endif
550#ifdef CONFIG_PCIE1
Jean-Christophe PLAGNIOL-VILLARD347b7932008-02-17 22:56:17 +0100551 const char *path;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600552 path = fdt_getprop(blob, node, "pci1", NULL);
553 if (path) {
554 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
555 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
556 }
557#endif
558 }
559}
560#endif
561
562#if defined(CONFIG_OF_BOARD_SETUP)
563void
564ft_board_setup(void *blob, bd_t *bd)
565{
566 ft_cpu_setup(blob, bd);
567#ifdef CONFIG_PCI
568 ft_pci_setup(blob, bd);
569#endif
570}
571#endif