blob: 729205f7129573198f8ff259d36b40f83866465b [file] [log] [blame]
Wang Huanc8a7d9d2014-09-05 13:52:45 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#include <config_cmd_default.h>
11
12#define CONFIG_LS102XA
13
14#define CONFIG_SYS_GENERIC_BOARD
15
16#define CONFIG_DISPLAY_CPUINFO
17#define CONFIG_DISPLAY_BOARDINFO
18
19#define CONFIG_SKIP_LOWLEVEL_INIT
20#define CONFIG_BOARD_EARLY_INIT_F
21
22/*
23 * Size of malloc() pool
24 */
25#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
26
27#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
28#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
29
30/*
31 * Generic Timer Definitions
32 */
33#define GENERIC_TIMER_CLK 12500000
34
35#define CONFIG_SYS_CLK_FREQ 100000000
36#define CONFIG_DDR_CLK_FREQ 100000000
37
Alison Wang8415bb62014-12-03 15:00:48 +080038#ifdef CONFIG_RAMBOOT_PBL
39#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
40#endif
41
42#ifdef CONFIG_SD_BOOT
43#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
44#define CONFIG_SPL_FRAMEWORK
45#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
46#define CONFIG_SPL_LIBCOMMON_SUPPORT
47#define CONFIG_SPL_LIBGENERIC_SUPPORT
48#define CONFIG_SPL_ENV_SUPPORT
49#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
50#define CONFIG_SPL_I2C_SUPPORT
51#define CONFIG_SPL_WATCHDOG_SUPPORT
52#define CONFIG_SPL_SERIAL_SUPPORT
53#define CONFIG_SPL_MMC_SUPPORT
54#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
55#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
56
57#define CONFIG_SPL_TEXT_BASE 0x10000000
58#define CONFIG_SPL_MAX_SIZE 0x1a000
59#define CONFIG_SPL_STACK 0x1001d000
60#define CONFIG_SPL_PAD_TO 0x1c000
61#define CONFIG_SYS_TEXT_BASE 0x82000000
62
63#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
64#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
65#define CONFIG_SPL_BSS_START_ADDR 0x80100000
66#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
67#define CONFIG_SYS_MONITOR_LEN 0x80000
68#endif
69
Alison Wangd612f0a2014-12-09 17:38:02 +080070#ifdef CONFIG_QSPI_BOOT
71#define CONFIG_SYS_TEXT_BASE 0x40010000
72#define CONFIG_SYS_NO_FLASH
73#endif
74
Wang Huanc8a7d9d2014-09-05 13:52:45 +080075#ifndef CONFIG_SYS_TEXT_BASE
76#define CONFIG_SYS_TEXT_BASE 0x67f80000
77#endif
78
79#define CONFIG_NR_DRAM_BANKS 1
80#define PHYS_SDRAM 0x80000000
81#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
82
83#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
84#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
85
86#define CONFIG_SYS_HAS_SERDES
87
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053088#define CONFIG_FSL_CAAM /* Enable CAAM */
89
Alison Wang4c59ab92014-12-09 17:37:49 +080090#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
91 !defined(CONFIG_QSPI_BOOT)
Zhao Qiangeaa859e2014-09-26 16:25:33 +080092#define CONFIG_U_QE
93#endif
94
Wang Huanc8a7d9d2014-09-05 13:52:45 +080095/*
96 * IFC Definitions
97 */
Alison Wangd612f0a2014-12-09 17:38:02 +080098#ifndef CONFIG_QSPI_BOOT
Wang Huanc8a7d9d2014-09-05 13:52:45 +080099#define CONFIG_FSL_IFC
100#define CONFIG_SYS_FLASH_BASE 0x60000000
101#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
102
103#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
104#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
105 CSPR_PORT_SIZE_16 | \
106 CSPR_MSEL_NOR | \
107 CSPR_V)
108#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
109
110/* NOR Flash Timing Params */
111#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
112 CSOR_NOR_TRHZ_80)
113#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
114 FTIM0_NOR_TEADC(0x5) | \
115 FTIM0_NOR_TAVDS(0x0) | \
116 FTIM0_NOR_TEAHC(0x5))
117#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
118 FTIM1_NOR_TRAD_NOR(0x1A) | \
119 FTIM1_NOR_TSEQRAD_NOR(0x13))
120#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
121 FTIM2_NOR_TCH(0x4) | \
122 FTIM2_NOR_TWP(0x1c) | \
123 FTIM2_NOR_TWPH(0x0e))
124#define CONFIG_SYS_NOR_FTIM3 0
125
126#define CONFIG_FLASH_CFI_DRIVER
127#define CONFIG_SYS_FLASH_CFI
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
129#define CONFIG_SYS_FLASH_QUIET_TEST
130#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
131
132#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
133#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
134#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
135#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
136
137#define CONFIG_SYS_FLASH_EMPTY_INFO
138#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
139
140#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800141#define CONFIG_SYS_WRITE_SWAPPED_DATA
Alison Wangd612f0a2014-12-09 17:38:02 +0800142#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800143
144/* CPLD */
145
146#define CONFIG_SYS_CPLD_BASE 0x7fb00000
147#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
148
149#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
150#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
151 CSPR_PORT_SIZE_8 | \
152 CSPR_MSEL_GPCM | \
153 CSPR_V)
154#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
155#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
156 CSOR_NOR_NOR_MODE_AVD_NOR | \
157 CSOR_NOR_TRHZ_80)
158
159/* CPLD Timing parameters for IFC GPCM */
160#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
161 FTIM0_GPCM_TEADC(0xf) | \
162 FTIM0_GPCM_TEAHC(0xf))
163#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
164 FTIM1_GPCM_TRAD(0x3f))
165#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
166 FTIM2_GPCM_TCH(0xf) | \
167 FTIM2_GPCM_TWP(0xff))
168#define CONFIG_SYS_FPGA_FTIM3 0x0
169#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
170#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
171#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
172#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
173#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
174#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
175#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
176#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
177#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
178#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
179#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
180#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
181#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
182#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
183#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
184#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
185
186/*
187 * Serial Port
188 */
Alison Wang55d53ab2015-01-04 15:30:59 +0800189#ifdef CONFIG_LPUART
190#define CONFIG_FSL_LPUART
191#define CONFIG_LPUART_32B_REG
192#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800193#define CONFIG_CONS_INDEX 1
194#define CONFIG_SYS_NS16550
195#define CONFIG_SYS_NS16550_SERIAL
196#define CONFIG_SYS_NS16550_REG_SIZE 1
197#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang55d53ab2015-01-04 15:30:59 +0800198#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800199
200#define CONFIG_BAUDRATE 115200
201
202/*
203 * I2C
204 */
205#define CONFIG_CMD_I2C
206#define CONFIG_SYS_I2C
207#define CONFIG_SYS_I2C_MXC
York Sunf8cb1012015-03-20 10:20:40 -0700208#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800209
Alison Wang5175a282014-10-17 15:26:35 +0800210/* EEPROM */
211#ifndef CONFIG_SD_BOOT
212#define CONFIG_ID_EEPROM
213#define CONFIG_SYS_I2C_EEPROM_NXID
214#define CONFIG_SYS_EEPROM_BUS_NUM 1
215#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
216#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
217#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
218#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
219#endif
220
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800221/*
222 * MMC
223 */
224#define CONFIG_MMC
225#define CONFIG_CMD_MMC
226#define CONFIG_FSL_ESDHC
227#define CONFIG_GENERIC_MMC
228
Alison Wang8251ed22014-12-09 17:37:34 +0800229#define CONFIG_CMD_FAT
230#define CONFIG_DOS_PARTITION
231
Alison Wangd612f0a2014-12-09 17:38:02 +0800232/* QSPI */
233#ifdef CONFIG_QSPI_BOOT
234#define CONFIG_FSL_QSPI
235#define QSPI0_AMBA_BASE 0x40000000
236#define FSL_QSPI_FLASH_SIZE (1 << 24)
237#define FSL_QSPI_FLASH_NUM 2
238
239#define CONFIG_CMD_SF
240#define CONFIG_SPI_FLASH
241#define CONFIG_SPI_FLASH_STMICRO
242#endif
243
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800244/*
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800245 * Video
246 */
247#define CONFIG_FSL_DCU_FB
248
249#ifdef CONFIG_FSL_DCU_FB
250#define CONFIG_VIDEO
251#define CONFIG_CMD_BMP
252#define CONFIG_CFB_CONSOLE
253#define CONFIG_VGA_AS_SINGLE_DEVICE
254#define CONFIG_VIDEO_LOGO
255#define CONFIG_VIDEO_BMP_LOGO
256
257#define CONFIG_FSL_DCU_SII9022A
258#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
259#define CONFIG_SYS_I2C_DVI_ADDR 0x39
260#endif
261
262/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800263 * eTSEC
264 */
265#define CONFIG_TSEC_ENET
266
267#ifdef CONFIG_TSEC_ENET
268#define CONFIG_MII
269#define CONFIG_MII_DEFAULT_TSEC 1
270#define CONFIG_TSEC1 1
271#define CONFIG_TSEC1_NAME "eTSEC1"
272#define CONFIG_TSEC2 1
273#define CONFIG_TSEC2_NAME "eTSEC2"
274#define CONFIG_TSEC3 1
275#define CONFIG_TSEC3_NAME "eTSEC3"
276
277#define TSEC1_PHY_ADDR 2
278#define TSEC2_PHY_ADDR 0
279#define TSEC3_PHY_ADDR 1
280
281#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
282#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
283#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
284
285#define TSEC1_PHYIDX 0
286#define TSEC2_PHYIDX 0
287#define TSEC3_PHYIDX 0
288
289#define CONFIG_ETHPRIME "eTSEC1"
290
291#define CONFIG_PHY_GIGE
292#define CONFIG_PHYLIB
293#define CONFIG_PHY_ATHEROS
294
295#define CONFIG_HAS_ETH0
296#define CONFIG_HAS_ETH1
297#define CONFIG_HAS_ETH2
298#endif
299
Minghuan Lianda419022014-10-31 13:43:44 +0800300/* PCIe */
301#define CONFIG_PCI /* Enable PCI/PCIE */
302#define CONFIG_PCIE1 /* PCIE controler 1 */
303#define CONFIG_PCIE2 /* PCIE controler 2 */
304#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
305#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
306
Minghuan Lian180b8682015-01-21 17:29:19 +0800307#define CONFIG_SYS_PCI_64BIT
308
309#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
310#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
311#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
312#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
313
314#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
315#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
316#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
317
318#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
319#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
320#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
321
322#ifdef CONFIG_PCI
323#define CONFIG_NET_MULTI
324#define CONFIG_PCI_PNP
325#define CONFIG_E1000
326#define CONFIG_PCI_SCAN_SHOW
327#define CONFIG_CMD_PCI
328#define CONFIG_CMD_NET
329#endif
330
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800331#define CONFIG_CMD_PING
332#define CONFIG_CMD_DHCP
333#define CONFIG_CMD_MII
334#define CONFIG_CMD_NET
335
336#define CONFIG_CMDLINE_TAG
337#define CONFIG_CMDLINE_EDITING
Alison Wang8415bb62014-12-03 15:00:48 +0800338
Alison Wangd612f0a2014-12-09 17:38:02 +0800339#ifdef CONFIG_QSPI_BOOT
340#undef CONFIG_CMD_IMLS
341#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800342#define CONFIG_CMD_IMLS
Alison Wangd612f0a2014-12-09 17:38:02 +0800343#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800344
Xiubo Li1a2826f2014-11-21 17:40:57 +0800345#define CONFIG_ARMV7_NONSEC
346#define CONFIG_ARMV7_VIRT
347#define CONFIG_PEN_ADDR_BIG_ENDIAN
Xiubo Lie87f3b32014-11-21 17:40:58 +0800348#define CONFIG_LS102XA_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800349#define CONFIG_SMP_PEN_ADDR 0x01ee0200
350#define CONFIG_TIMER_CLK_FREQ 12500000
351#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
352
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800353#define CONFIG_HWCONFIG
354#define HWCONFIG_BUFFER_SIZE 128
355
356#define CONFIG_BOOTDELAY 3
357
Alison Wang55d53ab2015-01-04 15:30:59 +0800358#ifdef CONFIG_LPUART
359#define CONFIG_EXTRA_ENV_SETTINGS \
360 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
361 "initrd_high=0xcfffffff\0" \
362 "fdt_high=0xcfffffff\0"
363#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800364#define CONFIG_EXTRA_ENV_SETTINGS \
365 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
366 "initrd_high=0xcfffffff\0" \
367 "fdt_high=0xcfffffff\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800368#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800369
370/*
371 * Miscellaneous configurable options
372 */
373#define CONFIG_SYS_LONGHELP /* undef to save memory */
374#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
375#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800376#define CONFIG_AUTO_COMPLETE
377#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
378#define CONFIG_SYS_PBSIZE \
379 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
380#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
381#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
382
383#define CONFIG_CMD_ENV_EXISTS
384#define CONFIG_CMD_GREPENV
385#define CONFIG_CMD_MEMINFO
386#define CONFIG_CMD_MEMTEST
387#define CONFIG_SYS_MEMTEST_START 0x80000000
388#define CONFIG_SYS_MEMTEST_END 0x9fffffff
389
390#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800391
Xiubo Li660673a2014-11-21 17:40:59 +0800392#define CONFIG_LS102XA_STREAM_ID
393
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800394/*
395 * Stack sizes
396 * The stack sizes are set up in start.S using the settings below
397 */
398#define CONFIG_STACKSIZE (30 * 1024)
399
400#define CONFIG_SYS_INIT_SP_OFFSET \
401 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
402#define CONFIG_SYS_INIT_SP_ADDR \
403 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
404
Alison Wang8415bb62014-12-03 15:00:48 +0800405#ifdef CONFIG_SPL_BUILD
406#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
407#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800408#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang8415bb62014-12-03 15:00:48 +0800409#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800410
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800411#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
412
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800413/*
414 * Environment
415 */
416#define CONFIG_ENV_OVERWRITE
417
Alison Wang8415bb62014-12-03 15:00:48 +0800418#if defined(CONFIG_SD_BOOT)
419#define CONFIG_ENV_OFFSET 0x100000
420#define CONFIG_ENV_IS_IN_MMC
421#define CONFIG_SYS_MMC_ENV_DEV 0
422#define CONFIG_ENV_SIZE 0x20000
Alison Wangd612f0a2014-12-09 17:38:02 +0800423#elif defined(CONFIG_QSPI_BOOT)
424#define CONFIG_ENV_IS_IN_SPI_FLASH
425#define CONFIG_ENV_SIZE 0x2000
426#define CONFIG_ENV_OFFSET 0x100000
427#define CONFIG_ENV_SECT_SIZE 0x10000
Alison Wang8415bb62014-12-03 15:00:48 +0800428#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800429#define CONFIG_ENV_IS_IN_FLASH
430#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
431#define CONFIG_ENV_SIZE 0x20000
432#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Alison Wang8415bb62014-12-03 15:00:48 +0800433#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800434
435#define CONFIG_OF_LIBFDT
436#define CONFIG_OF_BOARD_SETUP
437#define CONFIG_CMD_BOOTZ
438
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530439#define CONFIG_MISC_INIT_R
440
441/* Hash command with SHA acceleration supported in hardware */
442#define CONFIG_CMD_HASH
443#define CONFIG_SHA_HW_ACCEL
444
Ruchika Guptaba474022014-10-07 15:48:47 +0530445#ifdef CONFIG_SECURE_BOOT
446#define CONFIG_CMD_BLOB
447#endif
448
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800449#endif