commit 084a4e8787e0391bd15c657515a7a82c0fe10d1a
author sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Mon Nov 22 20:51:49 2004 +0000
committer sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Mon Nov 22 20:51:49 2004 +0000
tree f3d5b8e6ea8fc35c18d34f4ffab85d2aa0b17b3d
parent 9f649aa98a89c7d4d26267ce4a0cdd40a6e3aeb9

Fix some linking problems which were preventing memcheck from starting.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@3069 a5019735-40e9-0310-863c-91ae7b9d1cf9

coregrind/x86/state.c

diff --git a/coregrind/x86/state.c b/coregrind/x86/state.c
index 2cf446a..68bdb0d 100644
--- a/coregrind/x86/state.c
+++ b/coregrind/x86/state.c
@@ -251,6 +251,7 @@
    vg_assert(VG_(is_valid_tid)(tid));
    tst = & VG_(threads)[tid];
 
+   if (0)
    VG_(printf)("get_thread_shadow_archreg(%d, %d)\n",
                tid, archreg);
 
@@ -270,6 +271,7 @@
 /* Return the baseBlock index for the specified shadow register */
 static Int shadow_reg_index ( Int arch )
 {
+   if (0)
    VG_(printf)("shadow_reg_index(%d)\n",
                arch);
    switch (arch) {

include/tool.h.base

diff --git a/include/tool.h.base b/include/tool.h.base
index d928b56..3e9a873 100644
--- a/include/tool.h.base
+++ b/include/tool.h.base
@@ -579,17 +579,17 @@
 /* ------------------------------------------------------------------ */
 /* Accessing archregs and their shadows */
 /* ToDo: is this still needed ? */
-extern UInt VG_(get_archreg)            ( UInt archreg );
-extern UInt VG_(get_thread_archreg)     ( ThreadId tid, UInt archreg );
+extern UInt VGA_(get_archreg)            ( UInt archreg );
+extern UInt VGA_(get_thread_archreg)     ( ThreadId tid, UInt archreg );
 
-extern UInt VG_(get_shadow_archreg)     ( UInt archreg );
-extern void VG_(set_shadow_archreg)     ( UInt archreg, UInt val );
-extern void VG_(set_shadow_eflags)      ( UInt val );
-extern Addr VG_(shadow_archreg_address) ( UInt archreg );
+extern UInt VGA_(get_shadow_archreg)     ( UInt archreg );
+extern void VGA_(set_shadow_archreg)     ( UInt archreg, UInt val );
 
-extern UInt VG_(get_thread_shadow_archreg) ( ThreadId tid, UInt archreg );
-extern void VG_(set_thread_shadow_archreg) ( ThreadId tid, UInt archreg,
-                                             UInt val );
+extern Addr VGA_(shadow_archreg_address) ( UInt archreg );
+
+extern UInt VGA_(get_thread_shadow_archreg) ( ThreadId tid, UInt archreg );
+extern void VGA_(set_thread_shadow_archreg) ( ThreadId tid, UInt archreg,
+                                              UInt val );
 
 /* ToDo: FIX */
 /* This is the Intel register encoding -- integer regs. */

memcheck/mc_main.c

diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
index a3f78bd..fedc4fe 100644
--- a/memcheck/mc_main.c
+++ b/memcheck/mc_main.c
@@ -760,12 +760,12 @@
 
 static void mc_post_reg_write(ThreadId tid, UInt reg)
 {
-   VG_(set_thread_shadow_archreg)( tid, reg, VGM_WORD_VALID );
+   VGA_(set_thread_shadow_archreg)( tid, reg, VGM_WORD_VALID );
 }
 
 static void mc_post_reg_write_clientcall(ThreadId tid, UInt reg, Addr f )
 {
-   VG_(set_thread_shadow_archreg)( tid, reg, VGM_WORD_VALID );
+   VGA_(set_thread_shadow_archreg)( tid, reg, VGM_WORD_VALID );
 }
 
 static void mc_pre_reg_read(CorePart part, ThreadId tid, Char* s, UInt reg,
@@ -783,7 +783,7 @@
    default: VG_(tool_panic)("Unhandled size in mc_pre_reg_read");
    }
 
-   if (VGM_WORD_VALID != (mask & VG_(get_thread_shadow_archreg)( tid, reg )) )
+   if (VGM_WORD_VALID != (mask & VGA_(get_thread_shadow_archreg)( tid, reg )) )
       MAC_(record_param_error) ( tid, 0, /*isReg*/True, /*isUnaddr*/False, s );
 }