Cachegrind/Callgrind: allow for cache sizes other than only powers of two
The number of sets, ie. number of cache lines divided by associativity,
and the cache line size still have to be powers of two.
This change is needed for default cache parameters used on some Intel
Core 2 and Atom processors.
Includes cachegrind manual update and explicit tests with 24KB D1/3MB L2
Reverts addition of 6MB warning to {cachegrind,callgrind}/tests/filter_stderr
Backporting to VALGRIND_3_4_BRANCH needs r8912
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@9080 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/callgrind/sim.c b/callgrind/sim.c
index 506ed9e..29f72bd 100644
--- a/callgrind/sim.c
+++ b/callgrind/sim.c
@@ -74,7 +74,6 @@
Bool sectored; /* prefetch nearside cacheline on read */
int sets;
int sets_min_1;
- int assoc_bits;
int line_size_bits;
int tag_shift;
UWord tag_mask;
@@ -195,7 +194,6 @@
c->sets = (c->size / c->line_size) / c->assoc;
c->sets_min_1 = c->sets - 1;
- c->assoc_bits = VG_(log2)(c->assoc);
c->line_size_bits = VG_(log2)(c->line_size);
c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
c->tag_mask = ~((1<<c->tag_shift)-1);
@@ -259,8 +257,7 @@
int i, j;
UWord *set;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -359,8 +356,7 @@
int i, j;
UWord *set, tmp_tag;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
/* This loop is unrolled for just the first case, which is the most */
/* common. We can't unroll any further because it would screw up */
@@ -407,7 +403,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = (a+size-1) >> c->tag_shift;
+ UWord tag2 = (a+size-1) & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cachesim_setref_wb(c, ref, set1, tag);
@@ -676,7 +672,7 @@
/* We use lower tag bits as offset pointers to cache use info.
* I.e. some cache parameters don't work.
*/
- if (c->tag_shift < c->assoc_bits) {
+ if ( (1<<c->tag_shift) < c->assoc) {
VG_(message)(Vg_DebugMsg,
"error: Use associativity < %d for cache use statistics!",
(1<<c->tag_shift) );
@@ -690,7 +686,7 @@
static __inline__
void cacheuse_update_hit(cache_t2* c, UInt high_idx, UInt low_idx, UInt use_mask)
{
- int idx = (high_idx << c->assoc_bits) | low_idx;
+ int idx = (high_idx * c->assoc) + low_idx;
c->use[idx].count ++;
c->use[idx].mask |= use_mask;
@@ -709,8 +705,7 @@
UWord *set, tmp_tag;
UInt use_mask;
- /* Shifting is a bit faster than multiplying */
- set = &(c->tags[set_no << c->assoc_bits]);
+ set = &(c->tags[set_no * c->assoc]);
use_mask =
c->line_start_mask[a & c->line_size_mask] &
c->line_end_mask[(a+size-1) & c->line_size_mask];
@@ -745,7 +740,7 @@
}
set[0] = tag | tmp_tag;
- cacheuse_L2_miss(c, (set_no << c->assoc_bits) | tmp_tag,
+ cacheuse_L2_miss(c, (set_no * c->assoc) | tmp_tag,
use_mask, a & ~c->line_size_mask);
return Miss;
@@ -756,7 +751,7 @@
{
UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1);
UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1);
- UWord tag = a >> c->tag_shift;
+ UWord tag = a & c->tag_mask;
/* Access entirely within line. */
if (set1 == set2)
@@ -765,7 +760,7 @@
/* Access straddles two lines. */
/* Nb: this is a fast way of doing ((set1+1) % c->sets) */
else if (((set1 + 1) & (c->sets-1)) == set2) {
- UWord tag2 = a >> c->tag_shift;
+ UWord tag2 = a & c->tag_mask;
/* the call updates cache structures as side effect */
CacheResult res1 = cacheuse_isMiss(c, set1, tag);
@@ -800,8 +795,7 @@
/* First case: word entirely within line. */ \
if (set1 == set2) { \
\
- /* Shifting is a bit faster than multiplying */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask] & \
L.line_end_mask[(a+size-1) & L.line_size_mask]; \
\
@@ -809,7 +803,7 @@
/* common. We can't unroll any further because it would screw up */\
/* if we have a direct-mapped (1-way) cache. */\
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -826,7 +820,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -842,7 +836,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
return update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
\
@@ -850,10 +844,10 @@
/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
} else if (((set1 + 1) & (L.sets-1)) == set2) { \
Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:L2 miss */ \
- set = &(L.tags[set1 << L.assoc_bits]); \
+ set = &(L.tags[set1 * L.assoc]); \
use_mask = L.line_start_mask[a & L.line_size_mask]; \
if (tag == (set[0] & L.tag_mask)) { \
- idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -868,7 +862,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -882,15 +876,15 @@
set[j] = set[j - 1]; \
} \
set[0] = tag | tmp_tag; \
- idx = (set1 << L.assoc_bits) | tmp_tag; \
+ idx = (set1 * L.assoc) + tmp_tag; \
miss1 = update_##L##_use(&L, idx, \
use_mask, a &~ L.line_size_mask); \
block2: \
- set = &(L.tags[set2 << L.assoc_bits]); \
+ set = &(L.tags[set2 * L.assoc]); \
use_mask = L.line_end_mask[(a+size-1) & L.line_size_mask]; \
tag2 = (a+size-1) & L.tag_mask; \
if (tag2 == (set[0] & L.tag_mask)) { \
- idx = (set2 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -905,7 +899,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tmp_tag; \
- idx = (set2 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
+ idx = (set2 * L.assoc) + (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
@@ -919,7 +913,7 @@
set[j] = set[j - 1]; \
} \
set[0] = tag2 | tmp_tag; \
- idx = (set2 << L.assoc_bits) | tmp_tag; \
+ idx = (set2 * L.assoc) + tmp_tag; \
miss2 = update_##L##_use(&L, idx, \
use_mask, (a+size-1) &~ L.line_size_mask); \
return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:L2_Hit; \
@@ -984,7 +978,7 @@
CacheModelResult cacheuse_L2_access(Addr memline, line_loaded* l1_loaded)
{
UInt setNo = (memline >> L2.line_size_bits) & (L2.sets_min_1);
- UWord* set = &(L2.tags[setNo << L2.assoc_bits]);
+ UWord* set = &(L2.tags[setNo * L2.assoc]);
UWord tag = memline & L2.tag_mask;
int i, j, idx;
@@ -993,7 +987,7 @@
CLG_DEBUG(6,"L2.Acc(Memline %#lx): Set %d\n", memline, setNo);
if (tag == (set[0] & L2.tag_mask)) {
- idx = (setNo << L2.assoc_bits) | (set[0] & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (set[0] & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1008,7 +1002,7 @@
set[j] = set[j - 1];
}
set[0] = tmp_tag;
- idx = (setNo << L2.assoc_bits) | (tmp_tag & ~L2.tag_mask);
+ idx = (setNo * L2.assoc) + (tmp_tag & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
@@ -1024,7 +1018,7 @@
set[j] = set[j - 1];
}
set[0] = tag | tmp_tag;
- idx = (setNo << L2.assoc_bits) | tmp_tag;
+ idx = (setNo * L2.assoc) + tmp_tag;
l1_loaded->dep_use = &(L2.use[idx]);
update_L2_use(idx, memline);
@@ -1380,22 +1374,15 @@
static
void check_cache(cache_t* cache, Char *name)
{
- /* First check they're all powers of two */
- if (-1 == VG_(log2)(cache->size)) {
+ /* Simulator requires line size and set count to be powers of two */
+ if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
+ (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
VG_(message)(Vg_UserMsg,
- "error: %s size of %dB not a power of two; aborting.",
- name, cache->size);
- VG_(exit)(1);
+ "error: %s set count not a power of two; aborting.",
+ name);
}
- if (-1 == VG_(log2)(cache->assoc)) {
- VG_(message)(Vg_UserMsg,
- "error: %s associativity of %d not a power of two; aborting.",
- name, cache->assoc);
- VG_(exit)(1);
- }
-
- if (-1 == VG_(log2)(cache->line_size)) {
+ if (-1 == VG_(log2)(cache->line_size)) {
VG_(message)(Vg_UserMsg,
"error: %s line size of %dB not a power of two; aborting.",
name, cache->line_size);