commit 1685c2887bec68514f0830a45c082bbcfe5fa3e2
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Thu Nov 06 09:22:05 2008 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Thu Nov 06 09:22:05 2008 +0000
tree d84dc7e25660240684ac82c0cfe847669ccdea7f
parent cb07be2425eee24e72932432059663e1e620e681

Tighten up decoding of isel instruction.


git-svn-id: svn://svn.valgrind.org/vex/trunk@1871 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest-ppc/toIR.c

diff --git a/priv/guest-ppc/toIR.c b/priv/guest-ppc/toIR.c
index 3b4e541..dcd04af 100644
--- a/priv/guest-ppc/toIR.c
+++ b/priv/guest-ppc/toIR.c
@@ -9479,7 +9479,9 @@
          /* Deal with some other cases that we would otherwise have
             punted on. */
          /* --- ISEL (PowerISA_V2.05.pdf, p74) --- */
-         if (IFIELD(theInstr, 1, 5) == 15) {
+         /* only decode this insn when reserved bit 0 (31 in IBM's
+            notation) is zero */
+         if (IFIELD(theInstr, 0, 6) == (15<<1)) {
             UInt rT = ifieldRegDS( theInstr );
             UInt rA = ifieldRegA( theInstr );
             UInt rB = ifieldRegB( theInstr );