- Fix up verbosity control.
- A quick bit of profiling and inlining of HReg functions as
a result.
git-svn-id: svn://svn.valgrind.org/vex/trunk@98 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/main/vex_main.c b/priv/main/vex_main.c
index 2baa405..cac3f77 100644
--- a/priv/main/vex_main.c
+++ b/priv/main/vex_main.c
@@ -149,14 +149,16 @@
/* Turn it into virtual-registerised code. */
vcode = iselBB ( irbb );
-LibVEX_ClearTemporary(True); return TransOK;
- vex_printf("\n-------- Virtual registerised code --------\n");
- for (i = 0; i < vcode->arr_used; i++) {
- ppInstr(vcode->arr[i]);
+ if (vex_verbosity > 0) {
+ vex_printf("\n-------- Virtual registerised code --------\n");
+ for (i = 0; i < vcode->arr_used; i++) {
+ vex_printf("%3d ", i);
+ ppInstr(vcode->arr[i]);
+ vex_printf("\n");
+ }
vex_printf("\n");
}
- vex_printf("\n");
/* Register allocate. */
rcode = doRegisterAllocation ( vcode, available_real_regs,
@@ -165,15 +167,19 @@
genSpill, genReload,
ppInstr, ppReg );
- vex_printf("\n-------- Post-regalloc code --------\n");
- for (i = 0; i < rcode->arr_used; i++) {
- ppInstr(rcode->arr[i]);
+ if (vex_verbosity > 0) {
+ vex_printf("\n-------- Post-regalloc code --------\n");
+ for (i = 0; i < rcode->arr_used; i++) {
+ vex_printf("%3d ", i);
+ ppInstr(rcode->arr[i]);
+ vex_printf("\n");
+ }
vex_printf("\n");
}
- vex_printf("\n");
/* Assemble, etc. */
- LibVEX_ClearTemporary(True);
+ // LibVEX_ClearTemporary(True);
+ LibVEX_ClearTemporary(False);
return TransOK;
}